JPS60189265A - Thin film field effect semiconductor device - Google Patents
Thin film field effect semiconductor deviceInfo
- Publication number
- JPS60189265A JPS60189265A JP59044334A JP4433484A JPS60189265A JP S60189265 A JPS60189265 A JP S60189265A JP 59044334 A JP59044334 A JP 59044334A JP 4433484 A JP4433484 A JP 4433484A JP S60189265 A JPS60189265 A JP S60189265A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- gate electrode
- region
- film
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000010409 thin film Substances 0.000 title claims abstract description 13
- 230000005669 field effect Effects 0.000 title claims abstract description 7
- 239000010408 film Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 235000013372 meat Nutrition 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、シリコンを主成分とする非単結晶半導体を用
いた薄膜電界効果トランジスタ（ＴＰＴ）に関する。シ
リコンを主成分とした非単結晶半導体ＴＦＴは、安価な
ガラス基板上に比較的低い温度で作製出来、すぐれたオ
ン抵抗・オフ抵抗比を有するため、液晶パネルの駆動ス
イ・ノチングアレー等への応用が有望である。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film field effect transistor (TPT) using a non-single crystal semiconductor mainly composed of silicon. Non-single-crystal semiconductor TFTs, whose main component is silicon, can be fabricated on inexpensive glass substrates at relatively low temperatures and have excellent on-resistance/off-resistance ratios, making them suitable for applications such as switching and notching arrays for driving liquid crystal panels. is promising.
従来例の構成とその問題点
ＴＰＴを画像表示装置やイメージセンサ等のスイッチン
グ素子等として使用する場合には、必然的に外光が入射
する還境下に於いて使用される。Conventional Structure and Problems When the TPT is used as a switching element for an image display device, an image sensor, etc., it is inevitably used in a closed environment where external light is incident.
シリコンを主成分とする非単結晶半導体は、すぐれた光
伝導を有する材料でもあるので、外光がＴＰＴのチャン
ネル部に入射することによりオフ抵抗が減少し、オン抵
抗・オフ抵抗比が大巾に劣イビする欠点を有した。以下
、シリコンを主成分とする非単結晶半導体として水素化
非晶質シリコン（ａ−３ｉ：Ｈ）半導体を代表例として
述べる。Non-single crystal semiconductors whose main component is silicon are also materials with excellent photoconductivity, so when external light enters the channel portion of the TPT, the off-resistance decreases, and the on-resistance/off-resistance ratio widens. It had the disadvantage of being inferior to that of the previous model. Hereinafter, a hydrogenated amorphous silicon (a-3i:H) semiconductor will be described as a representative example of a non-single crystal semiconductor mainly composed of silicon.
第１図、第２図にａ−Ｓｉ：Ｈ半導体層を用いた典型的
な薄膜電界効果トランジスタ（ＴＰＴ ）の従来例の主
要平面図を示す。FIGS. 1 and 2 show principal plan views of a conventional example of a typical thin film field effect transistor (TPT) using an a-Si:H semiconductor layer.
ＴＰＴの製造工程を下記に示す。先ずガラス等の基板上
にＣｒ等の金属を蒸着しゲート電極及びゲートバス配線
１（１部）となるべき部分を残してエツチングする。次
にプラズマＣＶＤ法等によシ窒化シリコン膜を０．１〜
０．５μｍ 、’ ａ −Ｓ ｉ ：Ｈ膜を０．１〜０
．５ ｐ ｍ 、 ｎ＋にドープしたａ−８ｔ：Ｈ膜を
数百人程度連続に堆積する。次にＴＰＴとして残すべき
ａ−８ｉ：Ｈ膜の部分４（−・−で囲れた部分）をレジ
ストで被覆し、残余の部分のｎ＋ａ−８ｉ：Ｈをエツチ
ング除去する。次にＡ１等ＣＤ金属を蒸着しドレイン電
極２、ソース電極とソースバス配線３（り不 部）をバ
ターニングスル。The manufacturing process of TPT is shown below. First, a metal such as Cr is deposited on a substrate such as glass and etched, leaving only a portion that will become the gate electrode and gate bus wiring 1 (one part). Next, a silicon nitride film of 0.1~
0.5μm, 'a-S i :H film 0.1~0
．． Several hundred 5 pm, n+ doped a-8t:H films are continuously deposited. Next, portion 4 of the a-8i:H film to be left as TPT (the portion surrounded by -.-) is covered with resist, and the remaining portion of n+a-8i:H is removed by etching. Next, deposit a CD metal such as A1 and pattern the drain electrode 2, source electrode, and source bus wiring 3 (notch part).
更にＡｌ電極２．３をマスクにして両電極間に延在する
ｎ”ａ−８ｔ：Ｈ層を除去することによりＴＰＴが完成
する。Furthermore, the TPT is completed by removing the n''a-8t:H layer extending between both electrodes using the Al electrode 2.3 as a mask.
これらａ−８ｉ：ＨＴＦＴに於いては、電極の段差部に
於けるゲート絶縁膜の耐圧不良や、ゲート電極１とソー
ス・ドレイン電極２，３間に於けるゲート絶縁膜の耐工
、ノチング不良によるゲートリーク電流及びゲート電極
１とソース・ドレイン電極２．３間のショート率を低減
することを目的として本出願人の特願昭５７−１１９４
６０号に示されている以下の様な構造が採用されていた
。These a-8i: In HTFT, breakdown voltage failure of the gate insulating film at the step part of the electrode, failure of the gate insulating film between the gate electrode 1 and the source/drain electrodes 2 and 3, and notching failure. The present applicant's Japanese Patent Application No. 1194/1983 aims to reduce the gate leakage current and the short circuit rate between the gate electrode 1 and the source/drain electrodes 2.3.
The following structure shown in No. 60 was adopted.
すなわち、この構造は、第１図、第２図に示すように、
ゲート電極１とソース・ドレイン電極２゜３が重なり合
う領域（淵部）は、必子半導体膜層がバターニングされ
た領域（＝・−・−で囲まれた領域）に含まれるＴＰＴ
構造である。しかしながら、この場合ソース電極３とド
レイン電極２の間に存在する半導体層は全てＴＰＴのチ
ャンネル領域を形成し、第１図、第２図で示す６の部分
にはゲート電極側からの光入射に際し光伝導性を示しＴ
ＰＴのＯＦＦ抵抗を低下させてしまう欠点があった。That is, this structure, as shown in FIGS. 1 and 2,
The region where the gate electrode 1 and the source/drain electrodes 2 and 3 overlap (the edge) is TPT included in the region where the essential semiconductor film layer is patterned (the region surrounded by =・−・−).
It is a structure. However, in this case, the semiconductor layer existing between the source electrode 3 and the drain electrode 2 all forms the channel region of the TPT, and the portion 6 shown in FIGS. 1 and 2 is exposed to light incident from the gate electrode side. T exhibits photoconductivity
This had the disadvantage of lowering the PT's OFF resistance.
発明の目的
本発明は、これら従来のＴＰＴの欠点を改善するだめに
なされたものである。つま９、本発明は外部からの照射
光を完全にじゃへいすると共に、層間絶縁不良を低減さ
せる２つの目的を十分に達成出来るａ−３ｉ：ＨＴＦＴ
を提供する。OBJECTS OF THE INVENTION The present invention has been made to improve these drawbacks of conventional TPTs. Bottom line 9. The present invention completely blocks external irradiation light and can fully achieve the two objectives of reducing interlayer insulation defects.a-3i:HTFT
I will provide a.
発明の構成
本発明の装置は、透り基板の１主面上に、第１の電極と
絶縁膜を介して半導体薄膜の存在する第１の領域を有し
、前記半導体薄膜とオーミック接触をなす第２．第３の
電極を有する薄膜電界効果型トランジスタの前記基板の
主面上への投影図に於いて、前記第１の電極と第２．第
３の電極が重なり合う第２の領域は必ず前記半導体薄膜
が存在し、かつ前記第１の領域の輪郭を成す線のうち、
前記第２の電極と第３の電極を結ぶ全ての線が前記第１
の電極上を一度以上横切ることを特徴とするものである
。Structure of the Invention The device of the present invention has a first region on one principal surface of a transparent substrate, in which a semiconductor thin film is present via a first electrode and an insulating film, and makes ohmic contact with the semiconductor thin film. Second. In a projection view onto the principal surface of the substrate of a thin film field effect transistor having a third electrode, the first electrode and the second . The semiconductor thin film is always present in the second region where the third electrode overlaps, and among the lines forming the outline of the first region,
All lines connecting the second electrode and the third electrode are connected to the first electrode.
It is characterized by crossing over the electrode more than once.
実施例の説明
以下、本発明の構成をＴＰＴの要部平面図である第３図
、第４図を用いて詳細に説明する。DESCRIPTION OF EMBODIMENTS The structure of the present invention will be described in detail below with reference to FIGS. 3 and 4, which are plan views of main parts of the TPT.
第３図、第４図に於いて、従来ＴＰＴと同一構成要素に
対しては第１図、第２図で用いた番号。In FIGS. 3 and 4, the same numbers as in FIGS. 1 and 2 are used for the same components as in the conventional TPT.
記号を用いている。ＴＰＴの製造工程は従来ＴＰＴと同
様である。It uses symbols. The manufacturing process for TPT is similar to that for conventional TPT.
本発明の特徴は、第３図、第４図に於いてａ−８ｔ ：
Ｈ膜のバターニングして残される領域（−・−・−で
囲まれる部分）が、ゲート電極１とソース・ドレイン電
極２．３の重シ合う領域（フタ部）を必ず包含し、且つ
、ａ−８ｔ：Ｈ膜のバターニングして残される領域の輪
郭となる線（−・−・−）の内ソース電極３とドレイン
電極２を結ぶ線（ＡＢ）、（ＣＤ）が必ずゲート電極１
上を横切る構成を取るところにある。The features of the present invention are as shown in FIGS. 3 and 4.
The region left after patterning the H film (the part surrounded by -. a-8t: Among the lines (-・-・-) that form the outline of the area left after patterning the H film, the lines (AB) and (CD) connecting the source electrode 3 and drain electrode 2 are always the gate electrode 1.
It consists in taking a configuration that crosses the top.
本発明のＴＰＴに、ゲート電極１側から光が入射した場
合、ソース電極３とドレイン電極２の間に存在する半導
体層（チャンネル領域）の内黒くぬりつぶしだ部分は光
伝導によりソース電極３又はドレイン電極２とほぼ同電
位になるが、従来のＴＰＴ（第１図、第２図）とは異な
シ、ソース電極３とドレイン電極２間に半導体層はゲー
ト電極領域をはずれて延在せず、光伝導性を示す半導体
層がソース・ドレイン電極２，３間を結ぶことがないの
で、ＴＰＴの光伝導によるＯＦＦ抵抗の低下にはつなが
らない。When light enters the TPT of the present invention from the gate electrode 1 side, the solid black part of the semiconductor layer (channel region) existing between the source electrode 3 and the drain electrode 2 is exposed to the source electrode 3 or the drain electrode by photoconduction. The potential is almost the same as that of the electrode 2, but unlike conventional TPT (Figs. 1 and 2), the semiconductor layer does not extend beyond the gate electrode region between the source electrode 3 and the drain electrode 2. Since the semiconductor layer exhibiting photoconductivity does not connect the source/drain electrodes 2 and 3, the OFF resistance does not decrease due to photoconduction of TPT.
以下実施例を用いて詳細に説明する。This will be explained in detail below using examples.
まず従来の構成第６図、第６図を述べ、本発明との差異
を明らかにしつつ第７図の実施例について説明する。第
６図は従来のＴＰＴの要部平面図であり、１はゲート電
極及びゲートバス配線、２はドレイン電極、３はソース
電極及びソースバス配線である。４は島状に選択的に残
されたａ−８ｉ半導体膜であり、ソース電極、ソースバ
ス電極３及びドレイン電極２の各々とゲート電極すなわ
ちゲートバス電極１の重シ合う領域（２重余Ｉ線の部分
）は必ず含む様に残されている。この場合のドレイン電
極２の端（匂はゲート電極１の端（Ｇ）よシチャンネル
領域に対して外側に位置し、ａ−８ｔＯ島領域４の端（
ト）はその間に位置する様に設計されている。第６図は
第６図に於けるＩ−Ｉ’線の部分の断面図である。々お
、第６図は主要部のみを示している。透明基板６上に形
成されたゲート電極１（この断面図に於いては出現しな
いので点線で位置関係だけを示す。）上にチノ化シリコ
ン膜６及びａ−８ｉ 半導体膜４を連続して堆積し、ａ
−３ｔ 半導体膜４を不必要な部分をエツチング除去し
て島状に残し、ソース及びドレイン電極２゜ｐとなる導
体層を選択的に形成してＴＰＴが製造される。更にポリ
イミド等の絶縁層７を介して光がチャンネル部外へ入射
するのを防ぐだめの光じゃへい層８を設置して、外光に
対して安定であるａ−３ｉＴＦＴが出来上がる。この様
な従来の例の場合では上部方向からの入射光９に対して
は安定であるが、下部方向からの入射光１０はチャンネ
ル部の一部に光が入射して、ａ−３ｉＴＦＴの０Ｎ−Ｏ
ＦＦ％性は非常に劣化する。First, the conventional configuration shown in FIGS. 6 and 6 will be described, and the embodiment shown in FIG. 7 will be explained while clarifying the differences from the present invention. FIG. 6 is a plan view of main parts of a conventional TPT, in which 1 is a gate electrode and gate bus wiring, 2 is a drain electrode, and 3 is a source electrode and source bus wiring. Reference numeral 4 denotes an a-8i semiconductor film selectively left in the form of an island, where each of the source electrode, source bus electrode 3, and drain electrode 2 overlaps with the gate electrode, i.e., gate bus electrode 1 (double overlap I). The line part) is left in such a way that it is always included. In this case, the end of the drain electrode 2 (the end (G) of the gate electrode 1 is located outside of the channel region, and the end of the a-8tO island region 4 (
) is designed to be located between them. FIG. 6 is a sectional view taken along line II' in FIG. 6. Please note that Figure 6 shows only the main parts. A silicon tinide film 6 and an a-8i semiconductor film 4 are successively deposited on a gate electrode 1 formed on a transparent substrate 6 (does not appear in this cross-sectional view, so only the positional relationship is indicated by dotted lines). S,a
-3t A TPT is manufactured by etching away unnecessary portions of the semiconductor film 4 and leaving it in an island shape, and selectively forming a conductor layer that will become the source and drain electrodes 2°p. Further, a light shielding layer 8 for preventing light from entering outside the channel portion through an insulating layer 7 made of polyimide or the like is provided to complete an a-3i TFT that is stable against external light. In the case of such a conventional example, it is stable with respect to the incident light 9 from the upper direction, but the incident light 10 from the lower direction enters a part of the channel part, and the 0N of the a-3i TFT -O
The FF% property deteriorates significantly.
以上の欠点を解消出来る本発明の実施例を第７図に示す
。本発明の実施例ではドレイン電極２の端（Ｌ）はゲー
ト電極１の端（Ｔ）よシチャンネル領域側に位置し、ａ
−３ｔ 膜の島領域４の端は、（イ）と（財）の部分か
らなり、（イ）はドレイン電極の端（Ｌ）とゲート電極
の端（Ｊ）の間に位置し、儂はゲート電極の端Ｕ）に対
してチャンネル領域より外側に位置する様に形成される
。つまり、ｒＴＦＴの透影図に於いて、ゲート電極とソ
ース・ソースノ（スミ極又はドレイン電極が重シあう領
域に必ずａ−３ｉ 半導体膜が存在し且つ、ａ−Ｓｉ半
導体膜の輪郭を成す線のうち、ソース電極とドレイン電
極を結ぶ線が必ずゲート電極上を一度以上横ぎる」様な
構成に化は見られず、なおかつ、ソース・ドレイン電極
とゲート電極の重り合う部分に必ずａ−８ｉ 膜が残さ
れているので、ゲートリーク等の不良の少ない安定した
ＴＰＴを得ることが出来る。FIG. 7 shows an embodiment of the present invention that can eliminate the above drawbacks. In the embodiment of the present invention, the end (L) of the drain electrode 2 is located closer to the channel region than the end (T) of the gate electrode 1, and a
-3t The end of the island region 4 of the film consists of parts (a) and (goods), where (a) is located between the end of the drain electrode (L) and the end of the gate electrode (J), and the end of the film is It is formed so as to be located outside the channel region with respect to the end U) of the gate electrode. In other words, in the perspective view of an rTFT, there is always an a-3i semiconductor film in the area where the gate electrode and the source/source electrode overlap, and there is a line that forms the outline of the a-Si semiconductor film. Among them, there is no structure in which the line connecting the source electrode and the drain electrode always crosses over the gate electrode more than once, and there is no case where the line connecting the source electrode and the drain electrode always crosses the gate electrode more than once, and there is always an a-8i line in the overlapping part of the source/drain electrode and the gate electrode. Since the film remains, a stable TPT with few defects such as gate leakage can be obtained.
発明の効果
ゲート電極側からのチャンネル領域への入射光入射する
光をしゃへいする構成を付加すれば、外光が入射する還
境下に於いて使用しても、光伝導性によるＯＦＦ抵抗の
劣化はほとんど皆無になり非常に効果的である。Effects of the invention By adding a structure that shields light incident on the channel region from the gate electrode side, deterioration of OFF resistance due to photoconductivity can be prevented even when used in a closed environment where external light is incident. is almost completely eliminated, making it extremely effective.
第１図、第２図、第５図は従来のＴＰＴの要部平面図、
第３図、第４図、第７図は本発明の実施例のＴＰＴの要
部平面図、第６図は第５図のＩ −Ｉ′線の断面図であ
る。
１・・・・・・ゲート電極、２・・・・・・ドレイン電
極、３・・・・・・ソース電極及びソースバス配線、４
・・・・・ａ −３ｔ：Ｈ膜、６・・・・・・ゲート絶
縁膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第 ２ 図
第３１１
第４図
第 ５ 肉
第６図Figures 1, 2, and 5 are plan views of main parts of conventional TPT,
3, 4, and 7 are plan views of essential parts of a TPT according to an embodiment of the present invention, and FIG. 6 is a sectional view taken along line I--I' in FIG. 5. 1... Gate electrode, 2... Drain electrode, 3... Source electrode and source bus wiring, 4
...a-3t: H film, 6...gate insulating film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 311 Figure 4 Figure 5 Meat Figure 6
Claims (1)
導体薄膜の存在する第１の領域を有し、前記半導体薄膜
とオーミック接触をなす第２．第３の電極を有する薄膜
電界効果型トランジスタの前記基板の主面上への投影図
に於いて、前記第１の電極と第２．第３の電極が重なり
合う第２の領域は必ず前記半導体薄膜が存在し、かつ前
記第１の領域の輪郭を成す線のうち、前記第２の電極と
第３の電極を結ぶ全ての線が前記第１の電極上を一度以
上横切ることを特徴とする薄膜電界効果型半導体装置。A first region in which a semiconductor thin film is present is provided on one main surface of the transparent substrate via a first electrode and an insulating film, and a second region is in ohmic contact with the semiconductor thin film. In a projection view onto the principal surface of the substrate of a thin film field effect transistor having a third electrode, the first electrode and the second . The semiconductor thin film is always present in the second region where the third electrode overlaps, and among the lines forming the outline of the first region, all the lines connecting the second electrode and the third electrode are in the second region where the third electrode overlaps. A thin film field effect semiconductor device characterized in that it crosses over a first electrode once or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59044334A JPS60189265A (en) | 1984-03-08 | 1984-03-08 | Thin film field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59044334A JPS60189265A (en) | 1984-03-08 | 1984-03-08 | Thin film field effect semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60189265A true JPS60189265A (en) | 1985-09-26 |
| JPH0457113B2 JPH0457113B2 (en) | 1992-09-10 |
Family
ID=12688613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59044334A Granted JPS60189265A (en) | 1984-03-08 | 1984-03-08 | Thin film field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60189265A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0647971A1 (en) * | 1993-04-23 | 1995-04-12 | Kabushiki Kaisha Toshiba | Thin film transistor and display using the transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154289A (en) * | 1978-05-26 | 1979-12-05 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor array |
| JPS58102552A (en) * | 1981-12-14 | 1983-06-18 | Fujitsu Ltd | Thin film transistor matrix array |
| JPS58190042A (en) * | 1982-04-28 | 1983-11-05 | Toshiba Corp | Thin film semiconductor device |
| JPS599941A (en) * | 1982-07-08 | 1984-01-19 | Matsushita Electric Ind Co Ltd | Thin-film semiconductor device and its manufacture |
-
1984
- 1984-03-08 JP JP59044334A patent/JPS60189265A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154289A (en) * | 1978-05-26 | 1979-12-05 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor array |
| JPS58102552A (en) * | 1981-12-14 | 1983-06-18 | Fujitsu Ltd | Thin film transistor matrix array |
| JPS58190042A (en) * | 1982-04-28 | 1983-11-05 | Toshiba Corp | Thin film semiconductor device |
| JPS599941A (en) * | 1982-07-08 | 1984-01-19 | Matsushita Electric Ind Co Ltd | Thin-film semiconductor device and its manufacture |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5811846A (en) * | 1993-04-03 | 1998-09-22 | Kabushiki Kaisha Toshiba | Thin-film transistor and display device using the same |
| EP0647971A1 (en) * | 1993-04-23 | 1995-04-12 | Kabushiki Kaisha Toshiba | Thin film transistor and display using the transistor |
| EP0647971A4 (en) * | 1993-04-23 | 1995-05-03 | ||
| US5563432A (en) * | 1993-04-23 | 1996-10-08 | Kabushiki Kaisha Toshiba | Thin-film transistor and display device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0457113B2 (en) | 1992-09-10 |
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