JPS60185409A - Muting circuit - Google Patents
Muting circuitInfo
- Publication number
- JPS60185409A JPS60185409A JP60006584A JP658485A JPS60185409A JP S60185409 A JPS60185409 A JP S60185409A JP 60006584 A JP60006584 A JP 60006584A JP 658485 A JP658485 A JP 658485A JP S60185409 A JPS60185409 A JP S60185409A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- capacitor
- voltage
- output
- muting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
- Noise Elimination (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、電源電圧オン、オフ時に動作するミューティ
ング回路に関し、特にミコーディング出力を得るための
回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a muting circuit that operates when a power supply voltage is turned on or off, and particularly to a circuit for obtaining a micoding output.
従来、ステレオ増幅器等の音声信号増幅器において電源
オ′ン、オフ時に発生ずる過渡音を防止するためのミコ
ーティング回路には電源スィッチとは別個のスイッチを
設置プたものや第1図の回路に示す全電子回路等が用い
られていた。すなわち、第1図においてC1はミューテ
ィング時定数用コンデンサ、C2は積分コンデンサであ
る。[・ランスTに電源が投入されると1〜ランスTの
二次側にはダイオードDにより負の直流電圧が発生し、
抵抗R3、R4を介して1ヘランジスタQ1のベースは
充分低い電位に保たれ、1〜ランジスタQ1はオフとな
り、前記ミコーティング時定数用コンデンサC1が充電
され■点電位は抵抗R1とより決まる時定数により立」
二る。ミューティング出力は0点より検出し、所定の電
圧に立上った時に回路を動作させる。又、電源オフ時に
は負の直流電圧はなくなり、積分コンデンサC2は抵抗
R2、R3、R4を介して放電される。この放電電流に
よりトランジスタQ1はオンになり時定数用コンデンサ
C1は直ちに放電され過渡音を防止できる。Conventionally, in audio signal amplifiers such as stereo amplifiers, a separate switch from the power switch was installed in the mi-coating circuit to prevent transient noise that occurs when the power is turned on and off, or the circuit shown in Figure 1 was used. The all-electronic circuit shown was used. That is, in FIG. 1, C1 is a muting time constant capacitor, and C2 is an integrating capacitor. [・When the power is turned on to the lance T, a negative DC voltage is generated on the secondary side of the lance T by the diode D,
The base of the transistor Q1 is kept at a sufficiently low potential through the resistors R3 and R4, the transistors Q1 and Q1 are turned off, and the capacitor C1 for the micoating time constant is charged, and the potential at point 2 is determined by the time constant determined by the resistor R1. "Stand by"
Two. The muting output is detected from the 0 point, and the circuit is activated when it rises to a predetermined voltage. Further, when the power is turned off, the negative DC voltage disappears, and the integrating capacitor C2 is discharged via the resistors R2, R3, and R4. This discharge current turns on the transistor Q1, and the time constant capacitor C1 is immediately discharged, thereby preventing transient noise.
しかし、第1図回路においては全て電子回路であるため
、信頼性はあるが時定数用及び積分用に各々1個のコン
デンサを必要とし、時定数用コンデン膏すには電源オン
から回路が動作するまで数秒を必要とするため人容■の
ものが必要であり、又電源オフ時の作動時間も十分短か
いとはいえなかった。又、別個にスイッチを設りたもの
はコンデンサを2個必要とするのは無論のこと、該スイ
ッチの容量、耐久性、取付位置の選定等種々の問題がイ
Lじていた。However, since the circuit in Figure 1 is entirely electronic, it is reliable but requires one capacitor each for time constant and integration, and the circuit operates from the power on for the time constant capacitor. Since it takes several seconds for the power to turn off, a device with a human body size is required, and the operating time when the power is turned off is not sufficiently short. In addition, a device with a separate switch not only requires two capacitors, but also has various problems such as the capacity, durability, and selection of the mounting position of the switch.
本発明は」ニ述の問題点を解消したものであり、以下実
施例を図面を参照して説明する。The present invention solves the above-mentioned problems, and embodiments thereof will be described below with reference to the drawings.
第2図は本発明の動作原理を示す図であり、第2図にお
いて1はコンデンサCを充電する定電流源、3は0点に
加えられた電源電圧のLロレベルを検知し電源周波数と
比較し充分短かい期間パルスを発生させるパルス発生回
路、2は該パルス発生回路3からの信号により動作する
ゲート回路であり、一端が抵抗Rを介して0点に、他端
が接地点に接続されている。Fig. 2 is a diagram showing the operating principle of the present invention. In Fig. 2, 1 is a constant current source that charges the capacitor C, and 3 detects the L/L level of the power supply voltage applied to the 0 point and compares it with the power supply frequency. A pulse generating circuit 2 generates a pulse for a sufficiently short period of time, and 2 is a gate circuit operated by a signal from the pulse generating circuit 3. One end is connected to the 0 point via a resistor R, and the other end is connected to a ground point. ing.
電源がオンとなり、0点に第3図(イ)の電源電圧が加
えられた時、パルス発生回路3から−っ目のパルスが出
力され、グー1〜回路2はオンとなる。その後はパルス
発生回路3により0点出力電圧は第3図(ロ)のように
電源周波数の2倍の周波数でパルスが発生ずる。When the power supply is turned on and the power supply voltage shown in FIG. 3(A) is applied to the 0 point, the -th pulse is output from the pulse generating circuit 3, and the circuits 1 to 2 are turned on. Thereafter, the pulse generating circuit 3 generates a pulse at a frequency twice the power supply frequency for the zero point output voltage as shown in FIG. 3(b).
一方へ点電位は定電流源1により直流電圧+VCCまで
l1fnff線的に立上るが、前記ゲート回路2により
電源電圧OV時に抵抗Rを介して極めて短時間に放電が
行なわれるため第3図(ハ)のようになる。ここでミコ
ーティングレベルは0点より検出され、動作時間t1に
より決定される電圧V1以上になると所定の回路が動作
するように設定されている。(tiは上)ホのように通
常数秒である)電源が第3図13時にオフになった場合
、パルス3−
発生回路3はその後も所定時間電源が供給されているの
で、動作状態を維持しており、電源のゼロボルトを検出
して信号を出力している。この期間中はグー1〜回路2
がオン状態となっており、コンデンリーCの電荷は抵抗
「くを通して急速に放電される。On the other hand, the point potential rises linearly to the DC voltage +VCC due to the constant current source 1, but since the gate circuit 2 causes discharge to occur in a very short time via the resistor R when the power supply voltage is OV, as shown in FIG. )become that way. Here, the miscoating level is detected from the 0 point, and a predetermined circuit is set to operate when the voltage reaches or exceeds the voltage V1 determined by the operating time t1. (Ti is usually several seconds as shown in above) If the power is turned off at 13 in Figure 3, the pulse 3- generating circuit 3 will continue to be powered for a predetermined period of time, so it will maintain its operating state. It detects zero volts of the power supply and outputs a signal. During this period, Goo 1~Circuit 2
is in the on state, and the charge on the capacitor C is rapidly discharged through the resistor.
第4図は本発明の実施例であり、第2図と同一部分は同
一符号を記しである。1a、1bは各々コンデンサCを
充電するための定電流源、4は信号発生回路で■熱電位
を検出し、所定レベルにて信号を発生するレベル検出回
路5及び該レベル検出回路5の出力により1〜リガされ
信号を発生するシュミット回路6より成っている。又、
2a、21)は各々前記レベル検出回路5及びシュミッ
ト回路6の出力信じにより動作づ−るゲート回路である
。FIG. 4 shows an embodiment of the present invention, and the same parts as in FIG. 2 are denoted by the same reference numerals. 1a and 1b are constant current sources for charging the capacitor C, and 4 is a signal generation circuit. It consists of Schmitt circuits 1 to 6 which generate triggered signals. or,
Reference numerals 2a and 21) are gate circuits which operate depending on the outputs of the level detection circuit 5 and Schmitt circuit 6, respectively.
電源オン時には定電流源1aによりコンデンサCを充電
させ、レベル検出回路5にて■熱電位を検出し、ミコー
ティング時間t1により決定される電圧V1になった時
、レベル検出回路5及びシュミツ1〜回路6より出力信
号が発生し、ゲート回路2−4 =
a、2bを略同時に動作させる。従ってゲート回路2に
より、コンデンサCは定電流源1aの他に定電流源1b
からも充電が行われ、更に大きい傾斜により立上る。ま
た、グー1〜回路2bが動作することにJ:リパルス発
YV回路3の出力〔第5図(ロ)〕はゲート回路2に入
ツノされることになり、上述のように電源電圧OV時に
放電を行いながら直流電圧+VCCまで立上る〔第5図
(ハ)〕。電源オフ時にはレベル検出回路5の出力はミ
ューティングレベル電圧V1以下になった場合発生され
、ゲート回路2aが開放されるので定電流源1bからの
電流は流れなくなるが、シュミット回路6はレベル検出
回路5の出力がある設定レベルに低下するまでヒステリ
ス特性により出力が発生ずるため、ゲート回路2bはミ
ューティングレベル電圧v1以下になっても動作し、従
ってパルス発生回路3の信号はグー1〜回路2に入力さ
れ上)ホのにうにコンデンサCの放電が行われる。尚第
4図において、シュミット回路6の代わりにフリップフ
ロップで置き換えても同様な動作をする。When the power is turned on, the capacitor C is charged by the constant current source 1a, and the level detection circuit 5 detects the thermal potential. An output signal is generated from the circuit 6, and the gate circuits 2-4 = a and 2b are operated almost simultaneously. Therefore, by gate circuit 2, capacitor C is connected to constant current source 1b in addition to constant current source 1a.
Charging is also carried out from the top, and it rises due to an even larger slope. In addition, when circuits 1 to 2b operate, the output of the repulse YV circuit 3 [Fig. 5 (b)] is input to the gate circuit 2, and as described above, when the power supply voltage is While discharging, the DC voltage rises to +VCC [Figure 5 (c)]. When the power is turned off, the output of the level detection circuit 5 is generated when the muting level voltage V1 or less is reached, and the gate circuit 2a is opened, so no current flows from the constant current source 1b, but the Schmitt circuit 6 is used as a level detection circuit. Since the output is generated due to the hysteresis characteristic until the output of circuit 5 drops to a certain set level, the gate circuit 2b operates even when the muting level voltage v1 is lower than that, and therefore the signal of the pulse generation circuit 3 is (above), the capacitor C is discharged. In FIG. 4, the Schmitt circuit 6 may be replaced with a flip-flop to perform the same operation.
以−トの如く本発明によれば、スイッチ等機械的手段は
使用しない純電子式であるため信頼性が向−にされるば
かりでなく、電源オン時の定数回路用コンデンサ及び電
源27時の積分回路用コンデンサ1つで共有できるので
コスト的に安価になり、該コンデンサ以外は全てICに
組込むことができ装量の小形化も容易どなる。又、該コ
ンデンサは積分回路用どしては小容量であることが望ま
しく、時定数用どして考えた場合でも立上りの傾斜は定
電流源の電流値を可変することにより変えられるので、
従来と比べ大容量コンデンサを使用しなくてもよい。更
に、前記パルス発生回路のパルス幅を電源周波数と比べ
十分狭くできない時、充電時の立上り電圧が放電時の立
下り電圧より小さくなりコンデンサ充電電圧が立上らな
い場合があるが、本発明によればミューティング電圧ま
では信号発生回路4及びゲート回路21)によりパルス
はグー1〜回路2に入力されないため、上)ボのような
不都合は解消される。As described above, according to the present invention, since it is a purely electronic system that does not use mechanical means such as switches, reliability is not only improved, but also the constant circuit capacitor when the power is turned on and the Since one integral circuit capacitor can be used in common, the cost is low, and everything except the capacitor can be incorporated into the IC, making it easy to reduce the size of the integrated circuit. In addition, it is desirable that the capacitor has a small capacity for use in an integrating circuit, and even when used as a time constant, the slope of the rise can be changed by varying the current value of the constant current source.
There is no need to use large capacity capacitors compared to conventional methods. Furthermore, when the pulse width of the pulse generating circuit cannot be narrowed sufficiently compared to the power supply frequency, the rising voltage during charging may become smaller than the falling voltage during discharging, and the capacitor charging voltage may not rise. According to this, the signal generating circuit 4 and the gate circuit 21) do not input pulses to the circuits 1 to 2 until the muting voltage is reached, so the inconvenience described in (a) above is eliminated.
第1図は従来のミコーディング回路、第2図は本発明の
動作原理を示す回路、第3図は第2図の動作波形、第4
図は本発明の実施例、第5図は第4図の動作波形である
。
1.1a、1b・・・・・・定電流源
2.2a 、2b・・・・・・グー1−回路3・・・・
・・パルス発生回路 4・・・・・・信号発生回路5・
・・・・・レベル検出回路 6・・・・・・シュミツ1
ル回路特許出願人
パイオニア株式会社
7−
十Vcc
8−
第3囮Fig. 1 shows a conventional micoding circuit, Fig. 2 shows a circuit showing the operating principle of the present invention, Fig. 3 shows the operating waveforms of Fig. 2, and Fig. 4 shows a circuit showing the operating principle of the present invention.
The figure shows an embodiment of the present invention, and FIG. 5 shows the operating waveforms of FIG. 4. 1.1a, 1b... Constant current source 2.2a, 2b... Goo 1-circuit 3...
...Pulse generation circuit 4...Signal generation circuit 5.
...Level detection circuit 6 ...Schmidts 1
Circuit patent applicant Pioneer Corporation 7- 10Vcc 8- 3rd decoy
Claims (2)
ィング回路においで、該コンデン→ノーを充電する第1
及び第2の電流諒と、交流電源電圧のゼロレベルにてパ
ルスを発生ずるパルス発生回路と、前記コンデンサの充
電電圧を検出し、所定の電位にて出ノ〕を発生する信号
発生回路と、該信号発生回路出力により前記パルス発生
回路の信号伝達を制御する第1のゲート回路と、該第1
のグー1〜回路の出力信号によりオンされ前記コンデン
サの充電電荷の放電を制御する第2のゲート回路と、前
記信号発生回路出力により前記第2の定電流源のコンア
ン4ノへの送出を制御する第3のグー1−回路とを右す
るミューティング回路。(1) In a power supply muting circuit operated by a capacitor charging voltage, the first circuit that charges the capacitor→no
and a second current level, a pulse generation circuit that generates a pulse at the zero level of the AC power supply voltage, and a signal generation circuit that detects the charging voltage of the capacitor and generates an output at a predetermined potential. a first gate circuit that controls signal transmission of the pulse generation circuit by the output of the signal generation circuit;
a second gate circuit that is turned on by the output signal of the circuit and controls the discharging of the charge charged in the capacitor; and a second gate circuit that controls the output of the second constant current source to the condenser 4 by the output of the signal generation circuit. A third goo 1-circuit and a muting circuit.
1へ回路より構成されることを特徴とする特許請求の範
囲第1項記載のミューティング回路。(2) The muting circuit according to claim 1, wherein the signal generating circuit is comprised of a level sending circuit and a signal transmitting circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60006584A JPS60185409A (en) | 1985-01-17 | 1985-01-17 | Muting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60006584A JPS60185409A (en) | 1985-01-17 | 1985-01-17 | Muting circuit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52034098A Division JPS6040209B2 (en) | 1977-03-28 | 1977-03-28 | Muting circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60185409A true JPS60185409A (en) | 1985-09-20 |
JPS617B2 JPS617B2 (en) | 1986-01-06 |
Family
ID=11642372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60006584A Granted JPS60185409A (en) | 1985-01-17 | 1985-01-17 | Muting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60185409A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11230503B2 (en) * | 2017-06-27 | 2022-01-25 | General Electric Company | Resin for production of porous ceramic stereolithography and methods of its use |
-
1985
- 1985-01-17 JP JP60006584A patent/JPS60185409A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS617B2 (en) | 1986-01-06 |
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