KR880002867Y1 - Mono-stable multivibrator - Google Patents
Mono-stable multivibrator Download PDFInfo
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- KR880002867Y1 KR880002867Y1 KR2019850016219U KR850016219U KR880002867Y1 KR 880002867 Y1 KR880002867 Y1 KR 880002867Y1 KR 2019850016219 U KR2019850016219 U KR 2019850016219U KR 850016219 U KR850016219 U KR 850016219U KR 880002867 Y1 KR880002867 Y1 KR 880002867Y1
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- integrated circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/284—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator monostable
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- Power Engineering (AREA)
- Pulse Circuits (AREA)
Abstract
내용 없음.No content.
Description
제1(a)도는 종래의 회로도.1 (a) is a conventional circuit diagram.
제1(b)도는 종래회로의 각부에 나타나는 동작 파형도.1 (b) is an operation waveform diagram showing each part of a conventional circuit.
제2(a)도는 본 고안의 회로도.2 (a) is a circuit diagram of the present invention.
제2(b)도는 본 고안의 각부에 나타나는 동작파형도.Figure 2 (b) is an operating waveform diagram appearing in each part of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
Q1, Q2, Q3: 트랜지스터 OP1: 비교기Q 1 , Q 2 , Q 3 : Transistor OP 1 : Comparator
I1: 인버터 VR1: 가변저항I 1 : Inverter VR 1 : Variable resistor
C1: 콘덴서 VB. VB. : 바이어스전압C 1 : condenser V B. V B. : Bias voltage
20 : 집적회로내부 R1, R5: 저항20: internal circuit R 1 , R 5 : resistance
10 : 집적회로 외부의 연결단자10: Connection terminal outside the integrated circuit
본 고안은 집적회로(IC)내부의 단안정 멀티바이브레이터(mono multivibrator)의 구성을 콘덴서 (용량 수PF 수십 PF)를 포합하여 집적화하므로서 주변 회로의 간소화 시킬 수 있도록 한 단안정 멀티바이브레이터 회로에 관한 것이다.The present invention relates to a monostable multivibrator circuit in which the configuration of a monostable multivibrator in an integrated circuit (IC) is integrated by integrating a capacitor (capacity of several PF tens of PF) to simplify the peripheral circuit. .
종래에는 제1도에 도시한 바와 같이 단자(a)에는 논리입력이"1"이면 트랜지스터(Q1)는"온"상태가 되고, 트랜지스터(Q3)는 "오프"상태로 된다. 이때에 집적회로(20)의 외부에 연결된 콘덴서(C1)는 가변저항(VR1) 및 전원(Vcc) 값에 따라 제1(b)도의 (b)에서와 같이 충전상태가 된다. 이때에 콘덴서 (C1)의 충전 전압이 바이어스 전압(VB)보다 고전원 이면 비교기(OP1)의 논리출력단자(C)에는 제1(b)도의 (C)에 도시한 바와 같은 펄스 파형이 나타나게되고 논리 출력단자(C)에는 "1"의 상태로 된다. 한편 단자(a)에는 놀리입력이 "O"로 되면 트랜지스터(Q1)는 "오프"상태가 되고, 트랜지스터(Q3)는 "온"상태가 된다.Conventionally, as shown in FIG. 1, when the logic input is "1" to the terminal a, the transistor Q 1 is in the "on" state, and the transistor Q 3 is in the "off" state. At this time, the capacitor C 1 connected to the outside of the integrated circuit 20 is charged as shown in (b) of FIG. 1 (b) according to the value of the variable resistor VR 1 and the power supply Vcc. At this time, if the charging voltage of the capacitor C 1 is higher than the bias voltage V B , the logic waveform C of the comparator OP 1 has a pulse waveform as shown in (C) of FIG. Appears and the logic output terminal C is in the state of " 1 ". On the other hand, when the monolithic input is "O" at the terminal a, the transistor Q 1 is in the "off" state, and the transistor Q 3 is in the "on" state.
이때에 콘덴서(C1)의 충전 전압은 방전하게 되어 비교기(OP1)의 논리 출력단자(C)에는 "O"로 된다. 그러나 제1(b)도의 (b)에서와 같이 콘덴서(C)의 충전되는 특성이 직선성을 갖게하기 위하여 대용량의 콘덴서를 필요로 하므로 이로 인하여 집적회로 내에 집적화 할 수가 없게 되어 집적회로의 외부에 콘덴서(C1)를 가변저항(VR1)과 전원(Vcc)에 연걸하여야만 하므로서 외부회로 구성이 복잡하여 지는 문제점이 있었다.At this time, the charging voltage of the condenser C 1 is discharged and becomes "O" in the logic output terminal C of the comparator OP 1 . However, as shown in (b) of FIG. 1 (b), a large-capacity capacitor is required in order to make the charging characteristic of the capacitor C linear, which makes it impossible to integrate the integrated circuit into the integrated circuit. Since the capacitor C 1 must be connected to the variable resistor VR 1 and the power supply Vcc, there is a problem that the external circuit configuration becomes complicated.
본 고안은 이러한 점을 감안하여 집적회로 설계에 응용할 수 있도록 집적회로내에 적은 용량(수 PF 내지 수십 PF)의 콘덴서를 함께 접적화 시켜서 집적회로의 외부에 회로구성을 간단하게 할 수 있어, 단안정 멀티바이브레이터의 기능을 적용하는 집적회로내의 소자로서 용이하게 사용할 수 있도록 안출한 것으로 이를 첨부한 도면에 의하여 상세히 설명하면 다음과 같다.In consideration of this, the present invention integrates a capacitor of a small capacity (a few PF to several tens of PFs) together in an integrated circuit so that the circuit configuration can be simplified outside of the integrated circuit. The device is designed to be easily used as an element in an integrated circuit to which the function of the multivibrator is applied.
제2(a)도에 도시한 바와 같이 인버터(I1)를 트랜지스터(Q1)에 베이스측에 접속하고, 상기 트랜지스터(Q1)의 콜렉터측에 베이스측이 접속된 트랜지스터(Q2)의 에미터측에는 콘덴서(C1)와 비교기(OP1)의 반전단자 및 트랜지스터(Q3)의 콜렉터측을 연결하고, 상기 트랜지스터(Q3)의 에미터측에는 집적회로 외부 연결단자(10)와 가변저항(VR1)을 연결하여 구성한 것이다.Of claim 2 (a) as shown in Fig connected to the base side of the inverter (I 1) to the transistor (Q 1) and the transistor (Q 1) of the transistor (Q 2) is the base side connected to the collector side of the the emitter side of the capacitor (C 1) and a comparator (OP 1), an inverting terminal and a transistor connected to the collector side of the (Q 3), and said transistor (Q 3), the emitter side of the integrated circuit an external connection terminal 10 of the variable It is composed by connecting resistor (VR 1 ).
여기서 점선 내부(20)는 집적회로 내부를 표시한다.Here, the dotted line interior 20 represents the interior of the integrated circuit.
미설명 부호 Vcc는 전원단자이다.Unexplained sign Vcc is a power supply terminal.
이와 같이 구성된 본 고안의 작용 효과를 설명하면 다음과 같다.Referring to the effects of the present invention configured as described above are as follows.
제2도에 있어 단자(a)에는 논리입력 "1"신호가 입력되면 트랜지스터(Q1)는 "온"상태가 되어 이에 따라 트랜지스터(Q2)(Q3)는 "오프"상태가 된다.In FIG. 2, when the logic input " 1 " signal is input to the terminal a, the transistor Q 1 is in the " on " state, thereby the transistor Q 2 and Q 3 are in the " off " state.
이때에 콘덴서(C1)의 양단 전압은 순간적으로 Vcc트랜지스터(Q2)의 VBE(V)로 충전하게 되므로 비교기(OP1)의 논리출력단자(C)에는 제2(b)도의 (C)에 도시한 바와 같이 논리출력단자(C)에는 "O"가 되며 시간이 경과함에 따라 단자(a)에는 논리입력"O"상태로 하강되면 상기한 트랜지스터(Q1)는 "오프"상태가 되어 이에따라 트랜지스터(Q3)가 "온"상태가 된다. 따라서 콘덴서(C1)의 충전전압은 방전하게 되어 비교기(OP1)의 논리출력단자(C)DP "O"로 된다.At this time, since the voltage between both ends of the capacitor (C 1 ) is instantaneously charged to VBE (V) of the Vcc transistor (Q 2 ), the logic output terminal (C) of the comparator (OP 1 ) (C) of FIG. As shown in FIG. 5, when the logic output terminal C becomes “O” and as time passes, the transistor Q 1 becomes “off” when the terminal a falls to the logic input “O” state. As a result, the transistor Q 3 is turned on. Therefore, the charging voltage of the capacitor C 1 is discharged and becomes the logic output terminal C DP "O" of the comparator OP 1 .
그러나 제2(b)도의 (b)에서와 같이 콘덴서(C1)에 충전되는 전압이 트랜지스터(Q3) 및 외부연결단자(10)와 가변저항(VR1)으로 구성된 전류싱크(Sink)에 의하여 제2(a)도의 단자(b)에 나타나는 전압이 바이어스 전압(VB)보다 작아지는 순간 비교기(OP1)의 출력단자(C)에는 논리출력이 "1"인 상태로 변환된다.However, as shown in (b) of FIG. 2 (b), the voltage charged in the capacitor C 1 is applied to the current sink composed of the transistor Q 3 and the external connection terminal 10 and the variable resistor VR 1 . As a result, when the voltage appearing at the terminal b of FIG. 2 (a) becomes smaller than the bias voltage VB, the output terminal C of the comparator OP 1 is converted into a state in which the logic output is "1".
또한 제2(b)도의 (C)에 나타낸 바와 같이 지연시간 (t1-t2)설정은 집적회로 외부 연결단자(10)에 접속된 가변저항(VR1)을 조정하여 가변할 수 있는 것이다.Also, as shown in (C) of FIG. 2 (b), the delay time t 1 -t 2 setting can be changed by adjusting the variable resistor VR 1 connected to the integrated circuit external connection terminal 10. .
이상에서와 같이 동작되는 본 고안은, 집적회로 설계에 응용할 수 있도록 집적회로내에 적은 용량의 콘덴서를 함께 집적(IC)화 함으로서 세트를 설계할 때에 종래에 비교하여 외부회로 구성을 훨씬 간단하게 할 수 있는 실용적이 고안인 것이다.The present invention, which operates as described above, can make an external circuit much simpler than conventional designs when designing a set by integrating a small capacity capacitor (IC) together in an integrated circuit so that it can be applied to an integrated circuit design. It is a practical design.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850016219U KR880002867Y1 (en) | 1985-12-05 | 1985-12-05 | Mono-stable multivibrator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850016219U KR880002867Y1 (en) | 1985-12-05 | 1985-12-05 | Mono-stable multivibrator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR870011452U KR870011452U (en) | 1987-07-16 |
| KR880002867Y1 true KR880002867Y1 (en) | 1988-08-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019850016219U KR880002867Y1 (en) | 1985-12-05 | 1985-12-05 | Mono-stable multivibrator |
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|---|---|
| KR (1) | KR880002867Y1 (en) |
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1985
- 1985-12-05 KR KR2019850016219U patent/KR880002867Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR870011452U (en) | 1987-07-16 |
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