JPS60180261A - Clock signal selecting system - Google Patents
Clock signal selecting systemInfo
- Publication number
- JPS60180261A JPS60180261A JP59035523A JP3552384A JPS60180261A JP S60180261 A JPS60180261 A JP S60180261A JP 59035523 A JP59035523 A JP 59035523A JP 3552384 A JP3552384 A JP 3552384A JP S60180261 A JPS60180261 A JP S60180261A
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- clock
- circuit
- synchronism
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
【発明の詳細な説明】
く技術分野〉
本発明は多相多値デジタル通(i系の段調方式に関する
。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a multi-phase multi-value digital communication (i-system step-gradation system).
〈従来技術〉
一般に、多相多値デジタル通信系のデジタル伝送方式は
データ伝送の一方式として実用化されている。C1・k
近では情報伝送はの増大化に伴ない、周波数帯域の有効
利用化の研究開発が押し進められている。多相多値デジ
タル伝送方式の1つとじて例えば2 X2 値(n、m
は2以上の正の整数)の直交振幅変調器を用いた2n×
2m値直交振幅変調デジタル通伯方式(以下、多値QA
Mと略する)がある。この多値QA、Mを用いた通信系
においては、この変調方式が本質的にAM成分を有する
ために伝送路歪に弱い欠点があり、これを克服すべき種
々の等化技術を用い回線を構成しているのが現状である
。更に、海上区間等のフェージング発生確率の高い区間
への適用化の研究開発が押し進められて□おり、よりj
i%度な等化技術が必要とされている。その中のひとつ
にマルチ・キャリア復調方式がある。この方式は高能率
伝送を維持しつつ、耐フエージング特性を改善するのが
目的であり、フェージングによ多発生する帯域内振幅偏
差による回線品質の劣化は伝速速度に比例するという観
点から、従来1チヤンネル(R,F周波数)当りM b
tt/sの伝速容量を持つ回線に対しこれをN分割し、
隣接したMチャンネルでM / N btt/eX M
bit/sの伝送を行なう方式である。<Prior Art> In general, a digital transmission method for a multi-phase multi-value digital communication system has been put into practical use as a data transmission method. C1・k
In recent years, with the increase in information transmission, research and development on the effective use of frequency bands has been promoted. For example, one of the multiphase multivalue digital transmission systems is 2 x 2 values (n, m
is a positive integer of 2 or more) using a quadrature amplitude modulator of 2n×
2m-value quadrature amplitude modulation digital Tohaku method (hereinafter referred to as multi-value QA)
(abbreviated as M). In communication systems using this multilevel QA, M, this modulation method inherently has an AM component, so it has the disadvantage of being susceptible to transmission line distortion. The current situation is as follows. Furthermore, research and development is being pushed forward to apply it to sections with a high probability of fading occurring, such as offshore sections.
A unique equalization technique is needed. One of them is a multi-carrier demodulation method. The purpose of this method is to improve fading resistance while maintaining high efficiency transmission, and from the viewpoint that deterioration in line quality due to in-band amplitude deviation that often occurs due to fading is proportional to transmission speed. Conventional Mb per channel (R, F frequency)
Divide this into N for a line with a transmission capacity of tt/s,
M/N btt/eX M on adjacent M channels
This is a method that performs bit/s transmission.
第1図は、分割数N=4のこのマルチキャリア復j凋方
式の従来例のブロック図である。ここで多値QAM変i
i1.1方式としては16QAM変調方式とする。M
btt/sのデジダル信号4列およびクロック信号が1
α列/並列変換回路40に入力されたと想定する。クロ
ック信−弓は直列/並列変換回路4゜にてl/4周期に
カウントダウンされ小分岐される。またM bit/s
4列のデジタル信号はl/4にカウントダウンされた
クロック信号にて並列変換され、M/ 4 b1t/s
のデジタル信号4列とクロック信号が16Q直交振幅変
調器11−14に入力され、変調波として出力される。FIG. 1 is a block diagram of a conventional example of this multicarrier recovery method with the number of divisions N=4. Here, multilevel QAM change i
The i1.1 method is a 16QAM modulation method. M
4 columns of btt/s digital signals and 1 clock signal
Assume that the signal is input to the α column/parallel conversion circuit 40. The clock signal is counted down to 1/4 period by a serial/parallel conversion circuit 4° and divided into small branches. Also M bit/s
The four columns of digital signals are converted into parallel using a clock signal counted down to 1/4, resulting in M/4 b1t/s.
Four columns of digital signals and a clock signal are input to 16Q quadrature amplitude modulators 11-14, and output as modulated waves.
この変調波は適宜なる共通増幅、周波数変換され無線周
波として送・1−される。一方、受信側では各チャンネ
ルに対応した分波され直交振幅復調器21,22.28
゜24の入力信号となるが、本発明の主旨には相違する
ので省略しである。直交振幅復調器21〜24に入力さ
ハた変調波から搬送波を再生しこれにより同期検波を行
ない、デジタル信号が再生される。This modulated wave is subjected to appropriate common amplification, frequency conversion, and is transmitted as a radio frequency wave. On the other hand, on the receiving side, there are demultiplexed orthogonal amplitude demodulators 21, 22, and 28 corresponding to each channel.
Although this is an input signal of .degree.24, it is omitted since it is different from the gist of the present invention. A carrier wave is regenerated from the modulated wave input to quadrature amplitude demodulators 21 to 24, and synchronous detection is performed using the carrier wave, thereby regenerating a digital signal.
また、クロック信号も直交振幅変調器21,22゜28
.24から同様に抽出されクロック同期回路80にて位
相同期したクロック信号が再生されることとなる。これ
ら再生されたデジタル信号とクロック信号は並列/直列
変換回路41に入力される。したがってft16列のデ
ジタル信号と1列のクロック信号が並列/直列変換回路
41に入力されクロック信号は4逓倍されこの4逓倍さ
れたクロック信号にてデジタル信号の並列、・″直列変
換がなされM−btt/θのデジタル信号4列とクロッ
ク信号とが出力されることとなる。いま直交振幅復調器
21の系に機器障害あるいはマルチパスフェージング等
の伝送路障害が発生したと仮定すると、この時第1図に
示した1マルチキャリア周波数のルートは、識別再生用
のクロック同期回路80が非同期となシ、残り8列のル
ートが正常なる状態であるにもかかわらず、他のルート
にシステム切替が行なわれてしまう。In addition, the clock signal is also transmitted to the quadrature amplitude modulators 21, 22゜28.
.. A clock signal similarly extracted from 24 and phase-synchronized by the clock synchronization circuit 80 is reproduced. These reproduced digital signals and clock signals are input to the parallel/serial conversion circuit 41. Therefore, ft16 columns of digital signals and 1 column of clock signals are input to the parallel/serial conversion circuit 41, the clock signals are multiplied by 4, and the 4-multiplied clock signals are used to perform parallel and serial conversion of the digital signals.M- Four sequences of btt/θ digital signals and a clock signal will be output.Assuming that a device failure or a transmission line failure such as multipath fading has occurred in the quadrature amplitude demodulator 21 system, at this time In the 1 multi-carrier frequency route shown in Figure 1, the clock synchronization circuit 80 for identification and regeneration is not synchronized, and even though the routes in the remaining 8 columns are in a normal state, the system is switched to other routes. It will be done.
このように、従来のマルチキャリア復調方式の復調側で
のクロック信号抽出はN分割された直交振幅復調器の中
の1系列のみを使用しておシ、り四ツク信号抽出該当チ
ャンネルが機器障害あるいはフェージング等の伝送路障
害を受けた場合に残りの(N−1)チャンネルも同時に
回線障害となる欠点を有していた。In this way, the clock signal extraction on the demodulation side of the conventional multi-carrier demodulation method uses only one series of the N-divided orthogonal amplitude demodulator. Alternatively, if a transmission path failure such as fading occurs, the remaining (N-1) channels also suffer from a line failure at the same time.
〈発明の目的〉
したがって、本発明の目的は、クロック信号抽該当チャ
ンネルが機器障害あるいはフェージング等の伝送路障害
を受けた場合に残りのチャンネルも同時に回線障害とな
ることがない、マルチキャリア復調方式におけるクロッ
ク信号選択方式を提供することにある。<Objective of the Invention> Therefore, an object of the present invention is to provide a multicarrier demodulation method in which, even if a clock signal extraction channel suffers from an equipment failure or a transmission path failure such as fading, the remaining channels will not simultaneously experience a line failure. An object of the present invention is to provide a clock signal selection method in the present invention.
〈発明の構成〉
本発明のクロック信号選択方式は、特定の尖鋭度を有す
る共振回路を備えた複数のクロック信号抽出手段と、該
クロック信号抽出手段の出力を選択する手段とを有する
。<Configuration of the Invention> The clock signal selection method of the present invention includes a plurality of clock signal extraction means each having a resonant circuit having a specific sharpness, and means for selecting the output of the clock signal extraction means.
〈実施例〉 以下、杢発明の実施例を図面を参照しながら説明する。<Example> Hereinafter, embodiments of the heather invention will be described with reference to the drawings.
第2図は本発明の一実施例を示すブロック図で、第1図
の従来例において、クロック−期回路80を廃して、特
定の尖鋭度を有する共振回路を備え各直交振幅復調器2
1,22.28.24で抽出されたクロック信号を入力
して位相同期させるクロック同期回路81,82.38
.84と。FIG. 2 is a block diagram showing an embodiment of the present invention. In the conventional example shown in FIG.
Clock synchronization circuit 81, 82.38 that inputs the clock signal extracted in 1, 22, 28, and 24 and synchronizes the phase.
.. 84 and.
これらクロック同期回路81,82.88.84の出力
を入力し固定的な位相と調整した後、直交振幅復調器2
1,22.28.24から出力される制御信号により4
系列のうちの1つを選択するクロック参母選択回路85
を設けたものである。1制御侶号としては、例えばエラ
ーパルスをある一定時間カウントした信号が用いられる
。After inputting the outputs of these clock synchronization circuits 81, 82, 88, and 84 and adjusting the fixed phase, the quadrature amplitude demodulator 2
4 by the control signal output from 1, 22, 28, 24.
Clock reference selection circuit 85 that selects one of the series
It has been established. As the first control signal, for example, a signal obtained by counting error pulses for a certain period of time is used.
このような構成を有する復調系において、前述の機器障
害あるいはフェージング等伝送路障害が発生し、例えば
直交振幅復調器21の系が障害となったと仮定する。こ
の時、障害発生以前にクロック:4計重選択回路85が
クロック同期回路81の出力を選択していたとしても直
交振幅復調器21からの制御信号によシ、(予め主回線
の符号誤シ率が1xlOを越える点で制御信号が送出さ
れると仮定する)クロック信号を他の系に切替ることか
できる。したがって、直交振幅復調器22〜24、で再
生されたデジタル信号は障害となることがなく、クロッ
ク信号としても同期クロック信号が「1)生されること
となる。In the demodulation system having such a configuration, it is assumed that the aforementioned equipment failure or transmission path failure such as fading occurs, and for example, the system of the orthogonal amplitude demodulator 21 becomes the failure. At this time, even if the clock:4 weighting selection circuit 85 had selected the output of the clock synchronization circuit 81 before the occurrence of the fault, the control signal from the quadrature amplitude demodulator 21 (in advance, (assuming that the control signal is sent out at a point where the rate exceeds 1xlO) the clock signal can be switched to another system. Therefore, the digital signals reproduced by the orthogonal amplitude demodulators 22 to 24 do not become a hindrance, and a synchronous clock signal is generated as a clock signal.
〈冗明の効果〉
本発明によノ1.ば、クロックイ’t3号柚該当チャン
ネルが機器障害あるいはフェージング雪の伝送路障害を
受けた場合に残りのチャンネルも同時に回線障′吉とな
ることがないので、回弯j品qj(の向上を図ることが
でき、また動作71自・性についても再現性が高い。<Effect of redundancy> According to the present invention, No. 1. For example, if the corresponding channel of Clock I't3 suffers from equipment failure or transmission line failure due to fading snow, the remaining channels will not experience a line failure at the same time. Moreover, the reproducibility of the movement 71 is also high.
2151図は従来例のブロック図 1’< 2図は本発
明の1実施例のブロック図である。
11、12.1B、 14. ;直交振幅復調器。
21.22.28.24 ;直交振幅復調器。
81.82,88,84 :クロツク同期回路。
85 ;クロック蛙号選択回路。
4=(1; ’lf1列/並列変換回路。
4・l;並列/1y1列変換回路。
第1図
第2図Figure 2151 is a block diagram of a conventional example. Figure 1'<2 is a block diagram of an embodiment of the present invention. 11, 12.1B, 14. ; Quadrature amplitude demodulator. 21.22.28.24; Quadrature amplitude demodulator. 81.82,88,84: Clock synchronization circuit. 85; Clock frog selection circuit. 4=(1; 'lf1 column/parallel conversion circuit. 4・l; Parallel/1y1 column conversion circuit. Figure 1 Figure 2
Claims (1)
2 )分割されたマルチキャリア復調方式において、特
定の尖鋭度を有する共振回路を備えた複数のクロック信
号抽出手段と、該クロック信号抽出手段の出力を選択す
る手段とを有することを特徴とするクロツク信号1′1
!!択方式。Multi-level QAM modulation method of digital transmission system, especially N (〉
2) In a divided multi-carrier demodulation system, a clock signal is characterized in that it has a plurality of clock signal extraction means each having a resonant circuit having a specific sharpness, and means for selecting the output of the clock signal extraction means. signal 1'1
! ! Choice method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59035523A JPS60180261A (en) | 1984-02-27 | 1984-02-27 | Clock signal selecting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59035523A JPS60180261A (en) | 1984-02-27 | 1984-02-27 | Clock signal selecting system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60180261A true JPS60180261A (en) | 1985-09-14 |
Family
ID=12444104
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59035523A Pending JPS60180261A (en) | 1984-02-27 | 1984-02-27 | Clock signal selecting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60180261A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07143086A (en) * | 1993-11-17 | 1995-06-02 | Matsushita Electric Ind Co Ltd | Digital transmitter |
-
1984
- 1984-02-27 JP JP59035523A patent/JPS60180261A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07143086A (en) * | 1993-11-17 | 1995-06-02 | Matsushita Electric Ind Co Ltd | Digital transmitter |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0673131A2 (en) | Hierarchical OFDM system | |
JP2904986B2 (en) | Orthogonal frequency division multiplex digital signal transmitter and receiver | |
JP3832716B2 (en) | Signaling using phase rotation technology in digital communication systems | |
JP3582650B2 (en) | Phase modulation apparatus, phase modulation method thereof, and phase modulation program | |
JP2008227586A (en) | Transmitter and receiver | |
JPS60180261A (en) | Clock signal selecting system | |
US4122397A (en) | Apparatus and method for timing recovery from a pseudo-ternary signal | |
JPH06120995A (en) | Frame synchronizing circuit for digital radio receiver | |
JP3359927B2 (en) | Demodulator for quadrature amplitude modulation digital radio equipment. | |
JP2715873B2 (en) | Slot synchronization method | |
JP3117412B2 (en) | Diversity system and its transmitter and receiver | |
JPH0630069A (en) | Qam transmission system by multi-subcarrier | |
JPH08265288A (en) | Ofdm signal synchronization demodulator | |
JP3301462B2 (en) | Modulation multi-level information transmission method | |
JPS60189354A (en) | Communication system | |
JPH06101718B2 (en) | TDMA frame synchronization method | |
JP3278311B2 (en) | Data transceiver | |
JP3639175B2 (en) | Digital signal transmission device | |
US6731679B1 (en) | Modulator/demodulator and method of modulation/demodulation used for same | |
KR970000163B1 (en) | Modulator and demodulator in tdma | |
JPS60141057A (en) | Modulation demodulation switching system | |
JP2671803B2 (en) | Data multiplex transmission device | |
JPH0284836A (en) | Error correction method for multicarrier radio transmission system | |
JPS5934033B2 (en) | quadrature amplitude modulator | |
JPH0648830B2 (en) | Modulator |