JPS60175170A - Information processing system - Google Patents
Information processing systemInfo
- Publication number
- JPS60175170A JPS60175170A JP3067184A JP3067184A JPS60175170A JP S60175170 A JPS60175170 A JP S60175170A JP 3067184 A JP3067184 A JP 3067184A JP 3067184 A JP3067184 A JP 3067184A JP S60175170 A JPS60175170 A JP S60175170A
- Authority
- JP
- Japan
- Prior art keywords
- request
- main memory
- access
- processing units
- request receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
kA明の鵬する技術分野
本発明は粗結合型マルチプロセ、すで構成されたtH報
処理システムに胸する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention is directed to a loosely coupled multi-process, pre-configured tH information processing system.
従来技術
複数台の処理装置を有するマルチプロセッサシステムは
、金主メモリ領域を共用する密結合型と主メモリ領域を
共用しない粗結合型とに分類される。粗結合型マルチプ
ロセッサは装置間の独立性が高く、耐故障性に被れてい
るが、密結合型システムは性能改善向で粗結合型よシ優
れている。一方通常運用は密結合で行い、#Lいソフト
ウェアのデパック時、システムを粗結合連転し、業務の
運用と並行して独立なシステムでテバ、りするという運
用方式も行なわれている。ところが粗結合システムを構
築するためKは、各装置を完全に2xrc川xしなけれ
はならずハードウェア量が増加するという問題がある。BACKGROUND OF THE INVENTION Multiprocessor systems having a plurality of processing units are classified into tightly coupled types that share a main memory area and loosely coupled types that do not share a main memory area. Loosely coupled multiprocessors have high independence between devices and are fault tolerant, but tightly coupled systems are superior to loosely coupled systems in terms of improved performance. On the other hand, there is also an operation method in which normal operations are performed in a tightly coupled manner, and when depacking #L software, the system is loosely coupled, and an independent system is used in parallel with business operations. However, in order to construct a loosely coupled system, each device must be completely connected to 2 x rc servers, which poses a problem in that the amount of hardware increases.
すなわち、主メモリおよび主メモリへの演算処理装置の
アクセスを制御するシステム制御製筒は完全に2重に用
意する必喪がある。That is, it is necessary to provide completely duplicate main memory and system control cylinders that control access of the arithmetic processing unit to the main memory.
発明の目的
本発明の目的はハードウェア量の増加を最小にした粗結
合の&Th処理システムを提供するととKめる0
発明の構成
すなわち、本発明のシステムは、複数の演算処理装置、
と、複数の入出力処理装置と主メモリ忙接続され前記複
数の演算処理装置および入出力処理装置の主メモリアク
セスと前記各処理装置間の通信を制御する1台のシステ
ム制御装置と、前記複数の演算処理装置が密結合運転状
態か粗結合運転状態かを保持する状態保持手段と、前記
演算処理装置および入出力処理装置の主メモリアクセス
アドレスがアクセスを許容された主メモリ領域内かどう
かをチェ、りするアクセスチェック手段を有し、粗結合
状態で1台の主メモリ領域を分割して使用すΣことケ%
徴とする。OBJECTS OF THE INVENTION It is an object of the present invention to provide a loosely coupled &Th processing system that minimizes the increase in the amount of hardware.
a system control device that is connected to a plurality of input/output processing devices and a main memory and controls main memory access of the plurality of arithmetic processing devices and input/output processing devices and communication between the processing devices; state holding means for maintaining whether the arithmetic processing unit of the arithmetic processing unit is in a tightly coupled operating state or a loosely coupled operating state; It has an access check means to check, and it is possible to divide and use one main memory area in a loosely coupled state.
be a sign.
発明の実施例 次に本発明について、図面を参照して詳細に説明する。Examples of the invention Next, the present invention will be explained in detail with reference to the drawings.
第1図を参照すると、本発明の一実施例は、演算処理装
置i(以下CPU)2および3;入出力処理装k(以下
l0P)4および5:主記憶装置(以下MMU)6およ
びCPU2.3とl0P4.5のMMo6へのアクセス
とCPU2.3およびl0P4.5の間の通信を制御す
るシステム制御h*<以下8CLI)1から構成されて
いる。Referring to FIG. 1, one embodiment of the present invention includes arithmetic processing units i (hereinafter referred to as CPU) 2 and 3; input/output processing unit k (hereinafter referred to as 10P) 4 and 5; main memory unit (hereinafter referred to as MMU) 6 and CPU 2. .3 and l0P4.5 access to MMo6 and communication between CPU2.3 and l0P4.5.
5CU1の動作は密結合モードと粗結合モードとで異な
る。このモードは初期設定時に設定される。The operation of 5CU1 differs between tight coupling mode and coarse coupling mode. This mode is set during initial setup.
密結合モードにおいてはCPU2,3およびl0P4.
5は任意の主記憶エリヤ、任急のプロセッサにアクセス
できるが、粗結合モードにおいてはCPU 1祉l0P
4と、CPU2はl0P5とのみ′!!:個可能であシ
、CPU1およびCPU2間の通伯祉禁止される。また
、アクセスできる主記憶の領域も限定される。以下粗結
合モードでの動作を第2図を参照して説明する。第2図
は8CU1の概略構成を示す図である。In tightly coupled mode, CPU2, 3 and l0P4.
5 can access any main memory area and any processor at any time, but in loosely coupled mode, the CPU 1
4 and CPU2 is only l0P5'! ! : Communication between CPU1 and CPU2 is prohibited. Furthermore, the area of the main memory that can be accessed is also limited. The operation in the coarse coupling mode will be explained below with reference to FIG. FIG. 2 is a diagram showing a schematic configuration of 8CU1.
各装置jk2〜5からのメモリアクセス要求は5CU1
のリクエスト受付回路20,21,22および23にセ
ットされる。リクエスト受付回路20〜23は、谷処理
装置2〜5がアクセス可能な主記憶の領域を記憶するレ
ジスタを有する。本実施例ではアクセス可能領域を開始
番地とサイズの形で指定する2組のレジスタを各リクエ
スト受付(ロ)路20〜23は備えておシ、初期設定時
にその値が設定される。Memory access requests from each device jk2 to jk5 are 5CU1
is set in the request reception circuits 20, 21, 22 and 23 of. The request reception circuits 20 to 23 have registers that store areas of main memory that can be accessed by the valley processing devices 2 to 5. In this embodiment, each request receiving path 20 to 23 is provided with two sets of registers for specifying an accessible area in the form of a starting address and size, and the values thereof are set at the time of initial setting.
第3図を参照すると、MMo6の記憶領域は分割され、
CPUz 、l0P4およびCPUa、l0P5専川の
領域と全処理装置が共通にアクセスできる領域とに分け
られる。Referring to FIG. 3, the storage area of MMo6 is divided,
It is divided into an area for CPUz, 10P4 and CPUa, 10P5, and an area that can be commonly accessed by all processing units.
再び第2図を参照すると、リクエスト受付回路20.2
1.22および23は受付けたメモリアクセス要求のア
ドレスが、指定された領域内かどうかをチェックする。Referring again to FIG. 2, the request reception circuit 20.2
1.22 and 23 check whether the address of the accepted memory access request is within the specified area.
もしアクセス範囲外であれは、領域外アクセスエラーを
要求元装置に対し、応答回路24を介して報告する。ア
クセス要求が指定された領域内であれは、制御回路27
は各リクエスト受付−路20〜23からの信号に従いそ
の優先順位を判定し、最も優先順位の為いリクエストを
選びリクエスト送出1g路25を介してMMo 6に送
出する。MMo6はリクエストに従って畳込もしくは読
出動作を行い、その結果をメモリリブ2イ回路26に送
出する。さらにリプライは応答回路24を介して要求元
装置に送出される。If it is outside the access range, an out-of-range access error is reported to the requesting device via the response circuit 24. If the access request is within the specified area, the control circuit 27
determines the priority according to the signals from each request receiving path 20 to 23, selects the request with the highest priority, and sends it to the MMo 6 via the request sending path 25. The MMo6 performs a convolution or read operation according to the request, and sends the result to the memory rib circuit 26. Further, the reply is sent to the requesting device via the response circuit 24.
処理装置間の通信は次のように行なわれる。各処理装置
からの通信要求(CPUからQIOF起動またはIOP
からのCPUへの割込報告)はメモリアクセスと同様リ
クエスト受付回路20 、21 。Communication between processing devices is performed as follows. Communication requests from each processing unit (QIOF activation or IOP from CPU)
Similar to memory access, interrupt reports to the CPU from request receiving circuits 20 and 21 are performed.
22および23にセットされる。谷リクエスト受付回路
20.21.22および23は粗結合モードで許される
処理装置間通信かどうかを、初期設定情報にもとづきチ
ェックする。違反するアクセスはメモリの領域外アクセ
スエラーと同様にアクセス違反を要求元装置に報告する
。許されたアクセスであれば制御回路27による優先順
位の判定を行い、最もプライオリティが高けれは応答回
路24を介して、その要求は豐求先処理装klC送出さ
れる0
本実施例ではCPU3およびl0P5はMMU6のn番
地〜(2n−1,)番地、2n番地からm査地迄アクセ
ス可能である。この主メモリアドレスとプログラムアド
レスとの対応は、プログラムの発生する仮想アドレスを
生メモリの実アドレスへの変挨の過程で使用する公知の
ページ表を用いてCPU内で行なわれる。22 and 23. The valley request receiving circuits 20, 21, 22 and 23 check based on the initial setting information whether communication between processing devices is allowed in the coarse coupling mode. Violating accesses are reported to the requesting device in the same way as memory out-of-area access errors. If the access is permitted, the priority is determined by the control circuit 27, and if the priority is the highest, the request is sent to the requested processing unit klC via the response circuit 24. is accessible from address n to address (2n-1,) and from address 2n to address m of the MMU 6. This correspondence between main memory addresses and program addresses is done within the CPU using a well-known page table that is used in the process of converting virtual addresses generated by the program to real addresses in raw memory.
本実施例ではSCUが1つのシステムについて説明した
が、第4図に示される28CUのシステムにも適用可能
なことは明らかでめシ、第4図に示される例でi**大
4つのオペレーティングシステムの粗結合連転が可能と
なる。Although this embodiment describes a system with one SCU, it is obvious that it can also be applied to a system with 28 CUs as shown in FIG. 4. In the example shown in FIG. Roughly coupled interlocking of the system is possible.
発明の効果
本発明に11台のSCUで粗結合運転システムを構築で
きるため、ハードウェアの大幅なFill減ができると
いう効果がある。Effects of the Invention The present invention has the advantage that it is possible to construct a loosely coupled operation system with 11 SCUs, and therefore it is possible to significantly reduce the amount of hardware required.
第1−は本発明の一実施例を示す図、第2図はシステム
制御装置の構成例を示す図、第3図は生メモリ領域の割
尚を示す図、および#14図は本発明の他の実施例を示
す図である。
第1図から第41において、1,7・・・・・・システ
ム制御装置、Z、3,8.9・・・・・・演算処理装置
、4.5,9,11・・・・・・入出力処理装置、6.
12・・・・・・主メモリ。Figure 1- is a diagram showing an embodiment of the present invention, Figure 2 is a diagram showing an example of the configuration of a system control device, Figure 3 is a diagram showing allocation of raw memory area, and Figure #14 is a diagram showing an example of the configuration of the system control device. It is a figure which shows another Example. 1 to 41, 1, 7... system control device, Z, 3, 8.9... arithmetic processing unit, 4.5, 9, 11...・I/O processing device, 6.
12... Main memory.
Claims (1)
記入出力処理装置の主メモリアクセスと前記各処理装置
間の通イにとを制御する1台のシステム制御装置と、 前記複数の演算処理装置が密結合運転状態か粗結合運転
状態かを保持する状態保持手段と、前記演算処理装置お
よび前記入出力処理kmの前記主メモリアクセスアドレ
スがアクセスを許容された主メモリ領域内かどうかをチ
ェ、りするアクセスチェック中段とを肩し、 粗結合状態で1台の主メモリ領域を分割して使用するこ
とを特徴とする情報処理システム。[Scope of Claims] A plurality of arithmetic processing units; a plurality of input/output processing units; and a main memory connected to the plurality of arithmetic processing units and the input/output processing units, and connection between the main memory access of the plurality of arithmetic processing units and the input/output processing units, and the connection between the respective processing units. one system control device that controls the communication; a state holding means that maintains whether the plurality of arithmetic processing units are in a tightly coupled operating state or a loosely coupled operating state; The main memory access address of the main memory is within the main memory area that is permitted to be accessed. Information processing system.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3067184A JPS60175170A (en) | 1984-02-21 | 1984-02-21 | Information processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3067184A JPS60175170A (en) | 1984-02-21 | 1984-02-21 | Information processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60175170A true JPS60175170A (en) | 1985-09-09 |
Family
ID=12310187
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3067184A Pending JPS60175170A (en) | 1984-02-21 | 1984-02-21 | Information processing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60175170A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0830481A (en) * | 1994-07-19 | 1996-02-02 | Nec Commun Syst Ltd | Race operation test system |
-
1984
- 1984-02-21 JP JP3067184A patent/JPS60175170A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0830481A (en) * | 1994-07-19 | 1996-02-02 | Nec Commun Syst Ltd | Race operation test system |
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