JPS60167372A - Manufacture of thin-film transistor - Google Patents
Manufacture of thin-film transistorInfo
- Publication number
- JPS60167372A JPS60167372A JP2252884A JP2252884A JPS60167372A JP S60167372 A JPS60167372 A JP S60167372A JP 2252884 A JP2252884 A JP 2252884A JP 2252884 A JP2252884 A JP 2252884A JP S60167372 A JPS60167372 A JP S60167372A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- forming
- thin film
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000010408 film Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000009413 insulation Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 11
- 239000000463 material Substances 0.000 abstract description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 2
- 230000006837 decompression Effects 0.000 abstract 1
- 239000011521 glass Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、ガラス等板Ｈに作製される薄膜トランジスタ
に関するものであり、時に界面における表面準位密呵の
小さい非自己整合型簿膜トランジスタの製造方法に関す
る。[Detailed Description of the Invention] [Technical Field] The present invention relates to a thin film transistor manufactured on a glass plate H, and sometimes relates to a method for manufacturing a non-self-aligned thin film transistor with small surface state density at an interface. .
薄膜トランジスタは、安（Ｎ’ｉな絶縁基板を用いるこ
とができること、大面積化が容易なことから、アクティ
ブマトリクヌ基板あるいはイメーノセンサなどに使用す
る目的で、近年−各所で活発に研究が進めらｈている。Thin film transistors have been actively researched in various places in recent years for the purpose of using them in active matrix substrates or image sensors because they can use low-cost (N'i) insulating substrates and can easily be made into large areas. ing.
一般的に、薄膜トランジスタの構造としては、イオン打
込み法？用いて自己整合的にソース及びドレイン部を形
成する自己整合型薄！漠トランジスタと、アモル）了ス
シリコン薄師トランジスタなどのようにイオン打込み法
を用いずに作製される非自己整合型９１．Ｆｊ １４
トランジスタの２種ｔ（＋に大別される。前者のｌｌ
ウｌ−を寄生容量を小さくできるので動作速度を速くす
ることができるなどの効果が期待できる。しかし、この
構造はイオン打込み工程が必要なこと、及び少なくても
ホト４工程が必侠なことなどから、コスト的には不利と
なる。そこで低コスト化、工程の簡単化などの目的を満
たす為には後者の非自己整合型薄膜トランジスタのほう
が有和である。以下では非自己整合７ＩＩＩ薄ｌＩαト
ランジスタについて述べる。In general, the ion implantation method is used to construct thin film transistors. A self-aligned thin film that forms source and drain parts in a self-aligned manner! Non-self-aligned transistors manufactured without using ion implantation, such as thin silicon transistors and amorphous silicon thin film transistors. Fj 14
There are two types of transistors, t(+).
Since the parasitic capacitance can be reduced, the operating speed can be increased, and other effects can be expected. However, this structure is disadvantageous in terms of cost because it requires an ion implantation process and at least four photolithographic processes. Therefore, in order to meet the objectives of cost reduction and process simplification, the latter non-self-aligned thin film transistor is more advantageous. In the following, a non-self-aligned 7III thin lIα transistor will be described.
従来の非自己整合型薄膜トランジスタの構造を第１図に
示す。１け透明絶縁基板、２は半導体薄膜である。３の
ドレイン電極と４のソース電極を形成した後、ゲート絶
縁膜５を堆積させ、最後にゲート′Ｍ極６１ｒ形成する
。薄膜トランジスタにおいて、その特性に大きな影響を
およぼすのけ半導体薄膜とゲート絶縁１１σとの界面状
態である。つまり界面における表面準位密度を小さくで
きれば界面にトラップされる電子あるいは正孔が低減さ
れ、従ってトランジスタ特性を向上させることができる
。ところがＭ１図に示したような従来の製造方法による
と、半導体薄膜２とゲート絶縁膜５との界面には、ドレ
イン電極及びソース電極の構成材料が一叶堆積させられ
、その後、前記ドレイン電極３及びソース電極４をパタ
ー、ニングする時に除去される。このように界面の表面
準位密度を小さくおさえることは従来の製造方法ではむ
ずかしい、〔目的〕
本発明け、界面の衣面準位密ぼを低減させた高性節な非
自己整合型薄膜トランジスタを、耐熱温度の低い透明絶
縁基根上忙作製する半金可能にすることが目的である、
〔概要〕
半導体薄膜とゲート絶縁膜との界面を清浄に個つために
、リフトオフ法によりドレイン電極及びソース電極を形
成するのが、本発明の概要である。The structure of a conventional non-self-aligned thin film transistor is shown in FIG. 1 is a transparent insulating substrate, and 2 is a semiconductor thin film. After forming the drain electrode No. 3 and the source electrode No. 4, a gate insulating film 5 is deposited, and finally a gate 'M pole 61r is formed. In a thin film transistor, the state of the interface between the semiconductor thin film and the gate insulator 11σ has a great influence on its characteristics. In other words, if the surface state density at the interface can be reduced, the number of electrons or holes trapped at the interface can be reduced, and the transistor characteristics can therefore be improved. However, according to the conventional manufacturing method as shown in FIG. and is removed when patterning the source electrode 4. In this way, it is difficult to suppress the surface state density at the interface using conventional manufacturing methods. [Summary] In order to maintain a clean interface between the semiconductor thin film and the gate insulating film, the drain and source electrodes are separated by a lift-off method. The outline of the present invention is to form an electrode.
〔実施例１〕
第２図に実施例１を示す。まず透明絶縁フル板７のとに
半導体薄膜８１ｒ堆積させ、続いて、常圧ＣＶＤ法ある
いは減圧ＣＶＤ法あるいけプラズマＣＶＤ法あるいはス
パッタ法により、絶縁ＩＩＩ ９を堆積させる。次（絶
縁膜９をバターニングし続いて半導体薄＠８をバターニ
ングして同図（ｂＩに示すように薄膜トランジスタの概
形を形成する。次にドレイン電極およびソース電極のパ
ターンのレジスト１０を形成し、前記レジスト１０（＋
−７２りとしてまず絶縁膜９をエツチングする。その後
ドレイン電極とソース電極の構成材料１１を堆積させて
同図（ｃ）に示す形とする。ここでレジスト１０を剥離
してリフトオフ法によって、ドレイン電極１２、乃びソ
ース電極１３を形成し第２図（ぬＩＣ示すような形とす
る。次にゲート絶縁膜１４をＪ＋）積置せ、その上にゲ
ート常、極１５を形成する。同図１ｅ） Ｋ示す形で薄
膜）・ランジヌタが完成する。[Example 1] Example 1 is shown in FIG. First, a semiconductor thin film 81r is deposited on the transparent insulating full plate 7, and then an insulating film III 9 is deposited by normal pressure CVD, low pressure CVD, plasma CVD, or sputtering. Next, the insulating film 9 is patterned, and then the semiconductor thin film @8 is patterned to form the general shape of the thin film transistor as shown in the same figure (bI). Next, a resist 10 with the pattern of the drain electrode and source electrode is formed. Then, the resist 10 (+
-72, the insulating film 9 is first etched. Thereafter, the material 11 constituting the drain electrode and source electrode is deposited to form the shape shown in FIG. 3(c). Here, the resist 10 is peeled off and a drain electrode 12 and a source electrode 13 are formed by a lift-off method to form a shape as shown in FIG. A gate pole 15 is formed thereon. Figure 1e) The thin film) and lunge nut are completed in the shape shown by K.
ｒ実施例２〕
実施例１で述べた方法ではゲート絶縁膜は二ｌ−構造と
なる。そこでゲート絶縁膜を一層のみ忙することも考え
られるので実施例２として第３１ヌ１に示す。ドレイン
電極及びソース電極の形成は実施例１で述べたのと同様
に、リフトオフ法により形成するので、第３図（ａ）か
ら（Ｃ）までに示す工程は、第２図（ハ））から（ｃ）
までに示す工程と同一である６第２図（ｄ）に示す形と
した後、絶縁膜９も除去し、第５図回のような形に干る
。次に）ｒ’ −）絶縁１：尊１６を［積させ、そり上
にゲート１ｊ極１７を形成する。rExample 2] In the method described in Example 1, the gate insulating film has a 2l- structure. Therefore, it is conceivable to increase the thickness of the gate insulating film by only one layer, so a second embodiment is shown in No. 31 No. 1. The drain electrode and source electrode are formed by the lift-off method in the same way as described in Example 1, so the steps shown in FIGS. (c)
6 After forming the shape shown in FIG. 2(d), which is the same as the process shown above, the insulating film 9 is also removed and dried into the shape shown in FIG. Next,)r'-)insulation 1:layer 16 is laminated to form a gate 1j pole 17 on the warp.
同図（ｅ）で示す形で薄膜トランジスタが完成中る。A thin film transistor in the form shown in FIG. 4(e) is currently being completed.
本発明により、非自己整合型薄膜トラン／フタをホト６
エ程により、特性の劣イヒを起こすことなく作製するこ
とが可能となる。しかも、コーニング７０５９ガラスの
ように、耐熱温度が低くて安価なガラス基板を用いると
とができるので、大幅なコヌトダウンが期待できるもの
である、実施例１で述べたように界面には異物質が付着
したり、あるいは工・ソチンダ液にさらされたりする工
程が含まれないので、界面の嵌面準位密ずを低くおさえ
ることができる。従って、トランジスタ特性のヌレノシ
ュホルド電圧を小さく仙ｊつことかできる、ヌレンシュ
ホルド電圧が小さけねば、低いゲート電圧でトランジス
タを駆動できるので消費電力の低減が可能となる。界面
が汚染されな（／−まため、信頼性も向上する。さらに
、ホト３工程であり作製が簡単なために、歩留りが向と
される、また低コスト化のためにもその意味は大きい。According to the present invention, a non-self-aligned thin film transformer/lid can be fabricated by photo6.
The process allows production without deterioration of properties. Moreover, since it is possible to use an inexpensive glass substrate with a low heat resistance temperature, such as Corning 7059 glass, a significant reduction can be expected.As mentioned in Example 1, there are no foreign substances at the interface. Since there is no step of adhesion or exposure to the solution, the level density of the fitting surface at the interface can be kept low. Therefore, the null hold voltage of the transistor characteristics can be reduced. If the null hold voltage is small, the transistor can be driven with a low gate voltage, and power consumption can be reduced. Since the interface is not contaminated (/-), reliability is also improved.Furthermore, since the manufacturing process is simple due to the 3-step process of photophotography, yields are improved, and this also has great significance in terms of cost reduction. .
ゲート絶縁膜は各ａＣＶＤ法やスパッタ法なで低温形成
方法を採用してカリ、全工程を低温で行なうことができ
る。従って安価なガラス基板を用いることができ、この
点からも低コスト化に寄与している。また実施例２に示
した方法を用いれば、ゲート絶Ｒ膜は一層のみの構造に
することもできる。The gate insulating film can be formed using a low-temperature forming method such as the aCVD method or the sputtering method, so that the entire process can be performed at a low temperature. Therefore, an inexpensive glass substrate can be used, which also contributes to cost reduction. Further, by using the method shown in Example 2, the gate isolation film can be made to have a structure of only one layer.
この場合も、界面に異物質が付着干る工程はけいってい
ないので、界面は清浄に伏つことができる。In this case as well, there is no drying process in which foreign substances adhere to the interface, so the interface can remain clean.
半導体薄膜の材料としては、多結晶シリコンあるいけ非
晶質シリコンなどが考えられる。例えば、多結晶シリコ
ンを用いて本発明に応用すれば、ガラス基板上に多結晶
シリコン薄膜トランジスタを作製することができる。信
頼性に関して日、多結晶シリコンのほうが非晶質シリコ
ンよりも良い。Possible materials for the semiconductor thin film include polycrystalline silicon, amorphous silicon, and the like. For example, if the present invention is applied to polycrystalline silicon, a polycrystalline silicon thin film transistor can be manufactured on a glass substrate. In terms of reliability, polycrystalline silicon is better than amorphous silicon.
従って、たとえば多結晶シリコンを用いて本発明をアク
ティブマトリクス基板の作製に応用すれば高信頼度のア
クティブマトリクスを安価な、ガラス基板上に形成する
ことが回部となり、液晶表示パネルの低コスト化、高信
頼化を実現できる。Therefore, if the present invention is applied to the production of an active matrix substrate using, for example, polycrystalline silicon, it will be possible to form a highly reliable active matrix on an inexpensive glass substrate, thereby reducing the cost of the liquid crystal display panel. , high reliability can be achieved.
以上述べたように、本発明にょれ１ｆ非自己整合型薄膜
トランジスタを、界面ｆ＊浄に保も、しかもガラス基板
上傾作製する事が可絆となり、トランジスタ特性劣化防
止、および歩留りの向上と低コスト化、さらには、信頼
性の向上など、すぐれた効果を得ることができるもので
ある。As described above, it is possible to manufacture a 1f non-self-aligned thin film transistor according to the present invention by keeping the interface f* clean and tilting the glass substrate upward, thereby preventing deterioration of transistor characteristics and improving yield. It is possible to obtain excellent effects such as cost reduction and improved reliability.
第１図は、従来の非自己整合型薄膜トランジスタについ
て説明するための図である。第２図れ）〜（ｇ） Ｉｄ
、本発明の実施例１を説明するための図であり、第３図
（ａ）〜（ｅ）け、同じ〈実施例２を説明するための図
である。
以 ト
出願人 株式会社 諏訪精工舎
第１図
第２図FIG. 1 is a diagram for explaining a conventional non-self-aligned thin film transistor. Figure 2) ~ (g) Id
FIG. 3 is a diagram for explaining the first embodiment of the present invention, and FIGS. 3(a) to 3(e) are diagrams for explaining the same embodiment 2. FIG. Applicant: Suwa Seikosha Co., Ltd. Figure 1 Figure 2
Claims (2)
中る工程と、前記半導体薄膜及び檜縁・ｌｉ＆をパター
ニングする工程と、リフトオフ法によりソーヌ電極及び
ドレイン電極を形成する工程と、ゲート電極を形成する
工程から成ること？特徴とする薄膜トランジスタの製造
方法。(1) A step of forming a semiconductor thin film, a step of forming an insulating layer, a step of patterning the semiconductor thin film and the edge/li&, a step of forming a Saone electrode and a drain electrode by a lift-off method, and a step of forming an insulating layer. Consists of the process of forming electrodes? Characteristic method for manufacturing thin film transistors.
して、低温形成法（常圧Ｄ Ｖ Ｄ法、あるいけ減圧Ｃ
ＶＤ法、あるいはプラズマＣＶＩ）法、あるいはスパッ
タ法など）を用いることを特徴とする特許請求の範囲Ｎ
Ｋ１項記載のｉｔな膜トランジスタの製造方法。(2) As a method for forming the insulation layer and gate layer, a low-temperature forming method (normal pressure D V D method, low pressure C
Claim N characterized in that a VD method, a plasma CVI method, a sputter method, etc.) is used.
A method for manufacturing an IT film transistor according to Section K1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2252884A JPS60167372A (en) | 1984-02-09 | 1984-02-09 | Manufacture of thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2252884A JPS60167372A (en) | 1984-02-09 | 1984-02-09 | Manufacture of thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60167372A true JPS60167372A (en) | 1985-08-30 |
Family
ID=12085290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2252884A Pending JPS60167372A (en) | 1984-02-09 | 1984-02-09 | Manufacture of thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60167372A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100422438B1 (en) * | 1996-12-13 | 2004-05-17 | 페어차일드코리아반도체 주식회사 | Power mos transistor |
| GB2492442A (en) * | 2011-06-27 | 2013-01-02 | Pragmatic Printing Ltd | Method of manufacturing a thin film transistor |
| GB2492532A (en) * | 2011-06-27 | 2013-01-09 | Pragmatic Printing Ltd | Method of manufacturing a thin film transistor |
| EP3549157A4 (en) * | 2016-11-30 | 2020-06-24 | Boe Technology Group Co. Ltd. | Method of fabricating thin film transistor, thin film transistor, and display apparatus |
-
1984
- 1984-02-09 JP JP2252884A patent/JPS60167372A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100422438B1 (en) * | 1996-12-13 | 2004-05-17 | 페어차일드코리아반도체 주식회사 | Power mos transistor |
| GB2492442A (en) * | 2011-06-27 | 2013-01-02 | Pragmatic Printing Ltd | Method of manufacturing a thin film transistor |
| GB2492532A (en) * | 2011-06-27 | 2013-01-09 | Pragmatic Printing Ltd | Method of manufacturing a thin film transistor |
| GB2492532B (en) * | 2011-06-27 | 2015-06-03 | Pragmatic Printing Ltd | Transistor and its method of manufacture |
| GB2522565A (en) * | 2011-06-27 | 2015-07-29 | Pragmatic Printing Ltd | Transistor and its method of manufacture |
| GB2492442B (en) * | 2011-06-27 | 2015-11-04 | Pragmatic Printing Ltd | Transistor and its method of manufacture |
| GB2522565B (en) * | 2011-06-27 | 2016-02-03 | Pragmatic Printing Ltd | Transistor and its method of manufacture |
| US9425193B2 (en) | 2011-06-27 | 2016-08-23 | Pragmatic Printing Ltd | Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material |
| US10672765B2 (en) | 2011-06-27 | 2020-06-02 | National Centre For Printable Electronics | Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material |
| EP3549157A4 (en) * | 2016-11-30 | 2020-06-24 | Boe Technology Group Co. Ltd. | Method of fabricating thin film transistor, thin film transistor, and display apparatus |
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