JPS6016459A - Read only memory device - Google Patents

Read only memory device

Info

Publication number
JPS6016459A
JPS6016459A JP58124458A JP12445883A JPS6016459A JP S6016459 A JPS6016459 A JP S6016459A JP 58124458 A JP58124458 A JP 58124458A JP 12445883 A JP12445883 A JP 12445883A JP S6016459 A JPS6016459 A JP S6016459A
Authority
JP
Japan
Prior art keywords
film
insulation
gate electrode
drain
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58124458A
Other languages
Japanese (ja)
Inventor
Eiji Sugimoto
杉本　榮治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58124458A priority Critical patent/JPS6016459A/en
Publication of JPS6016459A publication Critical patent/JPS6016459A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/34—Source electrode or drain electrode programmed

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable to obtain the titled device having a high density and a short time until the product delivery by a method wherein code writing is enabled through a contact hole bored by self-alignment with a gate electrode, after the electrode is formed. CONSTITUTION:A polycrystalline Si film 3 and insulation films 4 and 5 are formed on an insulation thin film 2 formed on the surface of an Si substrate 1. Next, an insulation film 51 is formed on the side surface of the gate electrode 31, and further an interlayer insulation film 6 is formed after the formation of the source-drain 7. Then, the contact hole for writing ROM codes is etched by a method wherein insulation films 41 and 21 are etched but the film 51 is not. A conductive layer such as an Al film 8 connecting both contact holes is formed. Insulation gate type FET's Q1-Q3 are formed in such a manner, and among of them the FET Q2 is short-circuited between the source and drain. Thereby, code writing is enabled after the formation of the gate electrodes, and accordingly the time from code order reception to product delivery becomes shorter.

Description

【発明の詳細な説明】 〔発明の分野〕 本う６明は絶縁ゲート型電界効果トランジスタ（以下Ｉ
ＧＦＥＴ）を主な構成要素とした半導体読み出し専用記
憶装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an insulated gate field effect transistor (hereinafter referred to as I
The present invention relates to a semiconductor read-only memory device whose main component is a GFET (GFET).

〔従来技術〕[Prior art]

ＩＧ）’ＥＴによる読み出し専用記憶装＠（以下ｍｖ）
の構成方法には、１ＧＦＥＴｉａｌ力線に対して並列に
接続する横積み型と、１ＧＦＥ’ｌ、直列に接続する縦
積み型に大別する事が出来る。前者は高速動作が容易で
ある反面高密度化しにくく高価であシ。IG)'ET read-only storage @ (hereinafter referred to as mv)
The configuration method can be roughly divided into a horizontal stacking type in which 1GFETial is connected in parallel to the line of force, and a vertical stacking type in which 1GFETial is connected in series. The former is easy to operate at high speed, but is difficult to increase density and is expensive.

後者は逆に尚速動作には適さないが高密度化が容易であ
り大容［ＬＯＭに適している。又１（、Ｕ　Ｍの１き込
み方法には、前記横積み型に主として適用されているコ
ンタクト切換え方式、拡散層切換え方式、及び前記縦積
み型に主として適用されているイオン注入切換え方式等
が一般的である。以上３方式の概略を第１図（コンタク
ト切換え方式）。On the contrary, the latter is not suitable for high-speed operation, but it is easy to increase the density and is suitable for large capacity [LOM]. In addition, the UM single-loading method includes the contact switching method, the diffusion layer switching method, which is mainly applied to the horizontal stacking type, and the ion implantation switching method, which is mainly applied to the vertical stacking type. The three methods mentioned above are outlined in Figure 1 (contact switching method).

第２図（拡＃！Ｌ層切換え方式）、第３図（イオン注入
切換え方式）にボす。なお三図共（Ａ）はトランジスタ
記号で示した回路接続図、（Ｂ）は断面ｔ１４造図であ
り、三図共横方向に関してはほぼ同一規準で描かれてい
ることから大きさ金比叡できるようにしである。Figure 2 (enlarged #!L layer switching method) and Figure 3 (ion implantation switching method) are shown. In addition, all three figures (A) are circuit connection diagrams shown with transistor symbols, and (B) is a cross-sectional t14 drawing, and since all three figures are drawn with almost the same standard in the horizontal direction, the size can be compared. That's how it is.

前記の如くイオン注入切換え方式による縦積型ＲＯＭは
最も高密度化に適している。しがしながら）Ｌ〇八への
重要な要素であるコード受注から製品の出荷までの時間
（以下ＴＡＴと記す）に関しては、イオン注入切換え方
式は、ゲート電極形成前にイオン注入を行う必要がある
事から比較的長い。As mentioned above, the vertically stacked ROM using the ion implantation switching method is most suitable for increasing the density. Regarding the time from code order to product shipment (hereinafter referred to as TAT), which is an important factor for L08, the ion implantation switching method requires ion implantation before gate electrode formation. It's relatively long for some reason.

なお前記三方式の内最もＴ　Ａ　Ｔの短かい方式はコン
タクト切換え方式であるが、前述の如く多くの面）Ａｔ
イ了するため抵密度であり高価である。Of the three methods mentioned above, the method with the shortest T A T is the contact switching method, but as mentioned above, there are many aspects)
It is difficult to use and expensive because it is difficult to use.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、高密度にしてＴＡＴの短かい縦積型Ｉ
Ｌ’ｃ）Ｍを提供することにある・〔発明の構成〕 不発明による読み出し専用記憶装置（Ｂ、ＵＭ）は。The object of the present invention is to provide a vertically stacked type I with high density and short TAT.
L'c)M [Structure of the Invention] A read-only storage device (B, UM) according to the invention.

直列１ｃ接続したＩ　ＩＪ　Ｆ’　Ｅ　Ｔのソース、ド
レイン間を短絡せしむる事によって書き込む縦積み型１
（Ｕ　Ｍにおいて、前記短絡は、前記ソース、ドレイン
のそれぞれにゲート電極と自己整合的に穿ゆれたコンタ
クト孔全通して前記ゲート電極とは絶縁された導電層に
よってなされる半金特徴とする。Vertical stack type 1 that writes by shorting the source and drain of I IJ F' ET connected in series 1
(In the UM, the short circuit is a semi-metal feature formed by a conductive layer insulated from the gate electrode, passing through the contact hole formed in each of the source and drain in self-alignment with the gate electrode.

〔実施例〕〔Example〕

次に本発明による実施例を第４図を参照して説明する。 Next, an embodiment according to the present invention will be described with reference to FIG.

第４図（Ａ）、　（ＩＪＩお（（１）、（至）は各々本
発明による実施例の製造方法を順に説明するための断面
図。FIG. 4(A), (IJI) ((1) and (to) are sectional views for sequentially explaining the manufacturing method of the embodiment according to the present invention.

第４図（匂は対応するトランジスタ記号で示した回路図
である。FIG. 4 is a circuit diagram with corresponding transistor symbols.

一導電性半導体基体例えばシリコン基体（１）、の表面
に形成した絶縁薄膜（２）、上に形成されたゲート電極
、例えば多結晶シリコン膜（３）、前自己多結晶シリコ
ン膜（３）上に絶縁膜（４）を介して形成したｒｉｉＪ
記絶縁膜（４）とは異質な第二の絶ｉｔ膜（５）全形成
する（第４図（Ａ））。An insulating thin film (2) formed on the surface of a conductive semiconductor substrate, e.g. a silicon substrate (1), a gate electrode formed thereon, e.g. a polycrystalline silicon film (3), a pre-self-polycrystalline silicon film (3) riiJ formed via an insulating film (4) on
A second insulation film (5) different from the insulation film (4) is completely formed (FIG. 4(A)).

次に、前記第二の絶縁膜（５）と同じ絶縁膜全形成し、
主として下方向にのみエツチングされる異方性エツチン
グ全第二回目に形成した第二の絶縁膜と同じ絶縁膜と同
じ厚さだけ除去すべく行い、第４図ＦＢ１の如くゲート
電極３１の側面にも第二の絶縁膜（５１）’を形成する
。なおゲート電極が多結晶シリコン膜であれば第４図（
Ｈ）の如く側面部にも絶縁膜４１を介しておくのが好ま
しい。さらにソース、ドレイン（７）全イオン注入法等
で形成した後。Next, the same insulating film as the second insulating film (5) is entirely formed,
Anisotropic etching, which mainly etches only in the downward direction, is performed to remove the same thickness as the second insulating film formed in the second step, and as shown in FIG. 4 FB1, the side surface of the gate electrode 31 is A second insulating film (51)' is also formed. Note that if the gate electrode is a polycrystalline silicon film, see Figure 4 (
It is preferable that an insulating film 41 is also provided on the side surfaces as shown in H). Further, a source and a drain (7) are formed by a total ion implantation method.

層間絶縁膜（６）全形成する。The interlayer insulating film (6) is completely formed.

次に、前記絶縁膜４１．２１はエツチングされるが前記
第二の絶縁膜はエツチングされない方法で、ｌ（ＵＭコ
ード書き込み用コンタクト孔のエツチングを行う第４図
（Ｑ）。Next, the insulating film 41.21 is etched but the second insulating film is not etched to form a contact hole for writing the UM code (FIG. 4(Q)).

次に両コンタクト孔を接続する導電層１例えば。Next, a conductive layer 1, for example, which connects both contact holes.

アルミニウム膜８もしくは多結晶シリコン膜等を形成す
る。つま−り第４図（１））左方から１ＧＦＥ’ｒ　Ｑ
、。An aluminum film 8 or a polycrystalline silicon film or the like is formed. In other words, Fig. 4 (1)) 1 GFE'r Q from the left
,.

Ｑ２．Ｑ３　が形成されているが、そのうちＱ２は第４
図（匂の如くソース、ドレイン間が短絡されていること
になる。Q2. Q3 is formed, of which Q2 is the fourth
Figure (As you can see, the source and drain are short-circuited.

以上の如く、不発明によれば、ゲート電極全形成した後
にコードの誉き込みが可能であ、Ｑ　Ｔ　Ａ　Ｔは前記
コンタクト切換え方式の場合と同様に短かく、シかもコ
ンタクト孔の為の余分な面積を必要としないためイオン
注入切換え方式の縦横比ＵＭと全く同じ面積で実現出来
、従って高密度にして高密度にしてＴＡＴの短かい読み
出し専用記憶装置を実現できる。As described above, according to the invention, it is possible to write the code after the gate electrode is completely formed, and the Q T A T is short as in the case of the contact switching method, and it is possible to insert the code for the contact hole. Since no extra area is required, it can be realized in exactly the same area as the aspect ratio UM of the ion implantation switching method, and therefore a read-only storage device with high density and short TAT can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（Ａ）、　（Ｂ１．第２図（〜ｉＨ）、第３図ｔ
Ａ）、　ＣＢ）は各々従来？ｌＪによるＲＯＭの回路１
９Ｕ及び断面構造図である。第４図（Δ）〜（ト）は各
々不発明による一実施例全工程順に示す断面構造図、第
４図（匂はその回路図である。 なお図において、１・・・・・−導電性半導体基体。 ２・・・・・絶縁薄膜、３・・・・・・多結晶シリコン
膜、４゜４１・・・・・・絶縁膜、５．５１・・・・・
２８２の絶縁膜、６・・・・・・層間絶縁）漠、７・・
・・・ソース、ドレイン領域。 ８・・・・・アルミニウム膜。Figure 1 (A), (B1. Figure 2 (~iH), Figure 3 t
Are A) and CB) conventional? ROM circuit 1 by lJ
9U and a cross-sectional structure diagram. Figures 4 (Δ) to (g) are cross-sectional structural diagrams showing the entire process order of an embodiment according to the invention, respectively, and Figure 4 (the odor is the circuit diagram thereof. 2...Insulating thin film, 3...Polycrystalline silicon film, 4゜41...Insulating film, 5.51...
282 insulating film, 6... interlayer insulation) vague, 7...
...Source and drain regions. 8...Aluminum film.

Claims (1)

【特許請求の範囲】[Claims] 一導電性の半導体基体の表面に形成した絶縁ゲート型電
界効果トランジスタを複数個直列に接続し、前記直列に
接続した絶縁ゲート型電界効果トランジスタのソースと
ドレイン間全短絡せしむる事によって書き込む縦積型の
読み出し専用記憶装置において、前記ソースとドレイン
間を短絡せしむる手段は、前記ソース、ドレインのそれ
ぞれにゲート電極と自己整合的に穿かれたコンタクト孔
を通して前記ゲート電極とは絶縁された導電層による事
を特徴とする読み出し専用記憶装置。A plurality of insulated gate field effect transistors formed on the surface of a conductive semiconductor substrate are connected in series, and the sources and drains of the series connected insulated gate field effect transistors are completely shorted. In the multilayer read-only storage device, the means for short-circuiting between the source and the drain includes a contact hole that is insulated from the gate electrode through a contact hole formed in each of the source and drain in a self-aligned manner with the gate electrode. A read-only storage device characterized by a conductive layer.
JP58124458A 1983-07-08 1983-07-08 Read only memory device Pending JPS6016459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58124458A JPS6016459A (en) 1983-07-08 1983-07-08 Read only memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58124458A JPS6016459A (en) 1983-07-08 1983-07-08 Read only memory device

Publications (1)

Publication Number Publication Date
JPS6016459A true JPS6016459A (en) 1985-01-28

Family

ID=14886015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58124458A Pending JPS6016459A (en) 1983-07-08 1983-07-08 Read only memory device

Country Status (1)

Country Link
JP (1) JPS6016459A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61207057A (en) * 1985-03-11 1986-09-13 Sanyo Electric Co Ltd Manufacture of semiconductor integrated device
JPS6242458A (en) * 1985-08-19 1987-02-24 Seiko Epson Corp Manufacture of semiconductor device
JPS62120069A (en) * 1985-11-20 1987-06-01 Sanyo Electric Co Ltd Rom semiconductor device
JPS62206873A (en) * 1986-03-07 1987-09-11 Seiko Epson Corp Manufacture of semiconductor device
JPS62262455A (en) * 1986-05-09 1987-11-14 Seiko Epson Corp Manufacture of semiconductor device
EP0514850A2 (en) * 1991-05-20 1992-11-25 Matsushita Electronics Corporation Method for producing a MIS type semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61207057A (en) * 1985-03-11 1986-09-13 Sanyo Electric Co Ltd Manufacture of semiconductor integrated device
JPS6242458A (en) * 1985-08-19 1987-02-24 Seiko Epson Corp Manufacture of semiconductor device
JPS62120069A (en) * 1985-11-20 1987-06-01 Sanyo Electric Co Ltd Rom semiconductor device
JPS62206873A (en) * 1986-03-07 1987-09-11 Seiko Epson Corp Manufacture of semiconductor device
JPS62262455A (en) * 1986-05-09 1987-11-14 Seiko Epson Corp Manufacture of semiconductor device
EP0514850A2 (en) * 1991-05-20 1992-11-25 Matsushita Electronics Corporation Method for producing a MIS type semiconductor device
US5323048A (en) * 1991-05-20 1994-06-21 Matsushita Electronics Corporation MIS type semiconductor ROM programmed by conductive interconnects
EP0630052A2 (en) * 1991-05-20 1994-12-21 Matsushita Electronics Corporation MIS type semiconductor device and method for producing such semiconductor device
EP0630052A3 (en) * 1991-05-20 1995-03-15 Matsushita Electronics Corp MIS type semiconductor device and method for producing such semiconductor device.

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