JPS60161635A - Substrate for electronic device - Google Patents
Substrate for electronic deviceInfo
- Publication number
- JPS60161635A JPS60161635A JP1735884A JP1735884A JPS60161635A JP S60161635 A JPS60161635 A JP S60161635A JP 1735884 A JP1735884 A JP 1735884A JP 1735884 A JP1735884 A JP 1735884A JP S60161635 A JPS60161635 A JP S60161635A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- substrate
- film
- crystal substrate
- insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体層と絶縁体層とからなる電子デバイス用
基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a substrate for electronic devices comprising a semiconductor layer and an insulator layer.
（従来技術）
ＰｂＴｉＯｓ、ＰｂＴｉ０ｇ Ｌ：Ｉ）Ｐｂ及びＴｉ
の一部をそれぞれＬａ、Ｚｒで置換したＰ ｂ （Ｔ
ｉ Ｚ ｒ ） Ｏｓ （以下ＰＺＴと呼ぶ）、（Ｐｂ
Ｌａ） （ＴｉＺｒ）Ｏ，似−ＦＰＬＺＴと呼ぶ）、さ
らにはＢ ａ Ｔ ｉ Ｏｓなどのペロ７スカイト形の
結晶構造をとる誘電体材料はその有する強誘電性、焦電
性、圧電性などの機能性故に従来、コンデンサー、圧電
素子、電気光学素子など種々の機能デバイスに応用され
てきている。近年、デバイスの小型化高集積化の要請に
対応するためＫこれら材料の薄膜化の試みがなされ、焦
電型赤外線センサー、超音波センサー、光スィッチなど
で薄膜を用いたデバイスが試作されている。(Prior art) PbTiOs, PbTi0g L:I) Pb and Ti
P b (T
i Z r ) Os (hereinafter referred to as PZT), (Pb
Dielectric materials with a pero7skite crystal structure, such as La) (TiZr)O, similar to FPLZT), and B a Ti Os, have properties such as ferroelectricity, pyroelectricity, and piezoelectricity. Because of its functionality, it has been applied to various functional devices such as capacitors, piezoelectric elements, and electro-optical elements. In recent years, attempts have been made to make these materials into thin films in order to meet the demands for smaller and more highly integrated devices, and devices using thin films have been prototyped for pyroelectric infrared sensors, ultrasonic sensors, optical switches, etc. .
これら機能性誘電体を用いたデバイスにおいて最適なデ
バイス特性およびその再現性を確保するためＫは単結晶
を用いる−ことが必要である。多結晶体では粒界による
物理量の撹乱のため良好なデバイス特性を得ることがむ
つかしい。このことは薄膜形のデバイスにおいても同じ
であり、できるだけ完全な単結晶に近い機能性誘電体エ
ピタキシャル膜などが望まれる。このため単結晶膜の育
成が試みられており、１９８０年発行の７プライドフイ
ジツクス（Ａｐｐｌｅｉｄ Ｐｈｙｓｉｃｓ ）誌第２
１巻３３９頁〜３４３頁にＰＬＺＴをチタン酸ストロン
チウム（ＳｒＴｉＯｓ）及びマグネシア（ＭｇＯ）の単
結晶基板上にスパッター法によってエピタキシャル成長
したと報告されている。しかし、ｓｒ’ｒｔｏ３やＭｇ
Ｏなどの酸化物では大口径の単結晶基板を安価に製造す
ることはきわめて困難であり、またＭｇＯは化学的安定
性に欠けており、耐酸性、耐アルカリ性がなく、また大
気中より水分、炭酸ガス等を吸収して変質しやすく、デ
バイス製造プロセスに使用することは困難である。In order to ensure optimal device characteristics and their reproducibility in devices using these functional dielectrics, it is necessary to use a single crystal for K. In polycrystalline materials, it is difficult to obtain good device characteristics because physical quantities are disturbed by grain boundaries. The same is true for thin film devices, and a functional dielectric epitaxial film that is as close to a perfect single crystal as possible is desired. For this reason, attempts have been made to grow single crystal films;
1, pp. 339-343, it is reported that PLZT was epitaxially grown on a single crystal substrate of strontium titanate (SrTiOs) and magnesia (MgO) by sputtering. However, sr'rto3 and Mg
It is extremely difficult to manufacture large-diameter single crystal substrates at low cost with oxides such as O, and MgO lacks chemical stability, has no acid or alkali resistance, and is susceptible to moisture and moisture from the atmosphere. It is difficult to use in device manufacturing processes because it absorbs carbon dioxide gas and is easily deteriorated.
（発明の目的）
本発明は、上記従来、技術の欠点を改善するもので、ペ
ロブスカイト形結晶構造を有する機能性誘電体薄膜を含
む電子デバイス用基板を提供することを目的とする。(Object of the Invention) The present invention aims to improve the above-mentioned drawbacks of the conventional techniques, and an object of the present invention is to provide a substrate for an electronic device including a functional dielectric thin film having a perovskite crystal structure.
（発明の構成）
すなわち本発明はシリコン単結晶基板上に絶縁体膜が形
成され、該絶縁体膜上に一般式がＡＢ（５３で表わされ
、ＡとしてＰｂ、 Ｂａ％Ｓｒ、Ｍｇ及び希土類元素の
群から選ばれる一種以上の元素、ＢとしてＴｉ、Ｚｒの
一方または両方を含むぺ１１７７スカイト型結晶構造を
有する誘電体層が形成されているシリコン単結晶基板上
に形成する絶縁体単結晶〜
膜として、マグネシアスピネル（ＭｇＡ７，０． ）
・マグネシア（ＭｇＯ）が考えられる。この場合、Ｍｇ
Ｏは本出願人が提案（特願昭５７−２２９０３３）して
いるようにシリコン単結晶基板に直接成長するよりもシ
リコン基板上に成長したＭｇＡ／、Ｏ，を介して形成し
た方が良質の単結晶膜が形成できる。(Structure of the Invention) That is, in the present invention, an insulating film is formed on a silicon single crystal substrate, and a general formula AB (represented by 53) is formed on the insulating film, and A is Pb, Ba%Sr, Mg, and a rare earth element. An insulator single crystal formed on a silicon single crystal substrate on which a dielectric layer having a P1177 skyte crystal structure containing one or both of Ti and Zr as B is one or more elements selected from the group of elements. ~ As a film, magnesia spinel (MgA7,0.)
- Magnesia (MgO) can be considered. In this case, Mg
It is better to form O through MgA/, O, grown on a silicon substrate than to grow it directly on a silicon single crystal substrate as proposed by the present applicant (Japanese Patent Application No. 57-229033). A single crystal film can be formed.
従って絶縁体単結晶膜として２層構造のものでも良い。Therefore, the insulating single crystal film may have a two-layer structure.
また、本出願人は８１基板上に形成したＭｇ０Ａ４０３
工ビタキシヤノ頭は成長後ＭｇＯＡ４０３膜を通してＳ
ｔ基板を熱酸化することＫよってＭｇＡ４０４ ／５ｉ
０２ ／Ｓｔ構造にすることをすでに提案（特願昭５６
−１０３９６７ ）して〜・る。従って絶縁体単結晶膜
としてＳｔ単結晶基板上に非晶質ＳｔＯ，を介したよう
な構造のものでも良い。In addition, the present applicant has also developed Mg0A403 formed on an 81 substrate.
After growth, the plant head is exposed to S through the MgOA403 film.
By thermally oxidizing the substrate, MgA404/5i
02 /St structure has already been proposed (patent application 1982)
-103967) Do~・ru. Therefore, the insulating single crystal film may have a structure in which amorphous StO is interposed on a St single crystal substrate.
前述したように、ＰＬＺＴをマグネシアのバルク単結晶
基板上に成長させたという従来Ｕ術の報告はあるが、マ
グネシャスピネル単結晶基板上に成長させたという報告
はない。従って本発明においてマグネシアスピネルエピ
タキシャル膜上に形成されるペロ７ス力イト形誘電体エ
ピタキシャル膜は全く新規に行なわれたものである。ま
たマグネシアエピタキシャル膜の場合においても、ＰＬ
ＺＴがバルク単結晶基板上にエピタキシャル成長したか
らといりて、直ちにＳｔのような異種単結晶基板上成長
したマグネシアエピタキシャル膜上に同様ＫＰＬＺＴが
エピタキシャル成長するということにはならない。なぜ
なら、Ｓｔとマグネシアでは熱膨張係数に大きな差があ
り、Ｓｌｌ基板上形形成れたマグネシアエピタキシャル
膜中大きな残留応力が働い℃おり、マグネシアの格イは
かなり歪んでいる。またその結晶性もバルク単結晶にく
らべて劣っている。これらによる結晶表面エネルギーの
違いがエピタキシャル成長の際の結晶核発生に大きく影
響し′バルク単結晶上に成長する場合と全く異なった様
相を示すのが一般である。As mentioned above, there have been reports of conventional U technique in which PLZT has been grown on a magnesia bulk single crystal substrate, but there has been no report on growing PLZT on a magnesia spinel single crystal substrate. Therefore, in the present invention, the perovskite type dielectric epitaxial film formed on the magnesia spinel epitaxial film is completely new. Also, in the case of magnesia epitaxial film, PL
Just because ZT is epitaxially grown on a bulk single crystal substrate does not mean that KPLZT will be similarly epitaxially grown on a magnesia epitaxial film grown on a heterogeneous single crystal substrate such as St. This is because there is a large difference in thermal expansion coefficient between St and magnesia, and a large residual stress acts in the magnesia epitaxial film formed on the Sll substrate. Also, its crystallinity is inferior to that of bulk single crystals. These differences in crystal surface energy greatly affect the generation of crystal nuclei during epitaxial growth, and the behavior is generally completely different from that when growing on a bulk single crystal.
従って本願発明は絶縁体エピタキシャル膜としてマグネ
シアエピタキシャル膜を使用する場合もその新規性を材
料構造の観点から主張するものである。また、基板単結
晶としてＳｔ基板を用いるといういとから、以下に述べ
るように、その電子デバイスに与える有効性によって本
発明の甚大な効果を主張するものである。Therefore, the present invention asserts the novelty of the use of a magnesia epitaxial film as an insulator epitaxial film from the viewpoint of material structure. Further, since an St substrate is used as the single crystal substrate, the present invention claims great effects due to its effectiveness in electronic devices, as described below.
シリコン単結晶基板は良質で大口径のものが安価に入手
できるうえに熟成したシリコン半導体集積回路技術を用
いることによフてより高い機能を誘電体デバイスに持た
□せることができる。例えばシリコンＩＣと誘電体デバ
イスを同一チップ上に形成した複合デバイスの開発が可
能となる。とくに、マグネシアスピネル、マグネシアの
屈折率は１．７５程度テアルノニ対し、ＰｂＴｉＯ３，
ＰＺＴ等のペロゲスカイト形結晶構造を有する機能性誘
電体の屈折率は２．０以上で、マグネシアスピネルより
も大きい。従って、マグネシアスピネル上に形成した機
能性誘電体膜上釦光を導波させることが可能である。ま
た半導体レーザ材料となる■−■化合物半導体のマグネ
シアスピネル上へのエピタキシャル膜成長も可能であり
、半導体レーザ及び機能性誘電体を用いた受光素子及び
シリコン集積回路を一体化したような光ＩＣ素子の開発
も可能になる。High quality silicon single crystal substrates with large diameters are available at low cost, and by using mature silicon semiconductor integrated circuit technology, it is possible to provide dielectric devices with even higher functionality. For example, it becomes possible to develop a composite device in which a silicon IC and a dielectric device are formed on the same chip. In particular, the refractive index of magnesia spinel and magnesia is about 1.75, whereas that of PbTiO3,
The refractive index of a functional dielectric material having a perogeskite crystal structure such as PZT is 2.0 or more, which is larger than that of magnesia spinel. Therefore, it is possible to waveguide the button light on the functional dielectric film formed on the magnesia spinel. It is also possible to grow an epitaxial film on magnesia spinel, which is a ■-■ compound semiconductor used as a semiconductor laser material, to create an optical IC device that integrates a semiconductor laser, a photodetector using a functional dielectric, and a silicon integrated circuit. It also becomes possible to develop
以下実施例によって説明する。This will be explained below using examples.
（実施例１．）
面方位が（１００）のＳ１単結晶基板上にマグネシャス
ピネルをエピタキシャル成長し、その上品基板２は気相
成長法で成長したＭｇＡｔ、０３エピタキシヤル膜であ
る。３はスパッタ法で作成したＰｂＴｉ０．の単結晶膜
である。ＭｇＡ／、０．の気相成長は本出願人がすでに
提案（特願昭５７−１３６０５１ ）している方法で成
長した。すなわち反応ガスとしてＭｇＣ１，ＡｔＶｃＨ
Ｃｔガスを反応させて生成したｈｔｃｔ、 、Ｃｏ、％
Ｈ，ｆｆスを用い、キャリアガスとしてＮ、ガスを用い
た。ＭｇＡ４０．の生成反応はＭｇＣ４＋２ＡｔＣ４＋
４ＣＯ２＋４Ｈ２−＋ ＭｇＡ４０＆ ＋４ＣＯ＋８Ｈ
Ｃ２で表わされる。成長温度９５０℃で成長し、Ｘ線回
折及び電子線回折で（１０ｏ ）方位のＭ’ｇＡｔ、へ
がエピタキシャル成長していることを確認した。(Example 1) Magnetic spinel was epitaxially grown on an S1 single crystal substrate with a plane orientation of (100), and the elegant substrate 2 was an MgAt, 03 epitaxial film grown by vapor phase growth. 3 is PbTi0.3 prepared by sputtering method. It is a single crystal film. MgA/, 0. The growth was carried out by a method already proposed by the present applicant (Japanese Patent Application No. 136051/1982). That is, MgC1, AtVcH as the reaction gas
htct, , Co,% produced by reacting Ct gas
H, ff gas was used, and N gas was used as a carrier gas. MgA40. The production reaction is MgC4+2AtC4+
4CO2+4H2-+ MgA40& +4CO+8H
It is represented by C2. The film was grown at a growth temperature of 950° C., and it was confirmed by X-ray diffraction and electron diffraction that M'gAt in the (10o) orientation was epitaxially grown.
Ｐ ｂ Ｔ ｉ Ｏ３エピタキシャル膜は高周波マグネ
トロンスパッタリング法で作製した。酸化鉛ＰｂＯを１
５モルチだけ過剰に含んだＰｂＴｉＯ３粉末をターゲッ
トに用い、Ａｒ−ＯＨ混合ガス中で、基板温度７００℃
で行なった。ＭｇＡ４０．と同様ＫＸｔＭ回折と電子回
折によって（００１）方位に配向したエピタキシャル膜
であることを確認した。The P b T i O 3 epitaxial film was produced by high frequency magnetron sputtering method. 1 lead oxide PbO
PbTiO3 powder containing an excess of 5 molti was used as a target, and the substrate temperature was 700°C in an Ar-OH mixed gas.
I did it. MgA40. Similarly, it was confirmed by KXtM diffraction and electron diffraction that it was an epitaxial film oriented in the (001) direction.
（実施例２．）
（１００）Ｓｔ単結晶基板上にエピタキシャル成長した
ＭｇＡ／、Ｏ，膜を通してＳｔ基板を熱酸化し、Ｍ ｇ
Ａ ４０．膜とＳｔ基板の間に５ｉ０２を形成したあ
とでＭ ｇ Ａ ４０４ エビタキシャｉ＋４Ｊ：Ｖｃ
Ｐ’ ｂ Ｔ ｉ ０３をエピタキシャル成長させた。(Example 2) (100) The St substrate was thermally oxidized through the MgA/, O, film epitaxially grown on the St single crystal substrate, and the Mg
A40. After forming 5i02 between the film and the St substrate, M g A 404 Ebitaxia i+4J:Vc
P′ b T i 03 was epitaxially grown.
第２図は本実施例の工程図である。４はＳｔ基板、５は
ＭｇＡ４０．エピタキシャル膜、６は５ｉ０２７はＰｂ
Ｔｉ０１のエピタキシャル膜で（ａ）はＭｇＡ１４０４
のエピタキシャル成長工程（ｂ）は熱酸化による８ｉ０
２ｂの形成（ｅ）はＰｂＴｉ０１７のエピタキシャル成
長工程を示す。熱酸化の条件は１１００℃での水蒸気酸
化である。熱酸化によってＭｇＡｔ、Ｏ，の単結晶性は
損なわれなかった。むしろ、Ｘ線ロッキングカーブの半
値幅は３０％はど減少し結晶性は改善された。ＭｇＡ／
、Ｏ，及びＰｂＴｉ０．のエピタキシャル成長は実施例
又と同様の方法によりた。FIG. 2 is a process diagram of this example. 4 is St substrate, 5 is MgA40. Epitaxial film, 6 is 5i027 is Pb
Ti01 epitaxial film (a) is MgA1404
The epitaxial growth step (b) is 8i0 by thermal oxidation.
Formation 2b (e) shows the epitaxial growth process of PbTi017. The thermal oxidation conditions are steam oxidation at 1100°C. The single crystallinity of MgAt, O, was not impaired by thermal oxidation. On the contrary, the half width of the X-ray rocking curve was reduced by 30% and the crystallinity was improved. MgA/
, O, and PbTi0. Epitaxial growth was performed in the same manner as in the example.
（Ｐｂｌ 、、−ｘＬａＸ）（ＺＸｙＴｌ ｚ）Ｏｓい
わゆるＰＬＺＴ膜をエピタキシャル成長した。成分、原
子数ｔ６でｘ ／ ｙ ／ ｚが６ ／ ６５ ／ ３
５のα成長した。成長は実施例１と同様にマグネトロン
スパッター法（実施例４．）
（１００）Ｓｔ単結晶基板上に膜厚８００ＡのＭｇＡ４
０．をエピタキシャル成長しその上にさらに膜厚０．５
μｍのＭｇＯをエピタキシャル成長しノこのち実施例１
と同様に膜厚２μｍのＰｂＴｉＯ３を工。A so-called PLZT film of (Pbl,, -xLaX)(ZXyTl z)Os was epitaxially grown. component, number of atoms t6, x/y/z is 6/65/3
5 α has grown. The growth was carried out by the magnetron sputtering method as in Example 1 (Example 4). MgA4 with a thickness of 800A was grown on a (100)St single crystal substrate.
0. is epitaxially grown and a further film thickness of 0.5
Example 1 of epitaxial growth of μm MgO
Process PbTiO3 with a film thickness of 2 μm in the same manner as above.
ビタキシャル成長した。エピタキシャル温度は７００℃
でバルクのマグネシャ単結晶上に成長するより高温であ
りた。第３図に本実施によりて成るエピタキシャル膜の
構成を示す。８はＳｉ単結晶基板、９はＭｇＡ４０．エ
ピタキシャル膜、１０はＭｇＯエピタキシャル膜、１１
はＰｂＴｌＯ３エビタキシャル膜である。Vitaxial growth. Epitaxial temperature is 700℃
At higher temperatures than growing on bulk magnesia single crystals. FIG. 3 shows the structure of an epitaxial film obtained by this embodiment. 8 is a Si single crystal substrate, 9 is MgA40. Epitaxial film, 10 is MgO epitaxial film, 11
is a PbTlO3 epitaxial film.
以上のように本発明によって、機能性誘電体エピタキシ
ャル膜を容易にシリコン単結晶基板上に形成することが
可能となった。シリコン単結晶基板は大口径で良質のも
のが低価格に入手できること、及び誘電体機能素子とシ
リコンＩＣとを一体化できるという利点を考えれば本発
明の工業的価値は大きい。As described above, the present invention has made it possible to easily form a functional dielectric epitaxial film on a silicon single crystal substrate. The industrial value of the present invention is great considering the advantages that large-diameter, high-quality silicon single-crystal substrates can be obtained at low cost, and that a dielectric functional element and a silicon IC can be integrated.
第１〜３図は本発明による基板の製造プｐセスビタキシ
ャル膜、３，７．１１・・・・・・ＰｂＴｉ０．エピタ
キシャル膜、６・・・・・・５ｉＯ１，１０・・・・・
・ＭｇＯエピタキシャル膜。
オ １ 図
（０）
（ｂ）
オ ２ 図
（０）
（ｂ）
（Ｃ）
オ ３ 図1 to 3 show the manufacturing process of the substrate according to the present invention, p process bitaxial film, 3,7.11...PbTi0. Epitaxial film, 6...5iO1,10...
・MgO epitaxial film. E 1 Fig. (0) (b) O 2 Fig. (0) (b) (C) O 3 Fig.
Claims (4)
ばれる一種以上の元素、ＢとしてＴｉ、Ｚｒの一方また
は両方を含むペロブスカイト型結晶構造を有する誘電体
層が形成されていることを特徴とする電子デバイス用基
板。(1) An insulating film is formed on a silicon single crystal substrate, in which a dielectric layer having a perovskite crystal structure containing one or both of Ti and Zr as one or more elements, B, is formed. Substrates for electronic devices.
マグネシウムアルミネートスピネル（ＭｇＡ４０４ ）
エピタキシャル膜である特許請求の範囲第１項記載の電
子デバイス用基板。(2) The insulator film formed on the silicon single crystal substrate is magnesium aluminate spinel (MgA404).
The electronic device substrate according to claim 1, which is an epitaxial film.
マグネシウムアルミネートスピネル（Ｍ ｇ Ａ ４０
４ ）エピタキシャル膜と、さらにその上に形成される
マクネシア（ＭｇＯ）エピタキシャル膜である特許請求
の範囲第１項記載の電子デバイス用基板。(3) The insulator film formed on the silicon single crystal substrate is made of magnesium aluminate spinel (M g A 40
4) The substrate for an electronic device according to claim 1, which comprises an epitaxial film and a Macnesia (MgO) epitaxial film formed thereon.
該シリコン基板表面に形成される二酸化シリフン（Ｓｉ
ｎ、）層とこの上に形成される絶縁体エピタキシャル膜
とからなる特許請求の範囲第１項記載の電子デバイス用
基板。(4) The insulator film formed on the silicon single crystal substrate is made of silicon dioxide (Si) formed on the surface of the silicon substrate.
2. The electronic device substrate according to claim 1, comprising an insulator epitaxial film formed on the insulator epitaxial film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1735884A JPS60161635A (en) | 1984-02-02 | 1984-02-02 | Substrate for electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1735884A JPS60161635A (en) | 1984-02-02 | 1984-02-02 | Substrate for electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60161635A true JPS60161635A (en) | 1985-08-23 |
Family
ID=11941815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1735884A Pending JPS60161635A (en) | 1984-02-02 | 1984-02-02 | Substrate for electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60161635A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62245205A (en) * | 1986-04-17 | 1987-10-26 | Nec Corp | Thin film optical waveguide and its production |
| JPS6450575A (en) * | 1987-08-21 | 1989-02-27 | Nec Corp | Substrate for electronic device |
| JPH01241876A (en) * | 1988-03-23 | 1989-09-26 | Nec Corp | Substrate for electronic device |
| JPH01241877A (en) * | 1988-03-23 | 1989-09-26 | Nec Corp | Substrate for electronic device |
| US5084438A (en) * | 1988-03-23 | 1992-01-28 | Nec Corporation | Electronic device substrate using silicon semiconductor substrate |
| WO2003007440A3 (en) * | 2001-07-11 | 2003-12-18 | Motorola Inc | Integrated light source for frequency adjustment |
| KR100739098B1 (en) | 2005-12-21 | 2007-07-12 | 주식회사 실트론 | Silicon wafer and manufacturing method thereof |
-
1984
- 1984-02-02 JP JP1735884A patent/JPS60161635A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62245205A (en) * | 1986-04-17 | 1987-10-26 | Nec Corp | Thin film optical waveguide and its production |
| JPS6450575A (en) * | 1987-08-21 | 1989-02-27 | Nec Corp | Substrate for electronic device |
| JPH01241876A (en) * | 1988-03-23 | 1989-09-26 | Nec Corp | Substrate for electronic device |
| JPH01241877A (en) * | 1988-03-23 | 1989-09-26 | Nec Corp | Substrate for electronic device |
| US5084438A (en) * | 1988-03-23 | 1992-01-28 | Nec Corporation | Electronic device substrate using silicon semiconductor substrate |
| WO2003007440A3 (en) * | 2001-07-11 | 2003-12-18 | Motorola Inc | Integrated light source for frequency adjustment |
| KR100739098B1 (en) | 2005-12-21 | 2007-07-12 | 주식회사 실트론 | Silicon wafer and manufacturing method thereof |
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