JPS60160730A - Pcm system receiver - Google Patents

Pcm system receiver

Info

Publication number
JPS60160730A
JPS60160730A JP1511784A JP1511784A JPS60160730A JP S60160730 A JPS60160730 A JP S60160730A JP 1511784 A JP1511784 A JP 1511784A JP 1511784 A JP1511784 A JP 1511784A JP S60160730 A JPS60160730 A JP S60160730A
Authority
JP
Japan
Prior art keywords
input signal
high frequency
tuning
gain control
frequency amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1511784A
Other languages
Japanese (ja)
Inventor
Kazuo Ikeda
池田 和男
Teruo Fujii
藤井 輝雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1511784A priority Critical patent/JPS60160730A/en
Publication of JPS60160730A publication Critical patent/JPS60160730A/en
Pending legal-status Critical Current

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  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE:To attain accurate tuning without depending on an input signal level by applying a constant control voltage independently of a high-frequency input signal carrier level to a gain control circuit for high frequency amplifier at channel selection tuning only. CONSTITUTION:The gain control circuit section 2 for high frequency amplifier is selected at the channel selection tuning only and a constant control voltage independently of the input signal level is applied from a power supply 12 by using a switch 11. Thus, the tuning characteristic of a receiver at a weak input signal is obtained indepedently of the input signal level to obtain a true tuning point.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は,PCM方式受信機に関するもので、高周波入
力信号キャリアレベルを制御する利得制御回路を具備し
たPCM方式受信機に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a PCM receiver, and more particularly to a PCM receiver equipped with a gain control circuit that controls a high frequency input signal carrier level.

〔発明の背景〕[Background of the invention]

第1図は,従来の衛星放送用PCM方式受信機の一例を
示す回路構成図である。
FIG. 1 is a circuit configuration diagram showing an example of a conventional PCM receiver for satellite broadcasting.

第1・図において,高周波増幅器1の出力側には混合器
5,中間周波増幅器6,周波数弁別器e,PCM復調信
号処理回路部9・ビット誤り・車検出回路部10が順次
に接続されている。
In Fig. 1, a mixer 5, an intermediate frequency amplifier 6, a frequency discriminator e, a PCM demodulation signal processing circuit section 9, a bit error/car detection circuit section 10 are connected in sequence to the output side of the high frequency amplifier 1. There is.

そして、上記の高周波増幅器1と中間周波増幅器6との
間κは,高周波増幅器用利得制御回路部2と利得制御用
電圧検出回路部7とが直列に接続され,高周波入力信号
キャリアレベルを一制御する利得制御回路が形成されて
いる。また、上記混合器5には選局端子4を有する可変
局部発振器6が接続されている。
Between the high frequency amplifier 1 and the intermediate frequency amplifier 6, the high frequency amplifier gain control circuit section 2 and the gain control voltage detection circuit section 7 are connected in series to control the high frequency input signal carrier level. A gain control circuit is formed. Further, a variable local oscillator 6 having a tuning terminal 4 is connected to the mixer 5.

従来のPCM方式受信機は上記の回路構成からなるもの
で、以下,その基本動作について説明する。
A conventional PCM receiver has the above-mentioned circuit configuration, and its basic operation will be explained below.

可変局部発振器30選局端子4で、希望信号を選択する
。その出力は混合器5で高周波増幅器1の出力と混合さ
れて中間周波信号に変換される。この中間周波信号は中
間周波増幅器6で。
A desired signal is selected using the variable local oscillator 30 and the channel selection terminal 4. The output is mixed with the output of the high frequency amplifier 1 in the mixer 5 and converted into an intermediate frequency signal. This intermediate frequency signal is sent to an intermediate frequency amplifier 6.

増幅され1周波数弁別器8でFM復調を行ない。The signal is amplified and subjected to FM demodulation by a single frequency discriminator 8.

映像信号と音声信号を周波数分離する。Frequency separation of video and audio signals.

上記音声信号は、PCM方式で伝送されているから、P
CM復調信号処理回路部9で、それぞれ4相npsx復
調およびPCM復調し、デジタル信号から音声信号に変
換する。
Since the above audio signal is transmitted using the PCM method, P
The CM demodulation signal processing circuit section 9 performs four-phase NPSX demodulation and PCM demodulation, respectively, and converts the digital signal into an audio signal.

ビット誤り率検出回路部10は、上記PCM復調信号処
理回路部9で生ずる。PCM信号復隈時の再生ビット誤
り率を検出する回路部である。
The bit error rate detection circuit section 10 is generated in the PCM demodulation signal processing circuit section 9. This is a circuit section that detects the reproduced bit error rate when the PCM signal is recovered.

衛星放送では、特に、音声信号は、PCM方式を採用し
て高忠実度、高品位を図っており。
In satellite broadcasting, the PCM method is used for audio signals in particular to achieve high fidelity and high quality.

音声の良否は、デジタル化音声信号の復調時ビット誤り
率の特性によって決定される。
The quality of the audio is determined by the characteristics of the bit error rate during demodulation of the digitized audio signal.

ビット誤り率は、第2図に示すように、受信機の入力信
号キャリアレベル対雑音レベル比(以下CN比と記す)
に比例する。また、CN比は第3図に示すように、受信
機の同調特性によって変化する。
As shown in Figure 2, the bit error rate is the input signal carrier level to noise level ratio (hereinafter referred to as CN ratio) of the receiver.
is proportional to. Further, as shown in FIG. 3, the CN ratio changes depending on the tuning characteristics of the receiver.

第6図において、実線は弱入力信号時、点線は強入力信
号時の特性である。そのため、受信機の正確な同調点を
得ることが重要となってくる。
In FIG. 6, the solid line shows the characteristic when a weak input signal is applied, and the dotted line shows the characteristic when a strong input signal is applied. Therefore, it is important to obtain an accurate tuning point for the receiver.

従゛来の回路構成では、第1図に示すよ5K。The conventional circuit configuration has 5K as shown in Figure 1.

中間周波増幅器6から入力信号キャリアを取り出し、利
得制御用電圧検出回路部7により入力。
The input signal carrier is taken out from the intermediate frequency amplifier 6 and inputted by the gain control voltage detection circuit section 7.

信号レベルに応じた制御電圧を発生し、この制。Generates a control voltage according to the signal level and controls this.

御電圧を高周波増幅器用利得制御回路部2に印加して利
得制御を行なっている。
A control voltage is applied to the high frequency amplifier gain control circuit section 2 to perform gain control.

しかし、衛星放送での入力信号レベル強度範囲が広いた
め、受信機の高周波増幅器1では。
However, since the input signal level strength range in satellite broadcasting is wide, the high frequency amplifier 1 of the receiver has a wide range of input signal levels.

高利得可変幅をもつ利得制御を行なう必要かあ。Is it necessary to perform gain control with a wide variable gain range?

る。そのため、入力信号周波数に対する同調範囲が広く
なり、受信機の同調をとる際、真の同調点をめるのが困
難であるという問題がある。
Ru. Therefore, the tuning range for the input signal frequency becomes wide, and there is a problem in that it is difficult to find the true tuning point when tuning the receiver.

真の同調点より離調した点で同調をとった場合、第3図
から明らかなように、可変局部発振器乙の温度変化や電
圧変動に対して、CN比、つまりビット誤り率が大きく
劣化し、安定な受信を確保できないという欠点がある。
As is clear from Figure 3, when tuning is performed at a point offset from the true tuning point, the CN ratio, that is, the bit error rate, deteriorates significantly due to temperature changes and voltage fluctuations of the variable local oscillator. However, the disadvantage is that stable reception cannot be ensured.

〔発明の目的〕[Purpose of the invention]

本発明は前述の欠点を除去するためになされたものであ
り、その口重は、容易かつ正確に同調をとることができ
るPCM方式受信機を提供することにある。
The present invention has been made to eliminate the above-mentioned drawbacks, and its primary objective is to provide a PCM receiver that can be tuned easily and accurately.

〔発明の概要〕[Summary of the invention]

前記の目的を達成するために1本発明は、高周波入力信
号キ・リアレベルを制−する利得制御回路を有するPC
M方式受信機にiい−i、4−局同調時だけ、高周波入
力信号キャリアレベル一に依存しない、一定の制御電圧
を上記利得制御回路の構成要素である高周波増幅器用利
得制御回路部に印加する点に特徴かあ−る。
In order to achieve the above object, the present invention provides a PC having a gain control circuit for controlling high frequency input signal key and rear levels.
In the M system receiver, a constant control voltage that does not depend on the high frequency input signal carrier level is applied to the high frequency amplifier gain control circuit section, which is a component of the gain control circuit, only when the 4-station is tuned. It is characterized by the fact that it does.

〔発明の実施例〕[Embodiments of the invention]

以下、図面を参照して本発明の詳細な説明する。第4図
は本発明の一実施例の回路構成図であって、前記第1図
と同一の符号は、同一または同等部分をあられしている
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 4 is a circuit diagram of an embodiment of the present invention, and the same reference numerals as in FIG. 1 represent the same or equivalent parts.

第1図と第4図が異っているのは1選局同調 1時だけ
、高周波増幅器用利得制御回路部2に。
The only difference between Fig. 1 and Fig. 4 is the tuning at 1:1, which is in the high frequency amplifier gain control circuit section 2.

切換えスイッチ11で、入力信号レベルに依存しない、
ある一定の制御電圧を電源12から印加する点である。
With the changeover switch 11, it does not depend on the input signal level.
This is the point where a certain control voltage is applied from the power supply 12.

と記゛制御電圧の電圧値として、高周波増幅器1の出力
レベルが、高周波増幅器用利得制御回路部2によって弱
入力信号レベル時のキャリアレベルになるような電圧値
を選定しておけば。
As the voltage value of the control voltage, a voltage value is selected such that the output level of the high frequency amplifier 1 becomes the carrier level at the weak input signal level by the high frequency amplifier gain control circuit section 2.

入力信号レベルに依存することなく1弱入力信号時での
受信機の同調特性を得ることになる。
The tuning characteristics of the receiver when the input signal is weaker than 1 can be obtained without depending on the input signal level.

上記のように構成されたPCM方式受信機においては、
第2図及び第5図より、受信機の同調時、離調周波数に
対して、CN比およびビット誤り率が大幅に変化し、ビ
ット誤り率検出回路部100ビット誤り率の最小点を1
選局端子4で希望信号を変えてめるだけで、入力信号レ
ベルに関係なく、受信機の真の同調点をめることが出来
る。
In the PCM receiver configured as above,
From Figures 2 and 5, when tuning the receiver, the CN ratio and bit error rate change significantly with respect to the detuning frequency, and the minimum point of the 100 bit error rate in the bit error rate detection circuit section is 1.
By simply changing the desired signal at the tuning terminal 4, the true tuning point of the receiver can be set regardless of the input signal level.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように1本発明によれば、入力
信号レベルに依存することなく、ビット誤り率の最小点
をめることができ、PC・M方式受信機の正確な真の同
調点を容易、かつ、正確に得られ、安定な受信機性能が
確保できるという効果が達成される。
As is clear from the above description, according to the present invention, the minimum point of the bit error rate can be determined without depending on the input signal level, and the accurate true tuning point of the PC/M system receiver can be determined. can be obtained easily and accurately, and stable receiver performance can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の衛星放送用PCM方式受信機の回路構
成図、第2図は、CM比対ビット誤り率の特性図、第3
図は、受信機の離調周波数対CN比の特性図、第4図は
1本発明PCM方式受信機の一実施例を示す回路構成図
である。 1・・・高周波増幅器、2・・・高周波増幅器用利轡制
御回路部、3・・・可変局部発振器、4・・・選局端子
、5・・・混合器、6・・・中間周波増幅器、7・・・
利得制御用電圧検出回路部、8・・・周波数弁別器。 9・・・PCM復調信号処理回路部、10・・・ビット
誤り車検出回路部、11・・・切換えスイッチ、12・
・・電。 第 l 閉 第2WIJ 第3胆 CNl−乙<a5> −Jl&’m馬派奴第 4 図 工X12
Figure 1 is a circuit configuration diagram of a conventional PCM receiver for satellite broadcasting, Figure 2 is a characteristic diagram of CM ratio versus bit error rate, and Figure 3
4 is a characteristic diagram of the detuning frequency versus CN ratio of the receiver, and FIG. 4 is a circuit configuration diagram showing an embodiment of the PCM receiver according to the present invention. DESCRIPTION OF SYMBOLS 1... High frequency amplifier, 2... Usage control circuit section for high frequency amplifier, 3... Variable local oscillator, 4... Tuning terminal, 5... Mixer, 6... Intermediate frequency amplifier ,7...
Gain control voltage detection circuit section, 8... frequency discriminator. 9... PCM demodulation signal processing circuit section, 10... Bit error vehicle detection circuit section, 11... Changeover switch, 12.
...Electric. No. 1 Closing 2nd WIJ 3rd bile CNl-Otsu<a5>-Jl&'m horse school guy No. 4 Artwork X12

Claims (1)

【特許請求の範囲】 (1)高周波増幅器と中間周波増幅器との間に、高周波
増幅器用利得制御回路部と利得制御回路。 圧検出回路部とからなり、高周波入力信号キャリアレベ
ルを制御する利得制御回路を具備したPCM方式受信機
において1選局同調時だけ上記高周波入力信号キャリア
レベルに依存しない一定の制御電圧を、上記高周波増幅
器用利得制御。 御回終部に印加する一定の制御電圧印加手段を設けたこ
とを特徴とするPCM方式受信機。 (2)一定の制御電圧印加手段は、を源と、こり電源を
選局同調時だけ、利得制御用電圧検出回路部からの制御
信号に代えて高周波増幅器用オシ−1得制御回路部に接
続する切換えスイッチと、からなることを特徴とする特
許 (1)項記載のPCM方式受信機。
[Claims] (1) A high frequency amplifier gain control circuit section and a gain control circuit between the high frequency amplifier and the intermediate frequency amplifier. In a PCM receiver equipped with a gain control circuit that controls the high frequency input signal carrier level, a constant control voltage that does not depend on the high frequency input signal carrier level is applied to the high frequency input signal only when tuning to one channel. Gain control for amplifiers. A PCM receiver characterized in that it is provided with means for applying a constant control voltage to the end of the signal. (2) The constant control voltage applying means is connected to the oscillator gain control circuit for the high frequency amplifier in place of the control signal from the gain control voltage detection circuit only when tuning the channel. 1. A PCM receiver according to Patent (1), characterized in that the PCM receiver is comprised of a changeover switch for switching.
JP1511784A 1984-02-01 1984-02-01 Pcm system receiver Pending JPS60160730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1511784A JPS60160730A (en) 1984-02-01 1984-02-01 Pcm system receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1511784A JPS60160730A (en) 1984-02-01 1984-02-01 Pcm system receiver

Publications (1)

Publication Number Publication Date
JPS60160730A true JPS60160730A (en) 1985-08-22

Family

ID=11879881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1511784A Pending JPS60160730A (en) 1984-02-01 1984-02-01 Pcm system receiver

Country Status (1)

Country Link
JP (1) JPS60160730A (en)

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