JPS60158622A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60158622A JPS60158622A JP59011930A JP1193084A JPS60158622A JP S60158622 A JPS60158622 A JP S60158622A JP 59011930 A JP59011930 A JP 59011930A JP 1193084 A JP1193084 A JP 1193084A JP S60158622 A JPS60158622 A JP S60158622A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electron beam
- electrons
- resist
- substance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置の製造方法に係り、特に近接効果が
少なく且つ半導体素子への電子線照射による損傷の少な
い電子線描画法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an electron beam lithography method that causes less proximity effect and less damage to semiconductor elements due to electron beam irradiation.
従来の電子線描画法では、電子線のレジスト中での散乱
や、基板からの後方散乱により電子線の入射点より遠い
所までその影響を及ぼしパターンの転写精度が悪くなる
と共に入射した電子が基板深くまで侵入するためその際
に生ずる損傷が、素子初期特性や信頼性を大きく損うと
いう欠点があった。In conventional electron beam lithography, the scattering of the electron beam in the resist and the back scattering from the substrate affect areas far from the electron beam's incident point, resulting in poor pattern transfer accuracy and the incident electrons collapsing onto the substrate. Since it penetrates deeply, the damage that occurs at that time has the disadvantage that it greatly impairs the initial characteristics and reliability of the device.
本発明の目的はこの近接効果を低減し、図形の転写精度
を向上させるとともに、半導体素子に与える損傷を低減
し、信頼性の向上と特性の安定化が可能な電子線描画法
を提供することにある。An object of the present invention is to provide an electron beam lithography method that can reduce this proximity effect, improve pattern transfer accuracy, reduce damage to semiconductor elements, improve reliability, and stabilize characteristics. It is in.
固体中に注入された電子線は第１図に示すように固体を
形成する原子と衝突し一部のエネルギーを失いながら散
乱され、再び衝突を繰り返し、固体内で全てのエネルギ
ーを失い停止するが（１）、再び固体から外部へ飛散す
る（２）ことが知られている。一般に比重の重い物質又
は原子量の大きな物質は散乱するカが強いので電子の侵
入深さは浅くなり、多くの電子が後方に散乱される。従
って第２図に示すように比重の大きな物質又は原子量の
大きな物質２を半導体基Ｆｉ３に被着することにより、
電子の半導体基板への侵入を阻止し基板に対する損傷を
低減することができる。しかし重い物質は、入射した電
子を強く散乱するため、電子の入射点より遠く離れた位
置までその影響を及ぼす。このように電子の入射点より
離れた位置でも電子が飛来すると、その部分も電子線を
照射したと同等になるという問題がある。特に２つの図
形の間隔が近づいてくるとその間の部分が感光してしま
い、２つの図形が連ってしまうことになる。As shown in Figure 1, an electron beam injected into a solid collides with the atoms forming the solid, loses some of its energy, and is scattered.The electron beam repeats the collision again, and then it loses all its energy within the solid and stops. It is known that (1), and (2) the particles scatter again from the solid to the outside. In general, substances with heavy specific gravity or substances with large atomic weight have a strong scattering force, so the penetration depth of electrons becomes shallow, and many electrons are scattered backward. Therefore, as shown in FIG. 2, by depositing a substance 2 with a large specific gravity or a substance 2 with a large atomic weight on the semiconductor base Fi3,
It is possible to prevent electrons from entering the semiconductor substrate and reduce damage to the substrate. However, heavy substances strongly scatter the incident electrons, which affects locations far away from the point of incidence of the electrons. In this way, if electrons fly to a position far from the electron incident point, there is a problem in that the area becomes equivalent to being irradiated with an electron beam. In particular, if the distance between two figures gets closer, the part between them will be exposed to light, and the two figures will become connected.
これを近接効果と呼ぶ１重い物質を基板上に被着すると
そこからの反射電子が多くなり、この近接効果が大きく
なるという問題が生じる。そこで第３図に示すように重
い物質層７を電子線レジスト層６の直下におく。ここで
重い物質層７は入射した電子のエネルギーに対し十分薄
く、すなわ′ち電子が十分通過できる程度の厚さにして
おくことにより、レジスト層への後方散乱を小さくでき
る。This is called the proximity effect.If a heavy substance is deposited on a substrate, a large number of reflected electrons will be reflected from the substance, causing a problem that the proximity effect will become larger. Therefore, as shown in FIG. 3, a heavy material layer 7 is placed directly below the electron beam resist layer 6. By making the heavy material layer 7 sufficiently thin with respect to the energy of the incident electrons, that is, having a thickness sufficient to allow the electrons to pass through, backscattering to the resist layer can be reduced.
この重い物質層７の下には加工用のレジス１一層５を厚
く置く。この層には比重の軽いものでドライエツチング
耐性の高いものとして通常の感光性樹脂等を選ぶ。加工
用レジスト層５の下に第２の重い物質層２を設ける。入
射した電子線は電子線レジスト層６、第１の重い物質層
７、加工用レジスト層５によりその一部のエネルギーを
失いながら第２の重い物質層２に突入する。ここでほと
んどの電子は後方散乱され、基板３に到達する電子は著
しく少なくなる。−右後方散乱された電子は再び厚い加
工用レジスト層５中でエネルギーを失いながら第１の重
い物質層７に到達する。しかしもはやこの層を通過する
エネルギーを持たない。従って入射した電子の大部分は
この重い物質層２゜７間に閉じこめられることになる。Under this heavy material layer 7, a thick layer of resist 1 and layer 5 for processing are placed. For this layer, an ordinary photosensitive resin or the like is selected as it has a light specific gravity and is highly resistant to dry etching. A second heavy material layer 2 is provided below the processing resist layer 5. The incident electron beam enters the second heavy material layer 2 while losing part of its energy through the electron beam resist layer 6, first heavy material layer 7, and processing resist layer 5. Here, most of the electrons are backscattered and significantly fewer electrons reach the substrate 3. - The right backscattered electrons reach the first heavy material layer 7 while losing energy again in the thick resist layer 5 for processing. However, it no longer has the energy to pass through this layer. Therefore, most of the incident electrons will be confined between this heavy material layer 2.7.
従って表面層の電子線レジストは入射した電子のみに感
光し、基板３からの後方散乱の影響が少なくなるため、
近接効果が低減される。Therefore, the electron beam resist in the surface layer is exposed only to the incident electrons, and the influence of backscattering from the substrate 3 is reduced.
Proximity effect is reduced.
以下、本発明の一実施例を第４図により説明する。ＭＯ
８素子を形成した半導体基板３上に形成した１μｍのＡ
Ω配線金ａ８上にＷ膜９を２００〇八被着し、その上に
加工用のレジスト層１３としてＡＺ１３５０Ｊを２μｍ
厚に回転塗布し、ついで、Ｗ暎９を５Ｑ０八被へする。An embodiment of the present invention will be described below with reference to FIG. M.O.
A of 1 μm formed on the semiconductor substrate 3 on which 8 elements were formed.
A 20008 W film 9 is deposited on the Ω wiring gold a8, and a 2 μm thick AZ1350J film is applied thereon as a resist layer 13 for processing.
Spin coat thickly, then apply W 9 to 5Q0 8 coats.
最後に電子線レジストＣＭＳ６を５０００八回転塗布す
る。次に電子線を加速電圧３０ＫＶで２０μＣ／ｃＩＩ
Ｔ照射する（第４図（ａ））。Finally, an electron beam resist CMS6 is applied 5000 times. Next, the electron beam was
T irradiation is performed (Fig. 4(a)).
」ユ記ＣＭＳを現像後Ｗ＠９をドライエツチングしつい
で下層のＡ’Ｚ１３５０Ｊ ｌ ３を０２プラズマ中で
反応性スパッタエッチし厚いレジストパターンを形成す
る（第４巨１（ｂ））。次いでＷ膜９、ＡＱ膜８逐次エ
ツチングしてＭ ＯＳ素子の配線層を形成していた。After developing CMS, W@9 is dry etched, and the lower layer A'Z1350J13 is reactive sputter etched in 02 plasma to form a thick resist pattern (4th macro 1(b)). Next, the W film 9 and the AQ film 8 were sequentially etched to form a wiring layer for the MOS device.
この結果、多層レジスト膜中のタングステン膜９のかわ
りにシリコン膜又は酸化シリコン膜を用いた場合ＡＱ層
の加工精度が１ｐｍ配線において設計値より０．３μｍ
もシフトしていたのに対しＷ膜を用いることによりシフ
ト量が０．１μｍ以内となった。また電子線照射による
しきい値電圧も光学法に比べ２００ｍＶもシフトシてい
たのに対し、ＡＱ層上にタングステン膜を被着すること
により］、ＯｍＶ以下と著しく低減された。As a result, when a silicon film or a silicon oxide film is used instead of the tungsten film 9 in the multilayer resist film, the processing accuracy of the AQ layer is 0.3 μm lower than the design value for 1 pm wiring.
However, by using the W film, the amount of shift was within 0.1 μm. Furthermore, while the threshold voltage due to electron beam irradiation was shifted by 200 mV compared to the optical method, it was significantly reduced to below OmV by depositing a tungsten film on the AQ layer.
本発明の別の実施例を第５図で説明する。第１の実施例
と同様に半導体基板３上にへΩ膜８、Ｗ膜９を被着した
上に下地基板加工用レジスト１３としてＡ Ｚ １３５
０ Ｊを１．７μｍ回転塗布しつづいてヨー素化ポリス
チレン１５を０．５μｍ塗布する。次に電子線を３０Ｋ
Ｖで３０μＣ／ａｌ照射しヨー素化ポリスチレン１５を
現偉し、該ヨー素化ポリスチレン１５をマスクに下層の
ＡＺ１３５０Ｊ膜１３を０２プラズマ中で反応性イオン
エツチングする。ついで下地Ｗ膜９、ＡＱ膜８をエツチ
ングしてＭＯ８素子を完成させる。この結果最初の実施
例とほぼ同様の効果を得た。Another embodiment of the invention will be described with reference to FIG. As in the first embodiment, the Ω film 8 and the W film 9 are deposited on the semiconductor substrate 3, and then A Z 135 is applied as a resist 13 for base substrate processing.
0 J to a thickness of 1.7 μm, and then iodinated polystyrene 15 to a thickness of 0.5 μm. Next, apply an electron beam to 30K.
The iodinated polystyrene 15 is exposed by 30 μC/al irradiation with V, and the lower AZ1350J film 13 is subjected to reactive ion etching in 02 plasma using the iodinated polystyrene 15 as a mask. Next, the underlying W film 9 and AQ film 8 are etched to complete the MO8 element. As a result, almost the same effect as the first example was obtained.
本発明の第３の実施例を第６図に示す。本実施例では第
２の実施例のヨー素化ポリスチレン１５のかわりにタン
グステンオキサイド膜あるいはモリブデンオキサイド膜
１６を用いた。ここで電子線は５ＫＶの加速電圧で１０
０μＣ／ａ＃とした。A third embodiment of the invention is shown in FIG. In this embodiment, a tungsten oxide film or a molybdenum oxide film 16 was used in place of the iodinated polystyrene 15 of the second embodiment. Here, the electron beam is 10
It was set to 0 μC/a#.
この場合も第１の実施例と同様の効果を得た。In this case as well, the same effects as in the first embodiment were obtained.
第７図に本発明の第４の実施例を示す６本実施例ではＡ
Ｑ配線層を図に示すように２ＭのＡＱ層８にはさまれた
Ｔ ｒｈ １４１７を用いることにより実施例１〜３に
示したＡＱ層上のＷ層と同様の効果を得た。FIG. 7 shows a fourth embodiment of the present invention. In this embodiment, A
By using T rh 1417 sandwiched between 2M AQ layers 8 as the Q wiring layer as shown in the figure, the same effect as the W layer on the AQ layer shown in Examples 1 to 3 was obtained.
第８回に本発明の第５の実施例を示す。本実施例ではＡ
０配線層は１層のへΩ膜８を用い、多層レジスト層の中
間膜を２層のタングステン膜９にした例を示す。本方法
でも実施例１と同様の効果を得た。The fifth embodiment of the present invention will be shown in the eighth session. In this example, A
An example is shown in which a single layer of Ω film 8 is used for the 0 wiring layer, and two layers of tungsten film 9 are used as the intermediate film of the multilayer resist layer. The same effects as in Example 1 were obtained with this method as well.
第９図に本発明の第６の実施例を示す。本実施例ではＡ
Ｑ配線層をＡＱ層とＴａ層の多層膜としＡｎ層８ ／
’１’ ａ層１７／Ａｆ１層８ ／ Ｔ ａ層１７／Ａ
Ω層８という構造にし、Ｔａ層とＡＱ層間に電子線を閉
じ込めた。この場合多層レジスト層の中間Ｍ１８にはＳ
ｉ膜を用いた。FIG. 9 shows a sixth embodiment of the present invention. In this example, A
The Q wiring layer is a multilayer film of AQ layer and Ta layer, and An layer 8/
'1' a layer 17/Af1 layer 8/T a layer 17/A
A structure called Ω layer 8 was used, and the electron beam was confined between the Ta layer and the AQ layer. In this case, in the middle M18 of the multilayer resist layer, S
i membrane was used.
本発明によれば入射した電子はレジス１へｍおよび被加
工層又はレジスト層内の重い物質層間に閉じこめられ、
半導体基板中への電子の注入及び、表面の電子線レジス
ト層への後方散乱が低減できるので、近接効果の緩和や
素子の電子線照射による損傷低減の効果がある。According to the present invention, the incident electrons are confined between the resist 1 m and the heavy material layer in the processed layer or the resist layer,
Since injection of electrons into the semiconductor substrate and backscattering to the electron beam resist layer on the surface can be reduced, there is an effect of alleviating the proximity effect and reducing damage to elements caused by electron beam irradiation.
ＷＳ１図は電子線の固体中での散乱を示す図、第２図は
重金属が半導体表面に被着した場合の電子線の散乱を示
す図、第３図は本発明の詳細な説明するための図、第４
図乃至第９図は本発明の詳細な説明するための図である
。
■・・・固体、２・・・重金属又は比重の大きな物質、
３・・・半導体基板、４・・・被加工物質、５山比較的
比重の小さな物質、６・・・電子線レジスト、７・・・
薄い重金属又は比重の大きな物質、８・・・ＡＱ膜、９
・・・Ｗ膜、１０・・・リンガラス保護膜、１１由拡散
層、１２・・・ゲート金属、１３・・・下層１ノジスト
膜、１４・・・フィールド酸化膜、１５・・・コー素化
ポリスチレン膜、１６・・・タングステンオキサイド膜
又はモリブデンオキサイド膜、１７・・・タンタル膜、
１８・・・第 ｌ 図
第 ２ 凹
弗 ４ の
（α）
第 ５ 国
ｅ−
第 ６ 屈
第 ７ 目Figure WS1 is a diagram showing the scattering of an electron beam in a solid, Figure 2 is a diagram showing the scattering of an electron beam when heavy metals adhere to the semiconductor surface, and Figure 3 is a diagram for explaining the present invention in detail. Figure, 4th
9 to 9 are diagrams for explaining the present invention in detail. ■...Solid, 2...Heavy metals or substances with large specific gravity,
3... Semiconductor substrate, 4... Material to be processed, 5 Material with relatively low specific gravity, 6... Electron beam resist, 7...
Thin heavy metal or substance with high specific gravity, 8...AQ film, 9
... W film, 10... Phosphorous glass protective film, 11 Yu diffusion layer, 12... Gate metal, 13... Lower layer 1 nodist film, 14... Field oxide film, 15... Co oxidized polystyrene film, 16... tungsten oxide film or molybdenum oxide film, 17... tantalum film,
18...L Figure 2 Concave 4 (α) 5th country e- 6th 7th
Claims (1)
画法において、基板上に被着した１層以上の被加工物質
層および該被加工物質層上に形成した１層以上のレジス
ト層からなる多層膜構造で該多層膜を形成している層の
うち少なくとも２層が半導体基板を構成する物質より比
重の重いものからなり、該比重の重い物質層間に少なく
とも１層以上の半導体基板を構成する物質と同じか軽い
比重の物質が存在する多層膜構造を用いて図形を転写す
ることを特徴とする半導体装置の製造方法。In an electron beam lithography method that uses an electron beam to transfer a figure onto a semiconductor substrate, from one or more processed material layers deposited on the substrate and one or more resist layers formed on the processed material layers. In a multilayer film structure, at least two of the layers forming the multilayer film are made of a substance having a higher specific gravity than a substance constituting the semiconductor substrate, and at least one or more semiconductor substrate layers are formed between the layers of the substance having a higher specific gravity. 1. A method for manufacturing a semiconductor device, characterized in that a figure is transferred using a multilayer film structure in which a substance having a specific gravity equal to or lighter than that of a substance to be attached is present.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59011930A JPS60158622A (en) | 1984-01-27 | 1984-01-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59011930A JPS60158622A (en) | 1984-01-27 | 1984-01-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60158622A true JPS60158622A (en) | 1985-08-20 |
Family
ID=11791389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59011930A Pending JPS60158622A (en) | 1984-01-27 | 1984-01-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60158622A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015531169A (en) * | 2012-08-08 | 2015-10-29 | コミサリヤ・ア・レネルジ・アトミク・エ・オ・エネルジ・アルテルナテイブ | High resolution electron lithography substrate and corresponding lithography method |
-
1984
- 1984-01-27 JP JP59011930A patent/JPS60158622A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015531169A (en) * | 2012-08-08 | 2015-10-29 | コミサリヤ・ア・レネルジ・アトミク・エ・オ・エネルジ・アルテルナテイブ | High resolution electron lithography substrate and corresponding lithography method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7229745B2 (en) | Lithographic semiconductor manufacturing using a multi-layered process | |
| US4035522A (en) | X-ray lithography mask | |
| KR100319672B1 (en) | Pattern exposure method using electron beam | |
| US4612275A (en) | Multilayer resists with improved sensitivity and reduced proximity effect | |
| US5030549A (en) | Fine pattern forming method | |
| JPS60158622A (en) | Manufacture of semiconductor device | |
| JPS6239817B2 (en) | ||
| US4745044A (en) | Multilayer resists with improved sensitivity and reduced proximity effect | |
| US5186788A (en) | Fine pattern forming method | |
| JP3118887B2 (en) | Pattern formation method | |
| JPH03138922A (en) | Minute-pattern forming method | |
| JP2827992B2 (en) | Method of forming fine pattern | |
| JPH01220829A (en) | Pattern forming method | |
| JPS607131A (en) | Pattern formation | |
| JPS6015920A (en) | Manufacture of semiconductor device | |
| JPS5893327A (en) | Minute processing method | |
| Yi et al. | Proximity-effect correction in electron-beam lithography on metal multi-layers | |
| KR100299004B1 (en) | Method of drawing a pattern by direct writing with charged particle beam | |
| JP2752022B2 (en) | Fine pattern forming method | |
| JPH0658875B2 (en) | X-ray mask and pattern forming method using the same | |
| Wolfstädter | Electron beam fabrication of 0.2 μm lines, suitable for GaAs MMIC processing | |
| KR930000874B1 (en) | Patterning method of substrate in triple layer resist process | |
| JPS60123842A (en) | Production of photomask | |
| JPS6351637A (en) | Mask forming method | |
| JPS5934632A (en) | Manufacture of x-ray mask |