JPS5893327A - Minute processing method - Google Patents
Minute processing methodInfo
- Publication number
- JPS5893327A JPS5893327A JP19223581A JP19223581A JPS5893327A JP S5893327 A JPS5893327 A JP S5893327A JP 19223581 A JP19223581 A JP 19223581A JP 19223581 A JP19223581 A JP 19223581A JP S5893327 A JPS5893327 A JP S5893327A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- processed
- photoresist
- organic material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000011368 organic material Substances 0.000 claims description 19
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000007687 exposure technique Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 4
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 229910000838 Al alloy Inorganic materials 0.000 abstract 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 description 1
- 235000008708 Morus alba Nutrition 0.000 description 1
- 240000000249 Morus alba Species 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分針
本発明は、微細加工法に係わり、轡に段差を有する下地
表面上での微細加工法に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a microfabrication method, and more particularly, to a microfabrication method on a base surface having a step on the back.
発明の技術的背景とその問題点
従来、半導体素子等の製造工程において段差や凹凸を有
する基板上に微細パターンを形成し−ようと試みる場合
、基板形状に起因する積層膜の膜厚不均一性、或いはレ
ジストパターンの解儂度低下が生じ、微細パターンを高
精度に形成する上での大きな障害となっている。これら
の問題に対し、例えば配線パターンを形成する際には配
線材料膜を設ける前に下地絶縁膜の平坦化を行う試み、
或いは平坦な中間層を設けた多層構造方式のパターン形
成方法により配線材料膜上に設けるレジストパターンの
解像変向上をはかる試みが成されている。前者について
は、例えば文献（５６年、秋季応用物理宇金３１ａ−Ｎ
−５）、後者については文＃（１）Ｍ、 ８． Ｃｈａ
ｕｇ。Technical background of the invention and its problems Conventionally, when attempting to form a fine pattern on a substrate with steps or unevenness in the manufacturing process of semiconductor devices, non-uniformity in the thickness of the laminated film due to the shape of the substrate occurs. Alternatively, the degree of decomposition of the resist pattern may be lowered, which is a major hindrance to forming fine patterns with high precision. To solve these problems, for example, when forming wiring patterns, attempts have been made to flatten the underlying insulating film before forming the wiring material film.
Alternatively, attempts have been made to improve the resolution of a resist pattern formed on a wiring material film using a pattern forming method using a multilayer structure in which a flat intermediate layer is provided. Regarding the former, for example, refer to the literature (1956, Autumn Applied Physics Ugane 31a-N
-5), for the latter sentence #(1)M, 8. Cha
ug.
Ｌ Ｄ、Ｌｉｔ ａｍｄ Ｍ、Ｍ、σ丁ｅｅｌｓ
＊ ｌ ９ ８ １８Ｆ１１１？ｇ１１１１１＠ｏ
ｎ ＶＬＩｉＩ Ｔ＠＠ｈｎｏｌｏｇｙ ｌ ９８１
／Ｓ＠ｐｔ＠ｍｂ＠ｒ ｉ’ ８ ” ９ 、（２）
Ｊ、 Ｌ Ｍｏｒａｎ ａｎｄ Ｄ。L D, Lit amd M, M, σdingeels
* l 9 8 18F111? g11111@o
n VLIiI T@@hnology l 981
/S@pt@mb@r i' 8 ” 9, (2)
J, L Moran and D.
Ｍ、 Ｍａｙｄａｎ 、 Ｊ、 Ｖａｔ、８＠１． Ｔ
＠ｃｈｎｏｌ＠ｇｙ ｌ ６ ＊１６２０（１９７９）
、（３１Ｊ、 Ｈｅ Ｂｒａｇｉｍｇ。M, Maydan, J, Vat, 8@1. T
@chnol@gy l 6 *1620 (1979)
, (31J, He Bragimg.
Ｊ、Ｖａｃ、Ｓｅｔ、Ｔｅｃｈｎｏｌ １７ ．１１
４７（１９８０χ（４）Ｂ、Ｃａｒｌｓｏｎ ａｎｄ
Ｊ、Ａｒｎｏｌｄ 、ＫｏｄａｋＭｉｃｒｏｓ−
１＠ｃｔｒｏｎｉｅｓ＋ ８・ｍ１ｆｉａｒ、Ｓａｗ
Ｄｉｅｇｏ、ＣａｌｌｔｏｒｍＯｃｔｏｂｅｒ、 １９
８０ 等に記載されている。J, Vac, Set, Technol 17. 11
47 (1980χ(4)B, Carlson and
J, Arnold, Kodak Micros-
1@ctronies+ 8・m1fire, Saw
Diego, Calltorm October, 19
80 etc.
しかしながら、上述した方法を用いて微細加工を試みて
も得られる平坦性は不十分であり、十分高解儂度な加工
処理は成されなかった。これは、スピンコード法により
設けられる有機物質膜は急峻な形状を緩やかな滑らかな
膜面で覆うが、有機物質膜厚に比べ十分に広い領域にお
いては一定の膜厚となり、基板表面の高低差が反映され
るためである。すなわち、従来方法においては十分な平
坦化が成されず単に急峻な形状をゆるやかな形状−こす
るにとどまっており、これがために高解儂度の加工処理
を行い得なかった。However, even if microfabrication was attempted using the above-mentioned method, the obtained flatness was insufficient, and a sufficiently high-resolution machining process was not achieved. This is because the organic material film provided by the spin code method covers a steep shape with a gentle and smooth film surface, but the film thickness remains constant over a sufficiently wide area compared to the organic material film thickness, and the difference in height of the substrate surface This is because it is reflected. In other words, in the conventional method, sufficient flattening is not achieved and a steep shape is simply rubbed into a gentle shape, and for this reason, processing with a high degree of resolution cannot be performed.
発明の目的
本発明の目的は、表面段差のある被加工膜を完全に平坦
化することができ、微細パターン形を提供することにあ
る。OBJECTS OF THE INVENTION An object of the present invention is to provide a fine pattern that can completely flatten a processed film having surface steps.
発明の概要
本発明は、凹凸を有する下地表面上に設けられた被加工
膜上にレジストを塗布したのち、露光技術を用い上記レ
ジストを上記被加工膜の凹部の幅の広い部分にのみ選択
的に残存せしめ、次いで上記レジスト上および被加工膜
上に有機物質膜を回転塗布して線表面を平坦化し、しか
るのちドライエツチング技術を用い前記被加工膜と有機
物質膜との各エツチング速度が略等しく、かつ前記レジ
ストのエツチング速度が上記被加工膜および有機物質膜
のエツチング速度と略等しいか或いは小さい条件下で前
記有機物質膜の表面から全面エツチング処理するように
した方法である。SUMMARY OF THE INVENTION The present invention involves coating a resist on a film to be processed that is provided on a base surface having irregularities, and then selectively applying the resist only to the wide portions of the concave portions of the film to be processed using an exposure technique. Then, an organic material film is spin-coated on the resist and the film to be processed to flatten the line surface, and then dry etching technology is used so that the etching rates of the film to be processed and the organic material film are approximately equal to each other. In this method, the entire surface of the organic material film is etched under conditions in which the etching rate of the resist is substantially equal to or smaller than the etching rates of the film to be processed and the organic material film.
発明の効果 ：：
本発明によれば、被加工膜を同一高さにエツチングする
ことができ、被加工膜を完全に平坦化することができる
。このため、被加工膜の表面凹凸に起因するレジスト解
像度の低下等を未然に防止することができ、加工精度の
向上に寄与し得る。Effects of the Invention: According to the present invention, the film to be processed can be etched to the same height, and the film to be processed can be completely flattened. Therefore, it is possible to prevent a decrease in resist resolution caused by surface irregularities of the film to be processed, and this can contribute to improving processing accuracy.
発明の実施例
ＩＥＩ図（龜）〜＆）は本発明の一実施例を示す工程断
面図である。まず、第１図（ａ）に示す如きシリコン基
板ｌ上に絶縁膜２およびムＩ合金膜３が形成された凹凸
のある下地表面上にシリコン酸化ＩＩ（被加工膜）４を
被着した。なお、図中５は能動領域を示している。この
状態でシリコン酸化＠４の表面には大小の凹凸が複数存
在している。次に、第１図（ｂ）に示す如くシリコン酸
化＄４上にポジ型フォトレジスト６をスピンコードした
。続いて、露光技術を用いレジストＣを所望パターンに
露光し、第１図（ｃ）に示す如くシリコン酸化ｌ！４の
凹部の幅が広い部分にのみレジスト６を残存せしめた。Embodiment of the Invention Figures IEI and IE are process sectional views showing an embodiment of the present invention. First, silicon oxide II (film to be processed) 4 was deposited on the uneven base surface on which an insulating film 2 and a MuI alloy film 3 were formed on a silicon substrate 1 as shown in FIG. 1(a). Note that 5 in the figure indicates an active area. In this state, a plurality of large and small irregularities exist on the surface of silicon oxide@4. Next, as shown in FIG. 1(b), a positive type photoresist 6 was spin-coded on the silicon oxide layer 4. Subsequently, the resist C is exposed to a desired pattern using an exposure technique, and silicon oxide l! is formed as shown in FIG. 1(c). The resist 6 was left only in the wide portion of the recess 4.
そして、この状態での表面層は幅の狭い凹部のみが存在
することになる。In this state, the surface layer has only narrow recesses.
次に、第１図（ａ）に示す如くシリコン酸化膜４上およ
びレジスト５上に有機物質Ｉ１１をスピンコードし核表
面を平坦化した。ここで、有機物質膜１としてはポジ臘
フォトレジスト液とポリメチルメタクリレートのエチル
セロリルブアセテート溶液とを混合した混合液を用いた
。そして、この混合液が後述するエツチングの際シリコ
ン酸化膜４のエツチング速度と等しくなるよう調整した
。有機物質膜１の表面は下地表面の凹部の幅が狭いため
略完全に平坦化された。Next, as shown in FIG. 1(a), an organic substance I11 was spin-coated on the silicon oxide film 4 and the resist 5 to flatten the surface of the nucleus. Here, as the organic substance film 1, a mixed solution of a positive photoresist solution and an ethyl celeryl acetate solution of polymethyl methacrylate was used. This mixed solution was adjusted to be equal to the etching rate of the silicon oxide film 4 during etching, which will be described later. The surface of the organic material film 1 was almost completely flattened because the width of the concave portion on the underlying surface was narrow.
次に、ＣＦ、と■、との混合ガスを反応性ガスとする反
応性イオンエツチング技術を用い有機物質膜１を全面エ
ツチングした。このとき、シリコン酸化膜４、レジスト
＃および有機物質膜１のエツチング速度が略等しくなる
条件を選んだことにより、有機物質膜１、レジスト６お
よびシリコン酸化膜４を第１図（・）に゛示す如く同じ
深さにエツチングすることができた。これにより、ムｌ
合金膜、からなる下地凹部にシリコン酸化膜４を平坦
な状態で埋め込むことができた。Next, the entire surface of the organic material film 1 was etched using a reactive ion etching technique using a mixed gas of CF, and (2) as a reactive gas. At this time, by selecting conditions such that the etching rates of the silicon oxide film 4, the resist #, and the organic material film 1 are approximately equal, the organic material film 1, the resist 6, and the silicon oxide film 4 are formed as shown in FIG. As shown, etching could be done to the same depth. This makes it possible to
The silicon oxide film 4 was able to be buried in a flat state in the base recess made of the alloy film.
次に、シリコン酸化膜４およびムｌ 合金膜１からなる
下地表面上にシリコン酸化膜１を堆積シリコン酸化膜８
の表面が完全に平坦化されるので、後続するシリコン酸
化ＨＳ上での微細加工、が極めて容易となる。Next, a silicon oxide film 1 is deposited on the base surface consisting of the silicon oxide film 4 and the mulberry alloy film 1.
Since the surface of the silicon oxide HS is completely flattened, subsequent microfabrication on the silicon oxide HS becomes extremely easy.
このように本実施例によれば、被加工膜としてのシリコ
ン酸化膜４を下地表面の凹部に平坦な状態で確実に埋め
込むことができ、分離絶縁膜としてのシリコン酸化膜８
の表面を略完全に平坦化することができる。このため、
後続するレジストパターン形成時におけるレジスト露光
精度の低下等を未然に防止することができ、加工精度の
大幅な向上をはかり得る。また、前記レジスト６を残存
せしめるにあたり、下地パターンとの位置合わせ精度は
さほど必要でなく、さらに残存せしめるパターンは所望
領域を完全に平坦に埋めるものである必要もない。この
ため、１鴨の複雑化を招くこともなく極めて容易に実施
することができる。As described above, according to this embodiment, the silicon oxide film 4 as the film to be processed can be reliably buried in the recessed portion of the underlying surface in a flat state, and the silicon oxide film 8 as the isolation insulating film
The surface can be almost completely flattened. For this reason,
It is possible to prevent a decrease in resist exposure accuracy during subsequent resist pattern formation, and it is possible to significantly improve processing accuracy. Further, in making the resist 6 remain, alignment accuracy with the underlying pattern is not required so much, and furthermore, the pattern to be left does not need to fill the desired area completely flatly. Therefore, it can be implemented extremely easily without causing any complication.
なお、本発明は上述した実施例に限定されるものではな
い。例えば、前記全面エツチング処理時におけるシリコ
ン酸化膜４、レジスト６および有機物質膜１の各エッチ
。ング速度を必らずしも等しくする必要はなく、レジス
ト６のエツチング速度を他のエツチング速度よりも遅く
してもよい。このような条件下で第２図（ａ）に示すも
のを全面エツチングした場合、同図（ｂ）に示す如く有
機物質膜１の全部、シリコン酸化＄４の凸部の、みがエ
ツチング除去され、レジスト６の一部は残存することに
なる。そして、上記残ったレジスト６をＯ，プラズマ等
で除去すると下地表面が平滑化された状態となり、前記
実施例と同様の効果が得られることになる。Note that the present invention is not limited to the embodiments described above. For example, the silicon oxide film 4, the resist 6, and the organic material film 1 are etched during the entire surface etching process. The etching speeds do not necessarily have to be equal, and the etching speed of the resist 6 may be slower than the other etching speeds. When the entire surface of the material shown in FIG. 2(a) is etched under such conditions, the entire organic material film 1 and only the convex portion of the silicon oxide layer 4 are etched away, as shown in FIG. 2(b). , a portion of the resist 6 will remain. Then, when the remaining resist 6 is removed using O, plasma, etc., the underlying surface becomes smooth, and the same effect as in the embodiment described above can be obtained.
また、下地表面の高低差が１段でなくいくつかの高さの
異なる部分よりなる場合には、第３図に示す如く一部に
゛レジストｄの微細パターン形成を行い所望の高１を有
するレジストパターンを設けることもできる。仁の場合
、レジスト膜厚に比して小さなパターンにその領域を分
割し、露光される領域を現像後のレジストパターンが所
望高さとなるよう調整すればよい。そして、この後有機
物質膜１のスピンコートヲ行い前述した全面エツチング
処理を施すことによって、下地表面を平坦化できること
になる。In addition, if the height difference on the base surface is not one step but consists of several parts with different heights, as shown in Fig. A resist pattern can also be provided. In the case of thick resist, the area may be divided into patterns smaller than the resist film thickness, and the area to be exposed may be adjusted so that the resist pattern after development has a desired height. Thereafter, the organic material film 1 is spin-coated and the entire surface is etched as described above, thereby making it possible to planarize the underlying surface.
また、前記被加工膜としてはシリコン酸化膜に限らず、
絶縁膜、その他凹凸を有する膜であれば適用できる。さ
らに、前記レジストを残存せしめるための露光には、光
を用いる露光方法の他に、Ｘ線や電子線等の荷電粒子線
を用いる露光方法を利用してもよい。また、本発明は下
地表面を平坦化するのみに限らず、所望の高低差を有す
る形状に加工する工１にも適用することができる。要す
るに本発明は、その要旨を逸脱しない範囲で種々変形し
て実施することができる。Further, the film to be processed is not limited to a silicon oxide film,
Any insulating film or other film having irregularities can be applied. Further, for the exposure to leave the resist, an exposure method using a charged particle beam such as an X-ray or an electron beam may be used in addition to an exposure method using light. Furthermore, the present invention is not limited to flattening the base surface, but can also be applied to the process 1 in which the base surface is processed into a shape having a desired height difference. In short, the present invention can be implemented with various modifications without departing from the gist thereof.
第１図（ａ）〜（１）は本発明の一実施例を示す１楊断
面図、第２図（ａ） ＊ （ｂ）および第３図はそれぞ
れ変形例を説明するための断面図である。
１・・・、４Ｌ２・・・絶縁膜、３・・・ムｌ 合金膜
、４・・・シリコン酸化膜（被加工膜）５・・・能動領
域、６、・・レジスト、１・・・有機物質膜、Ｉ・・・
シリコン酸化膜（分離絶縁膜）。
出願人代理人 弁理土鈴 江 武 彦ＩＩＩ
Ｌ
第１ＩＩFigures 1 (a) to (1) are cross-sectional views showing one embodiment of the present invention, and Figures 2 (a) * (b) and 3 are cross-sectional views for explaining modified examples, respectively. be. 1..., 4L2... Insulating film, 3... Mul alloy film, 4... Silicon oxide film (film to be processed) 5... Active region, 6... Resist, 1... Organic material film, I...
Silicon oxide film (isolation insulating film). Applicant's agent Takehiko E Takehiko III
L 1st II
Claims (1)
ストを塗布する工程と、露光技術を−−７− 用い上記レジストを上記被加工膜の凹部の幅の広い部分
にのみ選択的に残存會しめる工程と、次いｔ上記レジス
ト上および被加工膜上に有機物質膜を回転塗布し該表面
を平坦化する工程と、しかるのちドライエツチング技術
を用い前記被加工膜と有機物質膜との各エツチング適度
が略等しく、かつ前記レジストのエラ予ング速Ｆｌが上
記被加工膜および有機物質膜のエツチング速度より違い
或いは略等しい条件下で前記有機物質膜の表面から全面
エツチング処理する工程とを真備したことを特徴とする
微細加工法。[Claims] A step of applying a resist onto a film to be processed provided on an uneven base surface, and applying the resist to a wide part of the recessed portion of the film to be processed using an exposure technique. a step of selectively allowing the organic material film to remain only on the resist and the film to be processed, a step of spin-coating an organic material film on the resist and the film to be processed and flattening the surfaces, and then dry etching the film to be processed using a dry etching technique. The etching rate of the resist film and the organic material film are approximately equal, and the etching speed Fl of the resist is different from or approximately equal to the etching speed of the film to be processed and the organic material film, and the entire surface is etched from the surface of the organic material film. A microfabrication method characterized by being equipped with an etching process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19223581A JPS5893327A (en) | 1981-11-30 | 1981-11-30 | Minute processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19223581A JPS5893327A (en) | 1981-11-30 | 1981-11-30 | Minute processing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5893327A true JPS5893327A (en) | 1983-06-03 |
Family
ID=16287894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19223581A Pending JPS5893327A (en) | 1981-11-30 | 1981-11-30 | Minute processing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893327A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59114823A (en) * | 1982-12-21 | 1984-07-03 | Agency Of Ind Science & Technol | Flattening method of semiconductor device |
| JPS60242623A (en) * | 1984-05-16 | 1985-12-02 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS61287245A (en) * | 1985-06-14 | 1986-12-17 | Hitachi Ltd | Multilayer interconnection method |
| JPS6437840A (en) * | 1987-07-21 | 1989-02-08 | Philips Nv | Manufacture of semiconductor device with planar structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5166778A (en) * | 1974-10-25 | 1976-06-09 | Hitachi Ltd | Handotaisochino seizohoho |
| JPS5339074A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Burying method of photoresist films |
| JPS5658247A (en) * | 1979-10-17 | 1981-05-21 | Fujitsu Ltd | Production of semiconductor device |
-
1981
- 1981-11-30 JP JP19223581A patent/JPS5893327A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5166778A (en) * | 1974-10-25 | 1976-06-09 | Hitachi Ltd | Handotaisochino seizohoho |
| JPS5339074A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Burying method of photoresist films |
| JPS5658247A (en) * | 1979-10-17 | 1981-05-21 | Fujitsu Ltd | Production of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59114823A (en) * | 1982-12-21 | 1984-07-03 | Agency Of Ind Science & Technol | Flattening method of semiconductor device |
| JPS60242623A (en) * | 1984-05-16 | 1985-12-02 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS61287245A (en) * | 1985-06-14 | 1986-12-17 | Hitachi Ltd | Multilayer interconnection method |
| JPS6437840A (en) * | 1987-07-21 | 1989-02-08 | Philips Nv | Manufacture of semiconductor device with planar structure |
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