JPS6015161B2 - bias circuit - Google Patents
bias circuitInfo
- Publication number
- JPS6015161B2 JPS6015161B2 JP51089416A JP8941676A JPS6015161B2 JP S6015161 B2 JPS6015161 B2 JP S6015161B2 JP 51089416 A JP51089416 A JP 51089416A JP 8941676 A JP8941676 A JP 8941676A JP S6015161 B2 JPS6015161 B2 JP S6015161B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- resistor
- terminal
- circuit
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/302—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明は、温度補償されたバイアス回路に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a temperature compensated bias circuit.
従来から温度補償されたバイアス回路としては、第１図
に示すような回路が知られている。As a conventional temperature-compensated bias circuit, a circuit as shown in FIG. 1 has been known.
図において、Ｒ，は一端を直流電圧源Ｖ＾に接続されか
つ他端を抵抗Ｒ２の一端に接続された抵抗で、前記抵抗
Ｒ２の他端はェミッタ接地されたトランジスタＴ，のコ
レクタ端子に接続されている。Ｔ２はベース端子を前記
抵抗Ｒ，とＲ２との接続点に接続されかつコレクタ端子
を前記直流電圧源Ｖ＾に接続されたトランジスタであり
、そのェミツタ端子は抵抗Ｒ３を介して接地されると共
に、基準バイアス電圧Ｖｏとして取り出される。次に動
作を説明する。In the figure, R is a resistor whose one end is connected to the DC voltage source V and the other end is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the collector terminal of the emitter-grounded transistor T. has been done. T2 is a transistor whose base terminal is connected to the connection point between the resistors R and R2, and whose collector terminal is connected to the DC voltage source V^, and whose emitter terminal is grounded via the resistor R3. It is extracted as a reference bias voltage Vo. Next, the operation will be explained.
トランジスタＴ２のェミッタ端子と抵抗沢３との接続点
より取り出される基準バイアス電圧Ｖｏは、トランジス
タＴ，，Ｔ２のベースェミツタ間電圧を同一のＶ８８と
するとＶ。＝くＶ＾−ＶＢ８）‐；章宅十ＶＢＥ−Ｖ８
８Ｒ２＝（Ｖ＾−ＶＢ８）・耳≠耳
で求まる。The reference bias voltage Vo taken out from the connection point between the emitter terminal of the transistor T2 and the resistor 3 is V, assuming that the base-emitter voltages of the transistors T and T2 are the same V88. =kuV^-VB8)-;AkiyajuVBE-V8
8R2=(V^-VB8)・Ear ≠ Ear.
上式におけるＶＢＥは温度変化により変動するためＶｏ
は安定せずバイアス回路としては好ましくない。すなわ
ち、Ｖ。を一定ならしめるため温度補償用として前記ト
ランジスタＴ２と同特性を有するトランジスタＴ，を抵
抗Ｒ２を介して前記トランジスタＴ２のベース端子に付
加する事により基準バイアス電圧Ｖｏの安定化を図らん
としたものであるが、ＶＢＢ成分は依然として残るため
、基準バイアスＶｏは温度変化に対しては依然として不
安定であるという欠点を有していた。本発明は、上記の
問題員点を解消すべく成されたものであり、以下、本発
明の一実施例を第２図に基づいて説明する。図において
、１は増幅回路で、トランジスタＴ３と、該トランジス
タＴ３のェミツタ端子に一端を接続されかつ他端を接地
された第１の抵抗Ｒ４と、前記トランジスタＬのコレク
タ端子に一端を接続これかつ他端を直流電圧源Ｖ＾に接
続された第２の抵抗Ｒ５とから構成されている。２は２
段のェミッタホロワ回路部であり、前記トランジスタＴ
３のコレクタ端子と抵抗Ｒ５との接続点ｂにベース端子
が接続されかつコレクタ端子が直流電圧源Ｖ＾に接続さ
れたトランジスタＬと、該トランジスタＴ４のェミッタ
端子に一端が接続されかつ池端が接地された抵抗Ｒ６と
、前記トランジスタＴ４のヱミッタ端子と抵抗Ｒ６との
接続点にベース端子が接続されかつコレクタ端子が直流
電圧源Ｖ＾に接続されたトランジスタＴ５と、該トラン
ジスタＴ５のェミッタ端子に一端が接続されかつ池端が
接地された抵抗Ｒ７とから構成されている。Since VBE in the above equation fluctuates due to temperature changes, Vo
is unstable and undesirable as a bias circuit. That is, V. In order to stabilize the reference bias voltage Vo, a transistor T having the same characteristics as the transistor T2 is added to the base terminal of the transistor T2 via a resistor R2 for temperature compensation, thereby stabilizing the reference bias voltage Vo. However, since the VBB component still remains, the reference bias Vo remains unstable with respect to temperature changes. The present invention has been made to solve the above-mentioned problems, and one embodiment of the present invention will be described below with reference to FIG. 2. In the figure, 1 is an amplifier circuit, which includes a transistor T3, a first resistor R4 whose one end is connected to the emitter terminal of the transistor T3 and whose other end is grounded, and whose one end is connected to the collector terminal of the transistor L. It is composed of a second resistor R5 whose other end is connected to a DC voltage source V^. 2 is 2
This is an emitter follower circuit section of the stage, and the transistor T
A transistor L whose base terminal is connected to the connection point b between the collector terminal of No. 3 and the resistor R5 and whose collector terminal is connected to the DC voltage source V^, and whose one end is connected to the emitter terminal of the transistor T4 and whose terminal is grounded. a transistor T5 whose base terminal is connected to the connection point between the emitter terminal of the transistor T4 and the resistor R6, and whose collector terminal is connected to the DC voltage source V^; and one end connected to the emitter terminal of the transistor T5. and a resistor R7, which is connected to the resistor R7 and whose terminal end is grounded.
前記トランジスタ公のェミツタ端子と抵抗戊？との接続
点ｃからの出力は基準バイアス電圧Ｖｏとして取り出さ
れると共に、前記増幅回路１のトランジスタＴ３のベー
ス端子に導かれている。なお前記トランジスタＴ３のェ
ミッタ端子と抵抗Ｒ４との接続点をａとする。次いで本
実施例の動作原理について説明する。The emitter terminal of the transistor and the resistor? The output from the connection point c is taken out as a reference bias voltage Vo, and is also led to the base terminal of the transistor T3 of the amplifier circuit 1. Note that the connection point between the emitter terminal of the transistor T3 and the resistor R4 is designated as a. Next, the operating principle of this embodiment will be explained.
接続点ａ〜ｃに得られれるバイアスは、接続点ａがＶａ
、接続点ｂがＶｂ、接続点ｃがＶｃである。トランジス
タＴ３のベース端子には基準バイアス電圧Ｖｏが印加さ
れるので、該トランジスタＴ３のェミツタ端子のバイア
スＶａはＶａ＝Ｖ。−ＶＢ８３ ……
■となり、トランジスタＴ３のェミッタ端子に流れる電
流ＩＥはｒＥ＝も土率 …■Ｒ４
となる。The bias obtained at connection points a to c is that connection point a is Va
, connection point b is Vb, and connection point c is Vc. Since the reference bias voltage Vo is applied to the base terminal of the transistor T3, the bias Va at the emitter terminal of the transistor T3 is Va=V. -VB83...
(2), and the current IE flowing to the emitter terminal of the transistor T3 is rE=R4.
ところで、直流増幅率が十分大きければ、該トランジス
タＴ３のェミツタ電流ＩＥとコレクタ電流ｌｃとはほぼ
等しいと考えられるので、トランジスタｔのコレクタ端
子のバイアス電圧ＶｂはＶｂ＝Ｖ＾−ｌｃ・Ｒ５
二Ｖ＾−ＩＥ・Ｒ５ ……■となる。By the way, if the DC amplification factor is sufficiently large, the emitter current IE and collector current lc of the transistor T3 are considered to be almost equal, so the bias voltage Vb at the collector terminal of the transistor t is Vb=V^-lc・R5 2V ^-IE・R5 ……■.
■式と■式よりＶｂ＝Ｖ＾−（Ｖ。From the formulas ■ and ■, Vb=V^-(V.
‐ＶＢＥ）・Ｒ５ ……■Ｒ４また、基準バイ
アスＶｏは、ェミッタホロワが２段であるのでＶ。-VBE)・R5 ……■R4 Also, the reference bias Vo is V because there are two stages of emitter followers.
＝Ｖｂ−２ＶＢ８ ……■■式■式
よりＶ。=Vb-2VB8...V from the ■■Formula■Formula.
ｉＶ＾−（Ｖ。−Ｖ８８）・蔓−２ＶＢＥ従って（．十
葦）Ｖ。iV^-(V.-V88)・vine-2VBE therefore (.ten reeds)V.
＝Ｖ＾＋串Ｖ８８−兆 ‐‐‐‐‐‐■となる。■劫か
て葦＝２とす側こよって、ＶＢ８の成分を完全に除去す
る事が可能である。= V^ + skewer V88-trillion -----■. (2) By setting the value of 2, it is possible to completely remove the VB8 component.
なお、本実施例においてェミッタホロワ回路が２段の場
合について説明したが、２段に限定されるわけではなく
、ェミッタホロヮ回路の接続段数と音の比（増幅率）と
を等しくとれ‘ま、常に温度補償されたバイアス回路を
得る事ができる。以上より明らかな如く、本発明によれ
ば、増幅回路に接続されたヱミッタホロワ回路の接続段
数と、前記増幅回路のトランジスタの第２の抵抗と第１
の抵抗との比の値とを等しくとる事によって、温度変化
に対して出力である基準バイアスが全く変動しないバイ
アス回路を得る事ができる。またェミッタホロワ回路の
接続段数を適当に設定することにより、それに応じた基
準バイアス値を選択できる。In this embodiment, the case where the emitter follower circuit has two stages has been explained, but it is not limited to two stages, and the number of connected stages of the emitter follower circuit and the sound ratio (amplification factor) can be made equal, and the temperature can always be maintained. A compensated bias circuit can be obtained. As is clear from the above, according to the present invention, the number of connected stages of the emitter follower circuit connected to the amplifier circuit, the second resistance of the transistor of the amplifier circuit, and the first
By setting the value of the ratio to the resistance of Furthermore, by appropriately setting the number of connected emitter follower circuits, a reference bias value can be selected accordingly.
第１図は従来のバイアス回路の一例を示す回路図、第２
図は本発明の一実施例におけるバイアス回路の回路図で
ある。
１……増幅回路、２……ェミッタホロワ回路部、Ｒ４・
・・・・・第１の抵抗、Ｒ５・・・第２の抵抗、Ｔ３・
・・・・・トランジスタ。
第１図
第２図Figure 1 is a circuit diagram showing an example of a conventional bias circuit, and Figure 2 is a circuit diagram showing an example of a conventional bias circuit.
The figure is a circuit diagram of a bias circuit in one embodiment of the present invention. 1...Amplification circuit, 2...Emitter follower circuit section, R4.
...First resistor, R5... Second resistor, T3.
...Transistor. Figure 1 Figure 2
Claims (1)
レクタ端子が第２の抵抗を介して直流電圧源に接続され
たトランジスタを有する増幅回路と、前記トランジスタ
のコレクタ端子に接続された１段以上のエミツタホロア
回路とを備え、最終段のエミツタホロア回路のエミツタ
端子を前記増幅回路中のトランジスタのベース端子に接
続しかつこの接続点から出力を取出すと共に、前記第２
の抵抗の抵抗値と第１の抵抗値との比を前記エミツタホ
ロア回路の接続段数に等しくしたバイアス回路。1 An amplifier circuit having a transistor whose emitter terminal is grounded through a first resistor and whose collector terminal is connected to a DC voltage source through a second resistor, and one or more stages connected to the collector terminal of the transistor. an emitter follower circuit, the emitter terminal of the final stage emitter follower circuit is connected to the base terminal of the transistor in the amplifier circuit, and an output is taken from this connection point, and the emitter follower circuit of the second
A bias circuit in which the ratio of the resistance value of the resistor and the first resistance value is equal to the number of connected stages of the emitter follower circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51089416A JPS6015161B2 (en) | 1976-07-26 | 1976-07-26 | bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51089416A JPS6015161B2 (en) | 1976-07-26 | 1976-07-26 | bias circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5314541A JPS5314541A (en) | 1978-02-09 |
| JPS6015161B2 true JPS6015161B2 (en) | 1985-04-18 |
Family
ID=13970038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51089416A Expired JPS6015161B2 (en) | 1976-07-26 | 1976-07-26 | bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6015161B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6184908A (en) * | 1984-10-02 | 1986-04-30 | Rohm Co Ltd | Bias circuit in high frequency circuit |
-
1976
- 1976-07-26 JP JP51089416A patent/JPS6015161B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5314541A (en) | 1978-02-09 |
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