JPS60149173A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS60149173A JPS60149173A JP480984A JP480984A JPS60149173A JP S60149173 A JPS60149173 A JP S60149173A JP 480984 A JP480984 A JP 480984A JP 480984 A JP480984 A JP 480984A JP S60149173 A JPS60149173 A JP S60149173A
- Authority
- JP
- Japan
- Prior art keywords
- film
- stress
- adhered
- layer
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 150000001875 compounds Chemical class 0.000 title claims abstract description 6
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 230000008018 melting Effects 0.000 claims description 11
- 238000002844 melting Methods 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 230000001747 exhibiting effect Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 20
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 6
- 238000000137 annealing Methods 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 230000006835 compression Effects 0.000 abstract 2
- 238000007906 compression Methods 0.000 abstract 2
- 238000007740 vapor deposition Methods 0.000 abstract 2
- 238000010894 electron beam technology Methods 0.000 abstract 1
- 238000004299 exfoliation Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 45
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- UKUVVAMSXXBMRX-UHFFFAOYSA-N 2,4,5-trithia-1,3-diarsabicyclo[1.1.1]pentane Chemical compound S1[As]2S[As]1S2 UKUVVAMSXXBMRX-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical group [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、ＱａＡｓなど化合物半導体ショットキ障壁ゲ
ート電界効果トランジスタ（以下ＭＢＳＦＥＴと略す）
とそのショットキ電極形成法に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a compound semiconductor Schottky barrier gate field effect transistor (hereinafter abbreviated as MBSFET) such as QaAs.
and its Schottky electrode formation method.
ゲート電極をマスクとしてｎ０層をイオン打込みによっ
て形成する自己整合型ＧａＡｓＭＥＳＦＥＴでは、ショ
ットキ電極に対して高耐熱性が要求される。第１図にそ
の製作工程の一例の概略を示す。In a self-aligned GaAs MESFET in which the n0 layer is formed by ion implantation using the gate electrode as a mask, the Schottky electrode is required to have high heat resistance. FIG. 1 shows an outline of an example of the manufacturing process.
（１１半絶縁性ＧａＡｓ基板１１にｎ層１”２としてＳ
ｉイオン打込み後、ゲート電極１３を形成する（第１図
（１１） 、 １２Ｒ（７）ゲート成極１３及Ｕ ＣＶ
Ｄ８ ｆＯｉ膜１膜管４スクとしてｎ＋層１６をＳｉイ
オン打込みによって形成する（第１図（２））。（３）
キャップ材１７として８１０＊ＣＶＤ膜又は５ｉ−Ｎプ
ラズマＣＶＤ膜を被着して表面保護膜となしＨ２雰囲気
中でアニールする（第１図（３））。（４）ソース・ド
レインｔ４ （ＡｕＧｅ／Ｎｉ／Ａｕ）１８ を形成り
、 てＧａＡｓＭＥ８Ｆ’ｇＴを完成する（第１図（４
））。(11 Semi-insulating GaAs substrate 11 with n layer 1”2)
After i ion implantation, gate electrode 13 is formed (Fig. 1 (11), 12R (7) gate polarization 13 and U CV
D8 An n+ layer 16 is formed by Si ion implantation using one fOi film and four film tubes (FIG. 1(2)). (3)
An 810*CVD film or a 5i-N plasma CVD film is deposited as a cap material 17 to serve as a surface protection film, and annealed in an H2 atmosphere (FIG. 1 (3)). (4) Form source/drain t4 (AuGe/Ni/Au) 18 to complete GaAsME8F'gT (Fig. 1 (4)
)).
今この製造工程で必要とされる要件は
（１）イオン打込み後のＨ２アニール（ｓｏｏｃ近傍）
によってＧａＡｓ基板からはく離することがないこと。The requirements required for this manufacturing process are (1) H2 annealing after ion implantation (near SOOC)
It must not peel off from the GaAs substrate due to
（２） ショットキ電極が熱処理によって電気的特性、
理想指数（ｎ値）、ショットキ障壁高さくφ農）等が劣
化しないこと。(2) The electrical properties of the Schottky electrode are improved by heat treatment.
The ideal index (n value), Schottky barrier height (φ), etc. should not deteriorate.
である。It is.
この熱処理による劣化を防ぐため、’ｒニーｗ（チタン
タングステン）シリサイド、Ｗ（タングステン）シリサ
イドの組成を最適化することによって膜内応力を減少さ
せる方法がある。（大西他″′超高速ｕａＡｓＶＬ８Ｉ
を指向したＷシリサイド・ゲートセルフアライメント技
術”電子通信学会研究資料ＥＤ８２−１０７）この方法
で制御する場合、安定した二元スパッタ蒸着装置が必要
であシ、その組成制御の再現性が重要な問題であった。In order to prevent deterioration due to this heat treatment, there is a method of reducing the stress in the film by optimizing the composition of titanium tungsten silicide and tungsten silicide. (Onishi et al.''Ultra high speed uaAsVL8I
"W silicide gate self-alignment technology aimed at Met.
本発明の目的は膜内応力の少ない高融点金属又は高融点
金属化合物をゲート電極に用いたＱａＡ８ＭＥＳＦＥ’
ｌ’の製作方法を提供することにある。The object of the present invention is to produce a QaA8MESFE' in which a high melting point metal or a high melting point metal compound with low internal stress is used for the gate electrode.
The object of the present invention is to provide a method for manufacturing l'.
〔発明の概要〕
一般に金属薄膜を基板上に被層すると、膜自身が内部応
力を持つ。この膜内応力は基板のそシを薄膜の被着前後
で測定して次式からめる。[Summary of the Invention] Generally, when a metal thin film is coated on a substrate, the film itself has internal stress. This internal stress in the film is calculated from the following equation by measuring the warp of the substrate before and after the thin film is applied.
ここで、σ；膜内応力 Ｅｓ；基板のヤング率 Ｄ；基板厚さ ｒ；基板の曲率半径 ｔ；薄膜の膜厚 シ；ポアッソン比 である。Here, σ; intramembrane stress Es; Young's modulus of the substrate D; Substrate thickness r; Radius of curvature of the substrate t: Thin film thickness C; Poisson's ratio It is.
膜内応力は被着方法、例えばスパッタ蒸着膜、ＥＢ蒸着
膜、クラスタイオンビーム蒸着膜の相違によって異なる
。一般にＥＢ蒸着膜は引張シ応力に、スパッタ膜は圧縮
応力が得られやすい。さらに被着条件、例えば基板温度
、被着時Ａｒ圧、被着速度、被着時Ａｒ圧等によって膜
内応力は変化する。Ｗのスパッタ膜については、ガラス
板上にスパッタ膜を被着し、膜内応力を検討した例とし
てはＲ，８，Ｗａｇｎｅｒ他の−ＴＬ１ｎｇｓｔ６Ｈｍ
ｅｔａｌｌｉｚａｔｉｏｎ ｆｏｒ ＬＳＩ ａｐｐｌ
ｉｃａｔｉｏｎｓ’Ｊ、ｖａｃ、Ｓｃｉ、Ｔｅｃｈｎｏ
ｌ、 １１．５８２ （１９７４）がある。それによれ
ばＡｔ圧、ＲＦノ（ワ、基板／（イアスを変えることに
よって膜内応力を圧縮から引張シまで変えることができ
る。しかし膜内応力は上記条件に対して、応力上口近傍
で急激に変イヒするため、その再現性の良い制御は困難
であった。The stress in the film differs depending on the deposition method, for example, sputter-deposited film, EB-deposited film, or cluster ion beam-deposited film. Generally, EB vapor deposited films tend to have tensile stress, and sputtered films tend to have compressive stress. Furthermore, the stress within the film changes depending on deposition conditions, such as substrate temperature, Ar pressure during deposition, deposition speed, Ar pressure during deposition, and the like. Regarding the sputtered film of W, an example in which the sputtered film was deposited on a glass plate and the stress in the film was investigated is as follows: -TL1ngst6Hm by R, 8, Wagner et al.
etallization for LSI appl
cations'J, vac, Sci, Techno
11.582 (1974). According to this, it is possible to change the stress in the film from compressive to tensile by changing the At pressure, RF pressure, substrate/earth. It has been difficult to control it with good reproducibility because the
そこで本方法はＧａＡｓＭＥｉＳＦＥ’ｌ’ のゲート
電極形成にあたって（）ａＡ８基板上に安定した条件で
圧縮又は引張りの膜内応力を示す第１の膜を被着し、次
に第１の膜と反対の応力を示す第２の膜を被層して、全
体として所望の膜厚を得るとともに、膜内応力を再現性
良く上口近傍に制御することである。さらに三層以上の
多層膜を用いることも原理的に可能である。Therefore, in forming the gate electrode of GaAsMEiSFE'l', the present method (1) deposits a first film exhibiting compressive or tensile internal stress on the aA8 substrate under stable conditions, and then deposits the first film exhibiting compressive or tensile internal stress on the aA8 substrate, and then deposits the first film exhibiting compressive or tensile internal stress on the aA8 substrate. The purpose is to coat the second film exhibiting stress to obtain a desired film thickness as a whole, and to control the stress within the film to be near the upper opening with good reproducibility. Furthermore, it is also possible in principle to use a multilayer film of three or more layers.
以下、本発明の実施例を図を用いて詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
［実施ｆｉｌｌ］
第２図はＧａＡｓＭＥＳＦＥＴの製造工程を示して＾る
。[Implementation Fill] Figure 2 shows the manufacturing process of GaAs MESFET.
（１） クロム＜ｃｒ）ドープしたＧａＡ３半絶縁性基
板２１にホトレジスト２２をＳｉＱ、２３ をマスク材
として、ｎ型不純物Ｓｉをドース量４Ｘ１０１２Ｃｒｌ
ｌ−” ％打込みエネルギ７５ＫｅＶの条件で打込みイ
オン打込み層２４を形成する（第２図（１））。(1) Chromium<cr) doped GaA3 semi-insulating substrate 21 is coated with photoresist 22 of SiQ, 23 is used as a mask material, and n-type impurity Si is applied at a dose of 4X1012Crl.
The ion implantation layer 24 is formed under conditions of implantation energy of 75 KeV (FIG. 2(1)).
（２） ホトレジスト２２ 、８ｉ０ｉ ２３ のマス
ク材を除去後、まずＷ２５をＥＢ蒸着装置で被着する（
第２図１２））。膜厚２００ｎｍを基板温度３００Ｃで
被着する。この時膜内応力はσ＝＝３ｘｌＯ’ｄｙｎｅ
／（−の引張シ志力であった。次にＷ２６ヲスパツク蒸
層装置で被層する。膜厚２００ ｎｍを基板温度２５０
Ｃでスパッタ中アルゴン圧２８ｗＴＯｒｒ被着する。こ
の時膜内応力はσ＝３Ｘ” ” ｄＹｎｅ／ｃｒｌ の
圧縮応力であった。全体厚さ４ Ｑ Ｑ ｎｍの二層Ｗ
２５．２６を低い膜内応力で被着することができる。一
般に高融点金属薄膜形成にＥＢ蒸着を前いれば、安定し
て引張り応力が得られ、スパッタ蒸着を用いれば圧縮応
力が得られやすい。この性質を利用すればＷ以外のＴａ
等の高融点金属も膜内応力の小さい安定した膜を得るこ
とができる。(2) After removing the photoresists 22 and 8i0i 23 mask materials, first deposit W25 using an EB evaporator (
Figure 2 12)). A film thickness of 200 nm is deposited at a substrate temperature of 300C. At this time, the stress in the film is σ==3xlO'dyne
The tensile force was /(-.Next, the film was coated with a W26 spacing evaporator.The film thickness was 200 nm and the substrate temperature was 250 nm.
The film was deposited using C at an argon pressure of 28 wTOrr during sputtering. At this time, the stress in the film was a compressive stress of σ=3X'' dYne/crl. Two layers W with total thickness 4 Q Q nm
25 and 26 can be deposited with low intra-film stress. Generally, if EB evaporation is used before forming a high melting point metal thin film, tensile stress can be stably obtained, and if sputter evaporation is used, compressive stress can easily be obtained. Using this property, Ta other than W
A stable film with low internal stress can also be obtained using high melting point metals such as.
（３１ＳｉＯ＊２７ を３００ｎｍ被着後通常ノホトリ
ソグラフィー技術を用いてゲート電極２８に加工する（
第２図（３））。(After depositing 31SiO*27 to a thickness of 300 nm, it is processed into the gate electrode 28 using normal photolithography technology (
Figure 2 (3)).
（４）Ｗ２５．２６及びＳ１０＊２７ をマスク材とし
て、Ｓｉをイオン打込みしてｎ９層２９を形成し、ゲー
ト電極２８とｎ＋層２９を自己整合型にする。この時所
望の領域以外はホトレジスト３０を用いてＢｉイオンが
打込まれないようにしておく（第２図（４））。(4) Using W25.26 and S10*27 as mask materials, Si is ion-implanted to form the n9 layer 29, making the gate electrode 28 and the n+ layer 29 self-aligned. At this time, a photoresist 30 is used to prevent Bi ions from being implanted in areas other than the desired areas (FIG. 2 (4)).
（５） ホトレジスト３０ 、５ｊ０２２７ を除去後
、Ｈ２雰囲気で８０（１，２・０分間アニールしｎノー
及びｎ７層の活性化を行なう。この時ＧａＡＳの熱分解
を防ぐため、あらかじめキャップ拐ａｘとｔ、ｃｓｉ−
ＮプラズマＣＶＤ膜、８１０２ＣＶＤ膜を被着しておく
（第２図（５））。(5) After removing the photoresists 30 and 5j0227, annealing is performed in an H2 atmosphere for 80 minutes (1, 2.0 minutes) to activate the n-no and n7 layers. At this time, in order to prevent thermal decomposition of GaAS, remove the cap and ax beforehand. t, csi-
An N plasma CVD film and an 8102CVD film are deposited (FIG. 2 (5)).
（６）最後に通常のリフトオフ技術を用いてソース・ド
レイン電極３２をＡｕＧｅ／Ｎ ｉ／Ａｕ 三層膜によ
シ形成する（第２図（６））。(6) Finally, source/drain electrodes 32 are formed using a three-layer film of AuGe/Ni/Au using a normal lift-off technique (FIG. 2 (6)).
なお、本発明によればシリサイドは抵抗がρ＝７１３０
μΩ１ と高く、ゲート抵抗が大きくなシ、高速変調が
不利となっていたが、Ｗではρ＝２０μΩ−ｍ程度で変
調に有利である。According to the present invention, the resistance of silicide is ρ=7130.
W has a high gate resistance of μΩ1, which is disadvantageous for high-speed modulation, but W has a value of about 20 μΩ−m, which is advantageous for modulation.
このようにして作製したＱａＡｓＦＥＴの特性は、ソー
ス・ドレイン間電圧Ｖ８Ｄ＝２ｖ％グートノ（イアス０
■の条件でソース・ドレイン間電流Ｉ ４ｇ＝３４±４
ｍＡが得られた。またゲート幅１μｍ当りＩｄｇ＝０．
５μＡの条件でピンチオフ電圧を測定したところ、Ｖ、
＝−１，８±０．１■ を得た。また相互コンダクタ７
スもｇｍ＝１００〜１２５ｍ５／＋ｍ という良好な結
果を得た。The characteristics of the QaAsFET manufactured in this way are as follows: source-drain voltage V8D=2v%
Source-drain current I 4g = 34±4 under the conditions of ■
mA was obtained. Also, Idg per 1 μm of gate width is 0.
When the pinch-off voltage was measured under the condition of 5 μA, V,
=-1.8±0.1■ was obtained. Also, mutual conductor 7
Good results were obtained with gm=100 to 125 m5/+m.
［実施例２］
実施例１はＥＢ蒸着膜とスパッタ蒸着膜の二層構造を用
いたが、スパッタ蒸着膜のみを用いても可能である。半
絶縁性ＧａＡＳ基板にスノ（ツタ中のアルゴン圧１４ｍ
Ｔ ｏ ｒ ｒの条件でタングステン（ＶＶ）シリサイ
ドを２００ ｎｍ被層する。膜内応力は圧縮応力でσ＝
２×ＩＯ’ｄ）’ｎｅ／ｉであった。次に第２層として
アルゴン圧２４ＩＩ１１１ＴＯｒｒの条件でＷシリサイ
ドを２００１１ｍ被着する。（’＝−２Ｘ １０’ ｄ
ｙｎｅ／ｃｙｄの引張シ応力であった。この膜全体とし
ては極めて応力が小さく、ゲート電極の耐熱性の向上が
みられ、８０（Ｉ’のＨａアニールによっても剥離は起
こらなかった。[Example 2] Although Example 1 used a two-layer structure of an EB vapor-deposited film and a sputter-deposited film, it is also possible to use only a sputter-deposited film. Snow on a semi-insulating GaAS substrate (argon pressure in ivy 14 m)
Tungsten (VV) silicide is coated to a thickness of 200 nm under conditions of T or r. The stress in the film is compressive stress and σ=
2×IO'd)'ne/i. Next, as a second layer, 20011 m of W silicide is deposited under an argon pressure of 24 II 111 Torr. ('=-2X 10' d
The tensile stress was yne/cyd. The stress of this film as a whole was extremely small, the heat resistance of the gate electrode was improved, and no peeling occurred even after Ha annealing at 80 (I').
この他スパッタ中に基板バイアスを印加することによっ
ても膜内応力の制御ができる。この方法との組合わせに
よっても膜内応力の低減は可能であった。In addition, the stress in the film can also be controlled by applying a substrate bias during sputtering. In combination with this method, it was also possible to reduce the stress within the film.
本発明によれば、ゲート電極となる高融点金属あるいは
尚融点金属セラミックス（たとえば高融点金属シリサイ
ド）の膜内応力を小さくすることが再現性良くできる。According to the present invention, it is possible to reduce the stress in the film of a high melting point metal or a high melting point metal ceramic (for example, a high melting point metal silicide) serving as a gate electrode with good reproducibility.
これによればＧａ Ａｓ等化合物半導体ＭＥＳＦＥＴ製
作の除行なうイオン打込み不純物の活性化、即ちＨ２雰
囲気中での高温アニールによって剥離することがなくな
る。This eliminates the possibility of peeling off due to the activation of ion-implanted impurities, that is, high-temperature annealing in an H2 atmosphere when manufacturing a compound semiconductor MESFET such as GaAs.
第１図は、ＧａＡｓＭＥＳＦＥ’ｌ” の製造工程を示
す装置の断面図、第２図は応力を小さくするために二層
膜構造としたゲート電極を用いたＧａ ＡｓＭＢＳＦＥ
Ｔの製造工程を示す装置の断面図である。
１１．２１・・・半絶縁性ＧａＡ３基板、１２，２４−
・・ｎｊ−１２５，２６・・・高融点金属又は高融点金
属セラミックス、１３．２８・・・ゲート電極、１７゜
３１・・・キャップ材、１８．３２・・・ソース・ドレ
イ第 １ 図
Ｙ２ 図
第１頁の続き
＠発明者 小橋 降格 国峙市刺
央研究所内
０発 明 者 高 橋 進 国分寺市刺央研究所内Figure 1 is a cross-sectional view of a device showing the manufacturing process of GaAsMESFE'1'', and Figure 2 is a GaAsMBSFE using a gate electrode with a double-layer structure to reduce stress.
It is a sectional view of the apparatus showing the manufacturing process of T. 11.21...Semi-insulating GaA3 substrate, 12,24-
...nj-125,26...Refractory metal or refractory metal ceramic, 13.28...Gate electrode, 17゜31...Cap material, 18.32...Source/dray No. 1 Figure Y2 Continuation of figure 1 page @ Inventor Kobashi demoted Kunichi City Shio Research Institute 0 Inventor Takahashi Susumu Kokubunji City Shio Research Institute
Claims (1)
融点金属、高融点金属シリサイドを第１層に、第１層と
逆向きの応力を示す高融点金属、高融点金属シリサイド
を第２層として重ね合わせたショットキ電極が化合物半
導体上に形成されており、少なくとも該ショットキ電極
をマスクとしてイオン打込み法により不純物を導入し、
その後熱処理によシｎ＋層を形成されたことを特徴とす
る化合物半導体装置の製造方法。1.711M High melting point metal and high melting point metal silicide exhibiting compressive stress or tensile stress are used as the first layer, and high melting point metal and high melting point metal silicide exhibiting stress in the opposite direction to the first layer are used as the second layer. Overlapping Schottky electrodes are formed on a compound semiconductor, and impurities are introduced by ion implantation using at least the Schottky electrodes as a mask,
A method for manufacturing a compound semiconductor device, characterized in that an n+ layer is formed by subsequent heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP480984A JPS60149173A (en) | 1984-01-17 | 1984-01-17 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP480984A JPS60149173A (en) | 1984-01-17 | 1984-01-17 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60149173A true JPS60149173A (en) | 1985-08-06 |
Family
ID=11594079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP480984A Pending JPS60149173A (en) | 1984-01-17 | 1984-01-17 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60149173A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6257255A (en) * | 1985-09-06 | 1987-03-12 | Agency Of Ind Science & Technol | Manufacture of compound semiconductor device |
| JPS6271281A (en) * | 1985-09-24 | 1987-04-01 | Nec Corp | Compound semiconductor device |
| JPS63179579A (en) * | 1987-01-20 | 1988-07-23 | Nec Corp | Manufacture of compound semiconductor device |
| JPH02228034A (en) * | 1989-02-28 | 1990-09-11 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| US5583074A (en) * | 1987-07-27 | 1996-12-10 | Texas Instruments Incorporated | Semiconductor circuit |
| GB2328793B (en) * | 1997-08-26 | 2000-06-07 | Lg Electronics Inc | Thin-film transistor and method of making same |
| USRE45579E1 (en) | 1997-03-04 | 2015-06-23 | Lg Display Co., Ltd. | Thin-film transistor and method of making same |
-
1984
- 1984-01-17 JP JP480984A patent/JPS60149173A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6257255A (en) * | 1985-09-06 | 1987-03-12 | Agency Of Ind Science & Technol | Manufacture of compound semiconductor device |
| JPS6271281A (en) * | 1985-09-24 | 1987-04-01 | Nec Corp | Compound semiconductor device |
| JPS63179579A (en) * | 1987-01-20 | 1988-07-23 | Nec Corp | Manufacture of compound semiconductor device |
| US5583074A (en) * | 1987-07-27 | 1996-12-10 | Texas Instruments Incorporated | Semiconductor circuit |
| JPH02228034A (en) * | 1989-02-28 | 1990-09-11 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| USRE45579E1 (en) | 1997-03-04 | 2015-06-23 | Lg Display Co., Ltd. | Thin-film transistor and method of making same |
| USRE45841E1 (en) | 1997-03-04 | 2016-01-12 | Lg Display Co., Ltd. | Thin-film transistor and method of making same |
| GB2328793B (en) * | 1997-08-26 | 2000-06-07 | Lg Electronics Inc | Thin-film transistor and method of making same |
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