JPS60149119A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60149119A JPS60149119A JP500184A JP500184A JPS60149119A JP S60149119 A JPS60149119 A JP S60149119A JP 500184 A JP500184 A JP 500184A JP 500184 A JP500184 A JP 500184A JP S60149119 A JPS60149119 A JP S60149119A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- holder
- thin film
- substrate holder
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、特に液晶等と組合せて画像表示装
置を構成するだめのシリコンを主成分とする非晶質シリ
コン半導体よりなる薄膜電界効果トランジスタ（以後Ｔ
ＦＴと呼ぶ）の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device, particularly a thin film field effect transistor ( From now on T
FT).
従来例の構成とその問題点
プラズマ化学気相堆積法により堆積される非晶質シリコ
ン（微結晶シリコンを含む）は、薄膜太陽電池、′″；
；インセンザー光電変換装置２画像表示装置として実用
化が期待されている。これらの装置は性質の異なる複数
の薄膜を積層したものであり、これらの績層膜を工業的
に大面積かつ大量に堆積する目的で、複数のプラズマ堆
積室を有するプラズマ化学気相堆積装置が開発されてい
る０ここで捷ずこのような装置として、２室のプラズマ
堆積室を有する装置を例にとって説明する。第１図に示
すように、基板１ａ、１ｂは基板保持部２に保持されて
第１の真空室３に下向きに配置され、基板１ａ、Ｉｂ主
面上に第１の薄膜が堆積される。その後、基板１は基惨
保持部２とともに搬送機構４ａ、４ｂにより開閉板５を
介して第２の真空室６へ真空状態の４：ま移動され、そ
こで第２の薄膜が堆積される。７ａ、７ｂはプラズマ電
極、８は基板保持台、９は裏板である。Structure of the conventional example and its problems Amorphous silicon (including microcrystalline silicon) deposited by plasma chemical vapor deposition method is used for thin film solar cells.
It is expected that the insensor photoelectric conversion device will be put to practical use as a two-image display device. These devices are made by laminating multiple thin films with different properties, and for the purpose of industrially depositing these laminated films over a large area and in large quantities, a plasma chemical vapor deposition device having multiple plasma deposition chambers is used. Here, as an example of such an apparatus that has been developed, an apparatus having two plasma deposition chambers will be explained. As shown in FIG. 1, the substrates 1a and 1b are held by a substrate holder 2 and placed in a first vacuum chamber 3 facing downward, and a first thin film is deposited on the main surfaces of the substrates 1a and Ib. Thereafter, the substrate 1 is moved together with the substrate holder 2 by the transport mechanisms 4a and 4b via the opening/closing plate 5 to a second vacuum chamber 6 in a vacuum state, where a second thin film is deposited. 7a and 7b are plasma electrodes, 8 is a substrate holding stand, and 9 is a back plate.
通常、薄膜が堆積される時には基板保持台２はプラズマ
電極７ａ 、７ｂに対向する電極を兼ね基板保持台２自
体がアース電位に固定されるようになっている。Normally, when a thin film is deposited, the substrate holder 2 also serves as an electrode facing the plasma electrodes 7a and 7b, and the substrate holder 2 itself is fixed at a ground potential.
次に、従来使用されている基板保持台２の基板が保持さ
れる部分の断面図を第２図に示す。保持台８には、基板
１の主面の面積に比べやや小さい開孔部８ａが金属基板
保持台８の一方面」りに形成され、かつ保持台８の他方
の面側には基板１の主面面積よりやや大きい穴８ｂが作
り込丑れている。Next, FIG. 2 shows a cross-sectional view of a portion of a conventionally used substrate holder 2 where a substrate is held. The metal substrate holder 8 has an aperture 8a that is slightly smaller in area than the main surface of the substrate 1 on one side of the metal substrate holder 8, and a hole 8a for the substrate 1 on the other side of the metal substrate holder 8. A hole 8b slightly larger than the main surface area is formed.
こうして大きい穴８ｂの側から基板１を落し込み、その
後基板の裏側に金属性裏板９を落し込み基板１の端部１
ａを台８と板９で保持する構造がとられていた。この構
造ではプラズマ放電中における基板保持台８と裏板９と
の電気的接触は単なる機械的接触のみに依存しており、
保持台８をアースしても裏板９すなわち基板１を充分ア
ース電位とすることができない。In this way, the board 1 is dropped from the side of the large hole 8b, and then the metal back plate 9 is dropped into the back side of the board, and the end 1 of the board 1 is
A was held by a stand 8 and a plate 9. In this structure, the electrical contact between the substrate holding table 8 and the back plate 9 during plasma discharge depends only on mechanical contact.
Even if the holding base 8 is grounded, the back plate 9, that is, the substrate 1, cannot be brought to a sufficient ground potential.
前記第１，２図の従来の基板保持部２を用いて、プラズ
マ化学気相堆積法によりリンを高濃度ドープした金属的
シリコン基板１上に、原料ガスとしてシラン、アンモニ
ア、希釈ガスとしてアルゴン。Using the conventional substrate holder 2 shown in FIGS. 1 and 2, silane and ammonia are used as source gases and argon is used as a diluent gas on a metallic silicon substrate 1 doped with phosphorus at a high concentration by plasma chemical vapor deposition.
窒素、水素等を使用して第１の薄膜なる窒化シリコン、
第２の薄膜なるアモルファスシリコンをそれぞれ４００
０人堆積し、選択的にエツチングすることによりチャン
ネル長１０μｍ 、チャンネル幅１祁の薄膜電界効果ト
ランジスタ（ＴＰＴ）を多数形成した。そのＴＰＴのド
レイン電流−ゲート電圧特性のひとつは第３図曲線Ｕに
示されるものであり、第３図■に示すごとく、そのＴＰ
Ｔのスイッチ−オン状態（本説明ではゲート電圧値が１
６Ｖの時）とオフ状態（本説明ではゲート電圧値が一、
ｏＶの時）のドレイン電流の比（ＯＮ−ＯＦＦ比）は６
桁（１ｏ５）以上であった。A first thin film of silicon nitride using nitrogen, hydrogen, etc.
The second thin film, amorphous silicon, is made of 400
A large number of thin film field effect transistors (TPTs) with a channel length of 10 μm and a channel width of 1 μm were formed by depositing and selectively etching. One of the drain current-gate voltage characteristics of the TPT is shown in the curve U in Figure 3, and as shown in Figure 3 ■, the TPT
T switch-on state (in this explanation, the gate voltage value is 1)
6V) and off state (in this explanation, when the gate voltage value is 1,
oV), the drain current ratio (ON-OFF ratio) is 6
It was more than digit (1o5).
一方、低価格基板の要求やＴＰＴを液晶ディスプレー等
のスイッチングマトリックスアレーへ応用する場合には
、シリコン基板ではなく透明絶縁性基板を用いる必要が
あることから、ガラス等絶縁性基板上へのＴＰＴの形成
は重要である。On the other hand, in response to the demand for low-cost substrates and when applying TPT to switching matrix arrays such as liquid crystal displays, it is necessary to use a transparent insulating substrate instead of a silicon substrate. Formation is important.
しかしながら、同様のプラズマ化学気相堆積装置により
前記従来の基板保持部２を用いてゲート金属が選択的に
被着形成されたガラス基板１上に、前述の場合と同様に
窒化シリコンとアモルファス例を第３図曲線ｌに示す。However, as in the case described above, silicon nitride and amorphous metal are deposited on a glass substrate 1 on which a gate metal is selectively deposited using the conventional substrate holder 2 using a similar plasma chemical vapor deposition apparatus. It is shown in curve 1 in Figure 3.
図に示すごとく、そのＴＰＴの０Ｎ−ＯＦＦ比は２桁（
１０２）と非常に小さく実用に耐えなかった０
尿発明者らはかかる問題を検討したところ、基板１の裏
板９が充分アース電位に保持されていないためであろう
と想定し、本発明はこの問題の解決することにより、良
好な薄膜トランジスタを作成可能とするものである０
発明の目的
すなわち、本発明は前述の問題点に鑑みなされたもので
、ガラス等の絶縁性基板上にＴＰＴ等の↓導体装置を形
成した場合にも所望の特性が得られる半導体装置の製造
方法を提供することを目的とする。As shown in the figure, the 0N-OFF ratio of the TPT is two digits (
102), which was too small to withstand practical use.The inventors investigated this problem and assumed that it was because the back plate 9 of the substrate 1 was not sufficiently maintained at the ground potential.The present invention solves this problem. By solving the problem, it is possible to create a good thin film transistor.0 Purpose of the Invention That is, the present invention was made in view of the above-mentioned problem, and it is possible to fabricate a thin film transistor of good quality on an insulating substrate such as glass. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can obtain desired characteristics even when a conductor device is formed.
発明の構成
本発明は、絶縁性基板への薄膜形成に用いるプラズマ化
学気相堆積装置に使用する基板保持台が、基板の密着保
持される領域の面積が基板よりも大きく、かつその領域
がアース電位に直接接続されている状態で薄膜を形成し
て半導体装置、特にＴＰＴを製造する方法を提供するも
のである。Structure of the Invention The present invention provides a substrate holder used in a plasma chemical vapor deposition apparatus used for forming a thin film on an insulating substrate, in which the area where the substrate is closely held is larger than the area of the substrate, and the area is grounded. The present invention provides a method for manufacturing semiconductor devices, particularly TPTs, by forming a thin film while directly connected to an electric potential.
実施例の説明 以下、図面を用いて本発明の詳細な説明する。Description of examples Hereinafter, the present invention will be explained in detail using the drawings.
本発明の一実施例に用いる基板保持部を第４図に示す。FIG. 4 shows a substrate holding section used in one embodiment of the present invention.
アルミニウム製等の導電性基板保持台１゜にはガラス等
の絶縁性基板１よりもやや大きくかつ深さｄｌの凹部が
形成され、基板１はこの凹部に押え部旧１１およびネジ
１２により基板保持台１ｏに密着収納される。なお、こ
の場合基板の厚みｄ２と凹部の深さｄｌ を機械精度程
度に一致させることにより、基板１の裏面が十分基板保
持台１ｏに密着され、且つ基板１の製膜面（表面）が基
板保持台１０のプラズマにさらされる主面１０ａと面い
ちになる２ことが好ましい。A conductive substrate holding stand 1° made of aluminum or the like is formed with a recess slightly larger than the insulating substrate 1 made of glass or the like and having a depth dl, and the substrate 1 is held in this recess by a holding part 11 and screws 12. It is stored closely on the stand 1o. In this case, by matching the thickness d2 of the substrate and the depth dl of the recess to a mechanical precision level, the back surface of the substrate 1 can be brought into close contact with the substrate holding table 1o, and the film forming surface (front surface) of the substrate 1 can be kept in close contact with the substrate holder 1o. It is preferable that the main surface 10a of the holding table 10 is flush with the main surface 10a exposed to plasma.
上述の基板保持台１０及び第１図の装置を使用してプラ
ズマ化学気相堆積法により、ゲート金属（図示せず）が
選択形成された下向きのガラス基板１表面上に原料ガス
としてシラン、アンモニア。Using the above-mentioned substrate holding table 10 and the apparatus shown in FIG. 1, silane and ammonia are deposited as raw material gases onto the surface of the downward glass substrate 1 on which gate metal (not shown) is selectively formed by plasma chemical vapor deposition. .
希釈ガスとしてアルゴン、窒素、水素等を使用し、窒化
シリコン、アモルファスシリコンをそれツレ４０００人
堆積して、チャンネル長１０μｍ、チャンネル幅１０ｍ
ｍのＴＰＴを形成したところ、そのＴＰＴのドレイン電
流−ゲート電圧特性は第３図曲線ｌに示すものと同じで
あった。すなわち、５桁（１０６）以上の非常にすぐれ
た０Ｎ−ＯＦＦ比を示すＴＰＴをガラス基板１上に形成
できた。Using argon, nitrogen, hydrogen, etc. as a diluent gas, silicon nitride and amorphous silicon were deposited 4,000 times each to form a channel with a channel length of 10 μm and a channel width of 10 m.
When a TPT of m was formed, the drain current-gate voltage characteristic of the TPT was the same as that shown in curve 1 of FIG. 3. That is, a TPT exhibiting an extremely excellent ON-OFF ratio of 5 digits (106) or more could be formed on the glass substrate 1.
本発明の他の実施例を第５図に示す。基板１の大きさし
よりも小さい内径１１の開孔部１３を一方面側に有し、
かつ他方の面側から基板１の大きさＬより大きい内径１
２の開孔部１４を有するアルミニウム製基板支持部材１
５の端部１５ａに、ガラス基板１をＴＰＴが形成される
表面を下に向けて載置した後、前述の開孔部１４の内径
１２２より小さい外径１３の凸部１６を有する基板保持
台１７に密着保持される。そして、保持台１７と支持部
材１６は互いに密着される。Another embodiment of the invention is shown in FIG. It has an opening 13 on one side with an inner diameter 11 smaller than the size of the substrate 1,
and an inner diameter 1 larger than the size L of the substrate 1 from the other surface side.
Aluminum substrate support member 1 having two openings 14
After placing the glass substrate 1 on the end 15a of the glass substrate 1 with the surface on which TPT is formed facing downward, a substrate holder having a convex portion 16 having an outer diameter 13 smaller than the inner diameter 122 of the aperture 14 described above is placed. 17. Then, the holding base 17 and the support member 16 are brought into close contact with each other.
上述のような基板保持台１７と支持部材１６を使用して
、ゲート金属が選択的に被着形成されたガラス基板、１
上に、窒化シリコン、アモルファスシリコンよりなるチ
ャンネル長１０μｍ、チャンネル幅１０ｍのＴＰＴを形
成した場合にも、そのＴＰＴのドレイ／電流−ゲート電
圧特性は第３図曲線１１のようになり、第５図のような
構造の基板保持機構もガラス基板上にＴＰＴを形成する
うえで有効であった。なお、第６図のような構造は、基
板１を基板保持台に保持する際に常に基板１を下向きの
ま１にして保持できることから、作業が容易であり、基
板１上にダストが付着しにくいなどの利点を有する。A glass substrate 1 on which gate metal is selectively deposited using the substrate holder 17 and support member 16 as described above.
Even when a TPT made of silicon nitride or amorphous silicon with a channel length of 10 μm and a channel width of 10 m is formed on the top, the drain/current-gate voltage characteristics of the TPT are as shown in curve 11 in Figure 3, and as shown in Figure 5. A substrate holding mechanism with a structure like this was also effective in forming TPT on a glass substrate. Note that the structure shown in FIG. 6 is easy to work with because the substrate 1 can always be held facing downward when it is held on the substrate holder, and dust does not adhere to the substrate 1. It has advantages such as being difficult to use.
以上本発明では実施例として、窒化シリコン。In the above embodiments of the present invention, silicon nitride is used.
アモルファスシリコンよりなるＴＰＴの製造法を中心に
述べたが、窒化シリコンのような絶縁体とアモルファス
シリコンのような半導体との界面を有する他の半導体装
置の製造法にも本発明は有効である。このことは以下に
述べるようなことから裏付けられる。例えばガラス基板
上に、金属−窒化シリコン−アモルファスシリコン−金
属の構造を有する装置を従来の基板保持部と本発明の基
板保持機構を使用してそれぞれ形成して、その容量−電
圧特性を測定した場合、第６図に示されるものであった
。第６図の曲線１が従来の基板保持部を用いた場合、曲
線Ｕが本発明の基板保持機構を使用した場合である。こ
の図から明らかなように、本発明の基板保持機構を使用
した方が、その窒化シリコン−アモルファスシリコン界
面に欠陥準位等が少なく安定である。Although the method for manufacturing a TPT made of amorphous silicon has been mainly described, the present invention is also effective for manufacturing methods for other semiconductor devices having an interface between an insulator such as silicon nitride and a semiconductor such as amorphous silicon. This is supported by the following. For example, a device having a metal-silicon nitride-amorphous silicon-metal structure was formed on a glass substrate using a conventional substrate holder and the substrate holding mechanism of the present invention, and the capacitance-voltage characteristics were measured. The case was as shown in FIG. Curve 1 in FIG. 6 is the case when the conventional substrate holder is used, and curve U is the case when the substrate holding mechanism of the present invention is used. As is clear from this figure, the use of the substrate holding mechanism of the present invention is more stable with fewer defect levels and the like at the silicon nitride-amorphous silicon interface.
以上、本発明がプラズマ化学気相法により本導体装置を
製造するうえで有効であることを述べてきたが、その原
因としては次のように考えられる。It has been described above that the present invention is effective in manufacturing the present conductor device by the plasma chemical vapor phase method, and the reasons for this are thought to be as follows.
すなわち、従来の基板保持部では、リンを高濃度ドープ
したシリコンのような導電性基板の代わりに、ガラス等
絶縁性基板を使用することにより、基板裏面側に位置す
る裏板９は保持台８と充分に電気的な接続がなされてい
ない状態となり、基板１の周辺のプラズマ電界が乱れ、
シラン等の原料ガスの分解に影響を与え、堆積膜質を変
化させる。That is, in the conventional substrate holder, an insulating substrate such as glass is used instead of a conductive substrate such as silicon doped with high concentration of phosphorus, so that the back plate 9 located on the back side of the substrate is replaced by the holder 8. There is no sufficient electrical connection with the substrate 1, and the plasma electric field around the substrate 1 is disturbed.
Affects the decomposition of raw material gases such as silane and changes the quality of the deposited film.
しかしながら本発明のように基板裏面にアース電位に直
接接続された導電性保持台が存在することにより、その
プラズマ電界の乱れを防止することができ、基板１表面
全域にわたって均一な膜質の半導体膜を作成できる。こ
のことが、プラズマ堆積法を用いて絶縁性基板上に良好
な多層薄膜を形成できる理由であると推察される。However, as in the present invention, the existence of a conductive holder directly connected to the ground potential on the back surface of the substrate makes it possible to prevent disturbances in the plasma electric field and to form a semiconductor film with uniform film quality over the entire surface of the substrate 1. Can be created. This is presumed to be the reason why a good multilayer thin film can be formed on an insulating substrate using the plasma deposition method.
発明の効果
以上述べたように、本発明は数基の真空室をもつ装置を
使用してガラス等の絶縁基板上にプラズマ化学気相堆積
法により半導体装置特に窒化シリコン、アモルファスシ
リコンヨｆ）なるＴＦＴを製造する際に、基板が基板の
面積よりも大きく直接アー・スミ位に接続された基板保
持台に保持されることにより、極めてすぐれたＯＮ特性
、ＯＦＦ 特性を有するＴＰＴを再現性よく製造できる
すぐれた効果を発揮するものである。Effects of the Invention As described above, the present invention provides semiconductor devices, particularly silicon nitride, amorphous silicon, etc., by plasma chemical vapor deposition on an insulating substrate such as glass using an apparatus having several vacuum chambers. When manufacturing TFTs, the substrate is held on a substrate holder that is larger than the area of the substrate and is directly connected to the ground, making it possible to manufacture TPTs with excellent ON and OFF characteristics with good reproducibility. It shows excellent effects.
第１図は半導体装置の製造装置の概略断面図、第２図は
従来の基板保持台の構造断面図、第３図は従来の基板保
持台及び本発明の基板保持台を使用してガラス基板上に
麺着形成されたＴＰＴの電流−電圧特性を示す図、第吉
図は本発明の一実施例の基板保持台の構造断面図、第６
図は従来及び本発明の基板保持台を使用してガラス基板
上に形成した金属−窒化シリコン−アモルファスシリコ
ン−金属構造を有する装置の容量−電圧特性を示す図で
ある。
１・・・・・・基板、１０．１７・・・−・・基板保持
台、３゜６・・・・・・堆積室、４ａ、４ｂ・・・・・
・搬送機構、５・・印・開閉板、７ａ、７ｂ・・・・・
・プラズマ電極、１１・・・・・・押え部拐、１２・・
・・・ネジ、１３．１４・・・・・・開孔部、１５・・
・・・・支持部材、１６・旧・・凸部。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名菓
１ 図
第 ３ 図
ゲート電圧
第 ４ 図
ＯFIG. 1 is a schematic sectional view of a semiconductor device manufacturing apparatus, FIG. 2 is a structural sectional view of a conventional substrate holder, and FIG. A diagram showing the current-voltage characteristics of the TPT with a noodle formed thereon.
The figure shows the capacitance-voltage characteristics of devices having a metal-silicon nitride-amorphous silicon-metal structure formed on a glass substrate using the conventional and present substrate holders. 1...Substrate, 10.17...Substrate holding stand, 3゜6...Deposition chamber, 4a, 4b...
・Transportation mechanism, 5... mark ・Opening/closing plate, 7a, 7b...
・Plasma electrode, 11... Presser foot removal, 12...
...Screw, 13.14...Opening part, 15...
...Supporting member, 16. Old...Convex part. Name of agent: Patent attorney Toshio Nakao and one other name
1 Figure 3 Gate voltage Figure 4 O
Claims (4)
有する導電性基板保持台に保持機構を介して密着保持し
、第１の真空室内にて前記基板の表面を下向きにして前
記基板表面を放電電極と対向配置し、前記基板保持台自
体を直接アース電位に接続した状態でプラズマ化学気相
堆積法を用いて前記基板表面上に第１の薄膜を形成し、
前記基板の保持された基板保持台を前記第１の真空室と
連通した第２の真空室に移動させ、この第２の真空室内
にて前記第１の薄膜上に、前記基板保持台自体を直接ア
ース電位に接続した状態でプラズマ化学気相堆積法を用
いて第２の薄膜を形成することを特徴とする半導体装置
の製造方法。(1) The back side of an insulating substrate is held in close contact with a conductive substrate holder having a larger area than the substrate via a holding mechanism, and the front surface of the substrate is turned downward in a first vacuum chamber. is arranged to face a discharge electrode, and a first thin film is formed on the surface of the substrate using a plasma chemical vapor deposition method with the substrate holder itself directly connected to ground potential;
The substrate holder holding the substrate is moved to a second vacuum chamber communicating with the first vacuum chamber, and the substrate holder itself is placed on the first thin film in the second vacuum chamber. 1. A method of manufacturing a semiconductor device, comprising forming a second thin film using a plasma chemical vapor deposition method while directly connected to a ground potential.
表面の端部を押圧することを特徴とする特許請求の範囲
第１項に記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, characterized in that the end portion of the surface of the insulating substrate is pressed by a metal body attached to the substrate holder.
、前記絶縁性基板の表面の端部を押え部材に設置するこ
とにより、前記基板保持台と絶縁性基板とを密着保持さ
せることを特徴とする特許請求の範囲第１項に記載の半
導体装置の製造方法。(3) The substrate holder and the insulating substrate are held in close contact by bringing the back side of the insulating substrate into contact with the convex portion of the substrate holder and placing the end of the front surface of the insulating substrate on a holding member. A method for manufacturing a semiconductor device according to claim 1, characterized in that:
ある特許請求の範囲第１項に記載の半導体装置の製造方
法。(4) The method for manufacturing a semiconductor device according to claim 1, wherein the first or second thin film is a non-single crystal silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP500184A JPS60149119A (en) | 1984-01-13 | 1984-01-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP500184A JPS60149119A (en) | 1984-01-13 | 1984-01-13 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60149119A true JPS60149119A (en) | 1985-08-06 |
| JPH0544180B2 JPH0544180B2 (en) | 1993-07-05 |
Family
ID=11599335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP500184A Granted JPS60149119A (en) | 1984-01-13 | 1984-01-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60149119A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02105527A (en) * | 1988-10-14 | 1990-04-18 | Kawasaki Steel Corp | Plasma cvd device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5628637A (en) * | 1979-08-16 | 1981-03-20 | Shunpei Yamazaki | Film making method |
| JPS56122122A (en) * | 1980-03-03 | 1981-09-25 | Fuji Photo Film Co Ltd | Manufacture of amorphous semiconductor |
| JPS5870524A (en) * | 1981-09-28 | 1983-04-27 | エナ−ジ−・コンバ−シヨン・デバイセス・インコ−ポレ−テツド | Method of depositing body material on base and system therefor |
-
1984
- 1984-01-13 JP JP500184A patent/JPS60149119A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5628637A (en) * | 1979-08-16 | 1981-03-20 | Shunpei Yamazaki | Film making method |
| JPS56122122A (en) * | 1980-03-03 | 1981-09-25 | Fuji Photo Film Co Ltd | Manufacture of amorphous semiconductor |
| JPS5870524A (en) * | 1981-09-28 | 1983-04-27 | エナ−ジ−・コンバ−シヨン・デバイセス・インコ−ポレ−テツド | Method of depositing body material on base and system therefor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02105527A (en) * | 1988-10-14 | 1990-04-18 | Kawasaki Steel Corp | Plasma cvd device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0544180B2 (en) | 1993-07-05 |
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