JPS6014693U - Inverter control circuit - Google Patents
Inverter control circuitInfo
- Publication number
- JPS6014693U JPS6014693U JP10478183U JP10478183U JPS6014693U JP S6014693 U JPS6014693 U JP S6014693U JP 10478183 U JP10478183 U JP 10478183U JP 10478183 U JP10478183 U JP 10478183U JP S6014693 U JPS6014693 U JP S6014693U
- Authority
- JP
- Japan
- Prior art keywords
- degrees
- data selector
- read
- control signal
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来及び本考案を説明するための一般的なイン
バータ主回路の結線図、第２図は従来のインバータ制御
回路の結線図、第３図は正弦波のデジタル化方法を説明
するための図、第４図は従来の正弦波の単位波形化方法
を説明するための図、第５図以降は本考案の一実施例に
関するものであり、第５図は制御回路の結線図、第６図
は第１のデータセレクタの具体的回路を示す図、第７図
はＲＯＭのデータ割付はマツプを示す図、第８図は単位
波形による正弦波化方法を説明するための図である。
図中１はインバータ主回路、２３はＲＯＭ（記憶素子）
、２６はレートマルチプライヤ、２７はアップダウンカ
ウンタ、３０は第１のデータセレクタ、−３７は６進カ
ウンタ、３８〜４０は第２のデータセレクタ、４２乃至
４４はエクスクルシブオアゲート、４５〜４７はデータ
ラッチ、Ａはデータセレクタ制御回路である。Fig. 1 is a wiring diagram of a general inverter main circuit for explaining the conventional and present invention, Fig. 2 is a wiring diagram of a conventional inverter control circuit, and Fig. 3 is for explaining a sine wave digitization method. Fig. 4 is a diagram for explaining the conventional method of converting a sine wave into a unit waveform, Fig. 5 and subsequent figures relate to an embodiment of the present invention, Fig. 5 is a wiring diagram of the control circuit, FIG. 6 is a diagram showing a specific circuit of the first data selector, FIG. 7 is a diagram showing a map of data allocation in the ROM, and FIG. 8 is a diagram for explaining a method of converting a unit waveform into a sine wave. In the figure, 1 is the inverter main circuit, 23 is the ROM (memory element)
, 26 is a rate multiplier, 27 is an up/down counter, 30 is a first data selector, -37 is a hexadecimal counter, 38 to 40 are second data selectors, 42 to 44 are exclusive or gates, 45 to 47 is a data latch, and A is a data selector control circuit.
Claims (1)
信号によりオン、オフさせて正弦波近似交流出力を得る
インバータにおいて、前記制御信号を電気角にして１５
°ごとに９０’分記憶する記憶素子及びその記憶内容の
読み出しを制御する読出し制御部を設け、この読出し制
御部を、前記記憶素子の１５°ごとの記憶内容を順方向
及び逆方向に交互に読み出すアップダウンカウンタとそ
のアップ及びダウン区間を示す信号により上記記憶内容
を選択し３０°ごとに分割された１８０°分の信号に変
換する第１のデータセレクタとこの第１のデータセレク
タからの出力を選択して３６０°分のパターン制御信号
に変換する第２のデータセレクタを含むデータセレクタ
制御回路とから構成したこととを特徴とするインバータ
制御回路。In an inverter that obtains a sinusoidal approximation AC output by turning on and off switching elements in the inverter main circuit using a pattern control signal, the control signal is converted into an electrical angle of 15
A memory element that stores 90' minutes every 15 degrees and a read control section that controls reading of the memory contents thereof are provided, and the read control section is configured to alternately read the memory contents of the memory element every 15 degrees in the forward and reverse directions. A first data selector that selects the above-mentioned stored content based on an up/down counter to be read and signals indicating its up and down sections and converts it into a signal for 180 degrees divided into 30 degrees, and an output from this first data selector. and a data selector control circuit including a second data selector that selects and converts the selected data into a 360° pattern control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10478183U JPS6014693U (en) | 1983-07-05 | 1983-07-05 | Inverter control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10478183U JPS6014693U (en) | 1983-07-05 | 1983-07-05 | Inverter control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6014693U true JPS6014693U (en) | 1985-01-31 |
Family
ID=30245883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10478183U Pending JPS6014693U (en) | 1983-07-05 | 1983-07-05 | Inverter control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6014693U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS573582A (en) * | 1980-06-05 | 1982-01-09 | Toshiba Corp | Controller for inverter |
| JPS5746677A (en) * | 1980-09-01 | 1982-03-17 | Toshiba Corp | Invertor controlling circuit |
-
1983
- 1983-07-05 JP JP10478183U patent/JPS6014693U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS573582A (en) * | 1980-06-05 | 1982-01-09 | Toshiba Corp | Controller for inverter |
| JPS5746677A (en) * | 1980-09-01 | 1982-03-17 | Toshiba Corp | Invertor controlling circuit |
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