JPS6025281U - mixing circuit - Google Patents
mixing circuitInfo
- Publication number
- JPS6025281U JPS6025281U JP11534783U JP11534783U JPS6025281U JP S6025281 U JPS6025281 U JP S6025281U JP 11534783 U JP11534783 U JP 11534783U JP 11534783 U JP11534783 U JP 11534783U JP S6025281 U JPS6025281 U JP S6025281U
- Authority
- JP
- Japan
- Prior art keywords
- selection
- circuit
- selects
- output
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Studio Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のナムミックスミキシング回路を示すブロ
ック図、第2図はナムミックスミキシング回路に用いら
れるフェーダコントロール信号ヲ示す信号波形図、第3
図は本考案によるミキシング回路の一実施例を示すブロ
ック図である。
11、 12. 13. 16・・・選択回路、14・
・・乗算回路、15・・・選択出力回路、17・・・比
較回路。Figure 1 is a block diagram showing a conventional Namix mixing circuit, Figure 2 is a signal waveform diagram showing a fader control signal used in the Namix mixing circuit, and Figure 3 is a block diagram showing a conventional Namix mixing circuit.
The figure is a block diagram showing an embodiment of a mixing circuit according to the present invention. 11, 12. 13. 16... selection circuit, 14.
. . . Multiplication circuit, 15 . . . Selection output circuit, 17 . . . Comparison circuit.
Claims (1)
きそれぞれ、第1(又は第2)の映像入力信号を選択す
る第1の選択回路、第2(又は第1)の映像入力信号を
選択する第2の選択回路及び第1(又は第2)のフェー
ダコントロール信号を選択する第3の選択回路と、上記
第1及び第3の選択回路の選択出力を乗算する乗算回路
と、上記乗算回路の乗算出力及び上記第2の選択出力の
うち大きい方を選択してミキシング出力信号として送出
する選択出力回路とを具えることを特徴とするミキシン
グ回路。a first selection circuit that selects the first (or second) video input signal when the selection control signal is in the first (or second) selection mode, and a second (or first) video input signal; a second selection circuit that selects the fader control signal; a third selection circuit that selects the first (or second) fader control signal; a multiplication circuit that multiplies the selection outputs of the first and third selection circuits; A mixing circuit comprising: a selection output circuit that selects the larger of the multiplication output of the multiplication circuit and the second selection output and sends it out as a mixing output signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11534783U JPS6025281U (en) | 1983-07-25 | 1983-07-25 | mixing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11534783U JPS6025281U (en) | 1983-07-25 | 1983-07-25 | mixing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6025281U true JPS6025281U (en) | 1985-02-20 |
JPH0112453Y2 JPH0112453Y2 (en) | 1989-04-11 |
Family
ID=30266294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11534783U Granted JPS6025281U (en) | 1983-07-25 | 1983-07-25 | mixing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6025281U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63202402U (en) * | 1987-06-09 | 1988-12-27 |
-
1983
- 1983-07-25 JP JP11534783U patent/JPS6025281U/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63202402U (en) * | 1987-06-09 | 1988-12-27 | ||
JPH0534801Y2 (en) * | 1987-06-09 | 1993-09-03 |
Also Published As
Publication number | Publication date |
---|---|
JPH0112453Y2 (en) | 1989-04-11 |
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