JPS60140822A - Electron-ray drawing device - Google Patents
Electron-ray drawing deviceInfo
- Publication number
- JPS60140822A JPS60140822A JP58246288A JP24628883A JPS60140822A JP S60140822 A JPS60140822 A JP S60140822A JP 58246288 A JP58246288 A JP 58246288A JP 24628883 A JP24628883 A JP 24628883A JP S60140822 A JPS60140822 A JP S60140822A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- marks
- detected
- predicting
- mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electron Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は電子線描画装置に係り、特に試料台が連続移動
している状態で描画１゛る方式において。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an electron beam lithography system, and particularly to a system in which lithography is performed while a sample stage is continuously moving.
高精度の位置合せ描画が可能な電子線描画装置に関する
。The present invention relates to an electron beam lithography device capable of highly accurate alignment lithography.
電子線描画装置の描画方式には大別して２方式がある。 There are two main types of lithography methods for electron beam lithography devices.
１方式は試料台が停止した状態で描画を行うもの、もう
１方式は試料台を連続的に移動している状態で描画全行
うものである。One method is to perform drawing while the sample stage is stopped, and the other method is to perform all drawings while the sample stage is continuously moving.
試料台停止型の装置において位置合せ描画を行う場合の
例會第１図に示す。第１図は半導体ウェハ２にＬＳＩの
チップ６の図形を電子線描画法により描画する場合介示
したものである。図中、１は試料台、２は半導体ウェハ
、３はＬＳＩチップを示しており、４はＬＳＩチップ部
分の拡大図である。５． ６． ７． ８はチップ周囲
に設けられたマーク全示している。位置合せ用マークと
しては例えばＬＳＩチップ４の周囲に設けられたマーク
５〜８を用いる。マーク間の距離が電子線の偏向範囲全
滅える場合は試料台を移動し各マークの位置を検出した
後チップ４０図形を描画する。この方式では描画図形の
近傍のマークを検出した後描画？行うため高精度の位置
合せが可能である。この方式の欠麿は試料台の移動時間
が無駄時間となり、高スルーブツトが期待できないこと
である。FIG. 1 shows an example of positioning and drawing performed in a sample stand stop type device. FIG. 1 shows a case in which the shape of an LSI chip 6 is drawn on a semiconductor wafer 2 by electron beam lithography. In the figure, 1 is a sample stage, 2 is a semiconductor wafer, 3 is an LSI chip, and 4 is an enlarged view of the LSI chip portion. 5. 6. 7. 8 shows all the marks provided around the chip. As alignment marks, for example, marks 5 to 8 provided around the LSI chip 4 are used. If the distance between the marks completely annihilates the deflection range of the electron beam, the sample stage is moved, the position of each mark is detected, and then the chip 40 figure is drawn. Is this method used to detect marks near the drawn figure and then draw? Because of this, highly accurate alignment is possible. The disadvantage of this method is that the time required to move the sample stage is wasted time, and high throughput cannot be expected.
一方試料台連続移動方式において位置合せ描画を行う場
合［は第２図に示すように半導体ウエノ１２上に設けら
れたマーク９．１０’＆検出した後。On the other hand, when alignment drawing is performed in the sample stage continuous movement method, [marks 9 and 10' provided on the semiconductor wafer 12 are detected as shown in FIG.
試料台１を矢印１１で示すようｉＣＸ軸方向に連続して
往復移動する。ＬＳＩ図形はこの試料台の移動と同時に
描画されるため、試料台の起動、移動、停止に伴う無駄
時間がなくなるため、高スループツトが実現できる。こ
の方式の欠点はウェハ内数点のマーク座標より全チップ
の描画位置を決定するため、チップ内での図形の歪、電
子線の位置ドリフトの補正を行うことができないため高
精度の位置合せが困難であることである。The sample stage 1 is continuously moved back and forth in the iCX axis direction as shown by arrow 11. Since the LSI figure is drawn simultaneously with the movement of the sample stand, there is no wasted time associated with starting, moving, and stopping the sample stand, and high throughput can be achieved. The disadvantage of this method is that the writing position of all chips is determined from the mark coordinates of several points on the wafer, so it is not possible to correct the distortion of the figure within the chip and the positional drift of the electron beam, making it difficult to achieve high-precision alignment. It is difficult.
本発明の目的は前述した試料台固定型の描画装置のもつ
高位置会せの特長と、試料台連続移動型の描画装置のも
つ高スループツトの特長ケ兼ね備えた電子線描画装置の
機能構造全提供することにある。The purpose of the present invention is to provide a complete functional structure of an electron beam lithography system that combines the above-mentioned feature of high position alignment of the fixed sample stage type lithography system and the high throughput feature of the sample stage continuously moving type lithography system. It's about doing.
上記の目的を達成するため、本発明の描画装置において
は試料台が連続的に移動している状態で描画１行う時、
被描画試料内に配列された位置合せマークのうち既に検
出したチップマークの位置情報より次に検出するチップ
マークの位置を予測して描画全行うものである。チップ
マーク位置の予測に用いる別チップを次に描画するチッ
プの近傍に選ぶことにより高精度の位置合せを可能とす
るものである。In order to achieve the above object, in the drawing apparatus of the present invention, when drawing 1 is performed while the sample stage is continuously moving,
The entire drawing is performed by predicting the position of the next detected chip mark based on the position information of the already detected chip mark among the alignment marks arranged in the sample to be drawn. By selecting another chip used for predicting the chip mark position near the next chip to be drawn, highly accurate positioning is possible.
以下、本発明全実施例により詳しく説明する。 Hereinafter, the present invention will be explained in detail with reference to all embodiments.
実施例１
第３図は本発明の一実施例を示す図である。同図（ａ）
は本発明の構能構造ケ示すもので、電子線１２は被描画
試料１７に照射され、その反射電子が検出器１３によっ
て検出される。同図（ｂ）の半導体ウェハ１７の１つの
チップ１８の描画が完了しているとき、チップ周辺のマ
ークＭｌ、Ｍ２． Ｍ３゜Ｍ４は既に位置検出が終了し
ており記憶装置１５にそのデータが蓄えられている。次
に試料台が２０の方向に移動し、チップ１９の周辺マー
クＭ５．Ｍ６．Ｍ７．Ｍ８のうちＭ５とＭ６の位置検出
が行われる。Ｍ１〜Ｍ４の位１［１情報よりチップ１９
の図形の歪が予測回路１６により計算され、マークＭ５
〜Ｍ８の予測座標が計算される。この予測座標はＭ５．
Ｍ６の位置検出が行われた後はＭ５．Ｍ６の予測座標と
のずれ全Ｍ５〜Ｍ８の位置にフィードバックし偏向器１
４によって図形が描画される。Embodiment 1 FIG. 3 is a diagram showing an embodiment of the present invention. Figure (a)
1 shows the functional structure of the present invention, in which an electron beam 12 is irradiated onto a sample 17 to be drawn, and the reflected electrons are detected by a detector 13. When the drawing of one chip 18 on the semiconductor wafer 17 in FIG. 2B is completed, marks M1, M2 . Position detection has already been completed for M3 and M4, and the data is stored in the storage device 15. Next, the sample stage moves in the direction 20, and the peripheral mark M5. M6. M7. The positions of M5 and M6 among M8 are detected. M1-M4 digit 1 [chip 19 from 1 information
The distortion of the figure is calculated by the prediction circuit 16, and the mark M5 is calculated by the prediction circuit 16.
The predicted coordinates of ~M8 are calculated. This predicted coordinate is M5.
After the position of M6 is detected, M5. The deviation from the predicted coordinates of M6 is fed back to the positions of all M5 to M8, and the deflector 1
4, the figure is drawn.
このように描画された図形と下地図形との位置合せの誤
差は±０．３μｍ以内であり、試料台固定式と比べて差
が認められなか゛つた。The error in alignment between the figure drawn in this way and the underlying map figure was within ±0.3 μm, and no difference was observed compared to the fixed sample stage type.
実権例２
第４図は本発明の他の一実施例管示すものである。第４
図に示すように半導体ウェハ２１の周辺に２個のマーク
２２．２３（ウェハマーク、長さ５００μｍ）、と１０
閲間隔長さ５０μｍのマーク（チップマーク）Ｍｌ、Ｍ
２．・・・・・・Ｍ２Ｓ、・・・・・・・・・を配列し
た。′電子線描画装置の電子線偏向範囲は上２゜５順で
あるため、１チツプを１／２に分割して描画する。まず
試料台全移動して２個のウェハマーク２２．２３の位置
検出を行う。この後試料台は連続移動モードに移る。ウ
ェハマーク２２．２３の位置情報よりチップマークＭ
１ 、Ｍ ２゜Ｍｌｏ、Ｍ９の位置ケ予測する。描画装
置がチップマークＭｌ’ｊｚ検出した後、Ｍｌの位置の
予測値と実測値との差をチップマークＭ２．Ｍ１０゜Ｍ
９の予測値にフィードバック全かけて第１チツプの１／
２の部分２５を描画する。次に第２チツプの１／２の部
分２６を描画するときは既に検出したマーク２２．２＋
１Ｍ１．Ｍ２よりチップマークＭ３．Ｍ８．Ｍ９の位置
を予測して行う。Practical Example 2 FIG. 4 shows another embodiment of the present invention. Fourth
As shown in the figure, two marks 22, 23 (wafer mark, length 500 μm) and 10 are placed around the semiconductor wafer 21.
Marks (chip marks) with viewing interval length of 50 μm Ml, M
2.・・・・・・M2S, ・・・・・・・・・ were arranged. 'Since the electron beam deflection range of the electron beam lithography system is in the upper 2°5 order, one chip is divided into 1/2 for lithography. First, the entire sample stage is moved to detect the positions of the two wafer marks 22 and 23. After this, the sample stage shifts to continuous movement mode. Chip mark M based on the position information of wafer marks 22 and 23
1, M2°Mlo, and predict the position of M9. After the drawing device detects the chip mark Ml'jz, the difference between the predicted value and the actual value of the position of Ml is calculated as the chip mark M2. M10゜M
Multiply the predicted value of 9 by all feedback to 1/1 of the first chip.
Draw part 25 of 2. Next, when drawing the 1/2 portion 26 of the second chip, the already detected mark 22.2+
1M1. Chip mark M3 from M2. M8. This is done by predicting the position of M9.
本実施例での位置合せの誤差は上０゜４μｍであった。The alignment error in this example was 0.4 μm above.
実施例では１チツプ周辺に４個のチップマークを配置し
た例を示したが、チップマーク検出の回数ケ減らすため
数チップを１ブロツクとして１ブロツクの周辺に複数の
マークを配置する方法においても同様に本発明の描画装
置で位置合せ描画を行うことかり能である。In the embodiment, an example was shown in which four chip marks were arranged around one chip, but the same method can be used in which several chips are made into one block and multiple marks are arranged around one block in order to reduce the number of chip mark detections. It is possible to perform alignment drawing using the drawing apparatus of the present invention.
以上説明したごとく本発明によれば高いスループットヲ
有する試料台連続移動方式の電子線描画装置において、
チップマークによる位置合せ方式を採用することが可能
となるので、高精度位置合わせと、高スループットｌ兼
ね備えた電子線描画装置を実現することができる。As explained above, according to the present invention, in an electron beam lithography system using a sample stage continuous movement type having a high throughput,
Since it is possible to employ a positioning method using chip marks, it is possible to realize an electron beam lithography apparatus that has both high precision positioning and high throughput.
第１図は試料台固定描画方式での位置合せ方法分示す図
、第２図は試料台連続移動描画方式での位置合せ方法全
示す図、第３図（ａ）、 （ｂ）は本発明による電子線
描画装置の構成分示すブロック図とこれ管用いて位置合
せ描画を行う方法を説明するための図、第４図は本発明
の゛電子線描画装置を用いて位置合せ描画ケ行うための
他の一実施例ケ示す図である。
図中、１ｉｌ−ｊ′試料台、２は半導体ウェハ、６はＬ
ＳＩチップ、４はＬＳＩチップ拡大図、５〜８はチップ
マーク、９，１０ｉｄウエハマーク、１１は試料台の移
動方向、１２は電子線、１３は反射電子線の検出器、１
４は電子線の偏向器、１５はマーク位置座標の記憶回路
、１６は描画チップのマーク位置座標の予測回路、１７
は半導体ウェハ、１８はチップ周辺のマークの位置の完
了したチップ、１９は次に描画すべきチップ、２０は試
料台の移動方向、２１は半導体ウェハ、２２．２３はウ
ェハマーク、２５〜６４は１チツプの１／２、Ｍ１〜Ｍ
１５はチップマークである。
第 １ 固
第 ２ 図
第 ３ 図
（ｂ）Fig. 1 is a diagram showing the positioning method using the sample stage fixed drawing method, Fig. 2 is a diagram showing the entire positioning method using the sample stage continuous moving drawing method, and Figs. 3 (a) and (b) are diagrams showing the method according to the present invention. FIG. 4 is a block diagram showing the components of an electron beam lithography system according to the present invention, and a diagram for explaining a method for performing alignment lithography using this tube. It is a figure which shows another example. In the figure, 1il-j' sample stage, 2 is a semiconductor wafer, and 6 is L.
SI chip, 4 is an enlarged view of the LSI chip, 5 to 8 are chip marks, 9 and 10 ID wafer marks, 11 is the moving direction of the sample stage, 12 is an electron beam, 13 is a detector for reflected electron beam, 1
4 is an electron beam deflector, 15 is a storage circuit for mark position coordinates, 16 is a prediction circuit for mark position coordinates of a drawing chip, 17
18 is a semiconductor wafer, 18 is a chip whose peripheral mark position has been completed, 19 is a chip to be written next, 20 is a moving direction of the sample stage, 21 is a semiconductor wafer, 22.23 is a wafer mark, 25 to 64 are 1/2 of 1 chip, M1~M
15 is a chip mark. Figure 1 Figure 2 Figure 3 (b)
Claims (1)
固装＃において、被描画チップ周辺の位置合せマークの
位置座標を既に検出した別チップ周辺のマークの位置情
報より推定し描画位置を決定する機能を有する電子線描
画装置。In electron beam lithography system #, which performs lithography while the sample stage is continuously moving, the lithography position is estimated by estimating the position coordinates of the alignment mark around the chip to be lithographically detected from the position information of the mark around another chip that has already been detected. An electron beam lithography device that has the function of determining.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58246288A JPS60140822A (en) | 1983-12-28 | 1983-12-28 | Electron-ray drawing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58246288A JPS60140822A (en) | 1983-12-28 | 1983-12-28 | Electron-ray drawing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60140822A true JPS60140822A (en) | 1985-07-25 |
Family
ID=17146313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58246288A Pending JPS60140822A (en) | 1983-12-28 | 1983-12-28 | Electron-ray drawing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60140822A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6229135A (en) * | 1985-07-29 | 1987-02-07 | Advantest Corp | Charged particle beam exposure and device thereof |
| JPH0287516A (en) * | 1988-09-26 | 1990-03-28 | Toshiba Corp | Position control method of electron beam lithography equipment |
| JPH04112117U (en) * | 1991-03-15 | 1992-09-29 | 三菱農機株式会社 | Combine power transmission device |
| JPH04112118U (en) * | 1991-03-15 | 1992-09-29 | 三菱農機株式会社 | combine gearing |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54118777A (en) * | 1978-03-08 | 1979-09-14 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of exposing pattern |
| JPS5662322A (en) * | 1979-10-26 | 1981-05-28 | Fujitsu Ltd | Electronic beam exposure method |
-
1983
- 1983-12-28 JP JP58246288A patent/JPS60140822A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54118777A (en) * | 1978-03-08 | 1979-09-14 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of exposing pattern |
| JPS5662322A (en) * | 1979-10-26 | 1981-05-28 | Fujitsu Ltd | Electronic beam exposure method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6229135A (en) * | 1985-07-29 | 1987-02-07 | Advantest Corp | Charged particle beam exposure and device thereof |
| JPH0287516A (en) * | 1988-09-26 | 1990-03-28 | Toshiba Corp | Position control method of electron beam lithography equipment |
| JPH04112117U (en) * | 1991-03-15 | 1992-09-29 | 三菱農機株式会社 | Combine power transmission device |
| JPH04112118U (en) * | 1991-03-15 | 1992-09-29 | 三菱農機株式会社 | combine gearing |
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