JPH0312916A - Electron beam lithography - Google Patents
Electron beam lithographyInfo
- Publication number
- JPH0312916A JPH0312916A JP15009989A JP15009989A JPH0312916A JP H0312916 A JPH0312916 A JP H0312916A JP 15009989 A JP15009989 A JP 15009989A JP 15009989 A JP15009989 A JP 15009989A JP H0312916 A JPH0312916 A JP H0312916A
- Authority
- JP
- Japan
- Prior art keywords
- vernier
- scribe line
- patterns
- electron beam
- drawn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000609 electron-beam lithography Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000007493 shaping process Methods 0.000 claims description 9
- 238000010894 electron beam technology Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000001459 lithography Methods 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Electron Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子ビーム描画方法に関し、特に可変整形型電
子ビーム描画装置を用いた電子ビーム描画方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electron beam lithography method, and more particularly to an electron beam lithography method using a variable shaping type electron beam lithography apparatus.
集積回路の微細化、高精度化に伴なって回路パターンの
描画には、描画精度と描画スピードの両面の優位性から
、可変整形型電子ビーム描画装置を用いて、レジスト膜
の形成された半導体基板（以下ウェハーという）に直接
パターンを描画する、電子ビーム直接描画方法が用いら
れるようになってきた。With the miniaturization and higher precision of integrated circuits, semiconductors with resist films formed using variable shaping electron beam lithography equipment are being used to draw circuit patterns due to their superiority in both drawing precision and drawing speed. Electron beam direct writing methods, which draw patterns directly on substrates (hereinafter referred to as wafers), have come into use.
この可変整形型電子ビーム描画装置においては第４図に
示す様に、ウェハーに照射する電子ビーム１４は、２個
の整形スリット１．５．１８で矩形整形され、縮小レン
ズ１９で縮小された後、ビームの位置決め偏向器２０で
照射位置が決定され、ウェハーの回路パターン領域２上
にパターンを描画する機構となっている。In this variable shaping type electron beam lithography system, as shown in FIG. The irradiation position is determined by a beam positioning deflector 20, and a pattern is drawn on the circuit pattern area 2 of the wafer.
上述した従来の電子ビーム描画装置は、電子ビームの偏
向可能な領域、すなわちフィールドサイズが数１１１ｍ
であるため、集積回路の１チツプのサイズがフィールド
サイズを越えると、１チツプを描画するには複数のフィ
ールドに分割して描画しなければならない。In the conventional electron beam lithography system described above, the area where the electron beam can be deflected, that is, the field size is several 111 m.
Therefore, if the size of one chip of an integrated circuit exceeds the field size, it is necessary to divide the chip into multiple fields to draw one chip.
一方、電子ビーム描画装置の特性−」二、フィールドの
接続部分においてパターン描画精度か最も悪くなるにも
かかわらず、従来の電子ヒーム直接描画方法ではフィー
ルドの接続部か複雑な回路パターンになるか、パターン
の存在しないスクライブ線領域になっている為、描画精
度か悪化した時の発見が困難である。このため描画精度
の異常に起因する集積回路の性能劣化や不良は、回路製
造工程の最終まで発見てきす、納期や工数に著しく不利
となる欠点がある。On the other hand, the characteristics of electron beam lithography equipment - 2. Although the pattern writing accuracy is the worst at the field connection part, does the conventional electron beam direct writing method result in a complex circuit pattern at the field connection part? Since the area is a scribe line area where no pattern exists, it is difficult to detect when the drawing accuracy has deteriorated. For this reason, performance deterioration or defects in integrated circuits due to abnormalities in drawing precision cannot be detected until the final stage of the circuit manufacturing process, which has the disadvantage of significantly reducing delivery time and man-hours.
本発明の電子ビーム描画方法は、可変整形型電子ビーム
描画装置を用いてレジスト膜の形成された半導体基板に
パターンを直接描画する電子ヒーム描画方法において、
前記半導体基板のスクライブ線領域の少くとも交差する
部分にバーニアパターンを描画するものである。The electron beam lithography method of the present invention is an electron beam lithography method in which a pattern is directly drawn on a semiconductor substrate on which a resist film is formed using a variable shaping type electron beam lithography apparatus.
A vernier pattern is drawn at least in a portion where the scribe line regions of the semiconductor substrate intersect.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例を説明するための回路パ
ターン領域２とスクライブ線領域３とからなるチップ領
域を示す図である。FIG. 1 is a diagram showing a chip area consisting of a circuit pattern area 2 and a scribe line area 3 for explaining a first embodiment of the present invention.
まず第１図に示す様にレジスト膜が形成されたウェハー
上に、描画用データにより回路パターン領域２内にパタ
ーンを描画すると共に、スクライブ線領域３のコーナ一
部分４カ所にバーニアパターン６を描画する。First, as shown in FIG. 1, on a wafer on which a resist film has been formed, a pattern is drawn in the circuit pattern area 2 using drawing data, and vernier patterns 6 are drawn in four corners of the scribe line area 3. .
このバーニアパターン６は第２図に示すように、スクラ
イブ線領域の中心線１をはさんで形成された疎バーニア
部４と微バーニア部５の対により構成される。５μｎ１
の疎バーニア部４と４９μｍの微バーニア部５からなる
バーニアパターン６を描画して現像すると、スクライブ
線領域３内で各チップ領域のコーナ一部に０．０５μｍ
１単位で描画位置精度を読み取れるバーニアパターン６
が形成される。As shown in FIG. 2, this vernier pattern 6 is composed of a pair of a sparse vernier section 4 and a fine vernier section 5, which are formed on both sides of the center line 1 of the scribe line region. 5μn1
When a vernier pattern 6 consisting of a coarse vernier portion 4 of 49 μm and a fine vernier portion 5 of 49 μm is drawn and developed, a 0.05 μm thick vernier pattern 6 is formed on a part of the corner of each chip area within the scribe line area 3.
Vernier pattern 6 that allows you to read the drawing position accuracy in 1 unit
is formed.
このバーニアパターン６を顕微鏡により観察することに
より、回路パターン領域２中のパターンの位置ずれを定
量的に測定することができる。半導体集積回路の製造歩
留り及び特性劣化に影響を及ぼさないパターンの位置ず
れ量をあらかじめ求めて規格値とすることにより、バー
ニアパターン６による位置ずれ測定結果を照合し、規格
内のものを良品とする。この操作により、製造歩留り等
を向上させることができる。By observing this vernier pattern 6 with a microscope, the positional deviation of the pattern in the circuit pattern area 2 can be quantitatively measured. By determining in advance the amount of positional deviation of the pattern that does not affect the manufacturing yield and characteristic deterioration of semiconductor integrated circuits and setting it as a standard value, the results of positional deviation measurement using the vernier pattern 6 are compared, and those within the standard are considered non-defective. . This operation can improve manufacturing yield and the like.
第３図は本発明の第２の実施例を説明するためのチップ
領域を示す図である。FIG. 3 is a diagram showing a chip area for explaining a second embodiment of the present invention.
木簡２の実施例は回路パターン領域２が複数のフィール
ド８により構成される場合であり、スクライブ線領域３
内のフィールド境界線７の交差する部分すべてにバーニ
アパターン６を描画する。In the embodiment of the wooden tablet 2, the circuit pattern area 2 is composed of a plurality of fields 8, and the scribe line area 3
A vernier pattern 6 is drawn at all intersections of field boundary lines 7 in the field.
この為１チツプ領域を複数のフィールドに分割した時に
、チップ領域がフィールドサイズで割り切れない場合に
発生する微小フィールド８Ａが存在しても、見かけの描
画精度が良くなる微小フィールド８Ａのコーナ一部より
、隣接するバーニアパターン６でより正確に描画精度を
測定できる利点かある。For this reason, when one chip area is divided into multiple fields, even if there is a small field 8A that occurs when the chip area is not divisible by the field size, the apparent drawing accuracy is better than the part of the corner of the small field 8A. , there is an advantage that drawing accuracy can be measured more accurately using adjacent vernier patterns 6.
以上説明したように本発明は、可変整形型電子ビーム描
画装置を用いた直接描画方法において、半導体基板に形
成するスクライブ線領域の少くとも交差する部分にバー
ニアパターンを形成することにより、簡便な方法で回路
パターンの描画位置精度を定量的に測定できるため、半
導体集積回路の製造を効率的に行なえるという効果があ
る。As explained above, the present invention provides a simple method in which a vernier pattern is formed at least in the intersection of scribe line regions formed on a semiconductor substrate in a direct writing method using a variable shaping electron beam writing device. Since the accuracy of the drawing position of a circuit pattern can be measured quantitatively, it is effective in efficiently manufacturing semiconductor integrated circuits.
第１図は本発明の第１の実施例を説明するためのチップ
領域を示す図、第２図は本発明の実施例におけるバーニ
アパターンを示す図、第３図は本発明の第２の実施例を
説明するためのチップ領域を示す図、第４図は電子ビー
ム描画装置の構成図である。
］・・・スクライブ線領域の中心線、２・・・回路パタ
ーン領域、３・・・スクライブ線領域、４・・・疎バー
ニア部、５・・・微バーニア部、６・・バーニアパター
ン、７ ・フィールド境界線、１３・・・電子銃、１４
・・・電子ビーム、１５・・・第１整形スリツト、１６
・・集束レンズ、
１
７・・
ヒーム整形偏向器、
・第
２整形スリツト、
９・・・縮小レンズ、
２０・・位置
決め偏向器。FIG. 1 is a diagram showing a chip area for explaining a first embodiment of the present invention, FIG. 2 is a diagram showing a vernier pattern in the embodiment of the present invention, and FIG. 3 is a diagram showing a second embodiment of the present invention. FIG. 4, which is a diagram showing a chip area for explaining an example, is a configuration diagram of an electron beam lithography apparatus. ]...Center line of scribe line area, 2...Circuit pattern area, 3...Scribe line area, 4...Sparse vernier portion, 5...Fine vernier portion, 6...Vernier pattern, 7・Field boundary line, 13... Electron gun, 14
...electron beam, 15...first shaping slit, 16
...Focusing lens, 1 7.. Heam shaping deflector, - 2nd shaping slit, 9.. Reducing lens, 20.. Positioning deflector.
Claims (1)
成された半導体基板にパターンを直接描画する電子ビー
ム描画方法において、前記半導体基板のスクライブ線領
域の少くとも交差する部分にバーニアパターンを描画す
ることを特徴とする電子ビーム描画方法。In an electron beam lithography method in which a pattern is directly drawn on a semiconductor substrate on which a resist film is formed using a variable shaping electron beam lithography device, a vernier pattern is drawn on at least a portion intersecting a scribe line region of the semiconductor substrate. An electron beam writing method characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15009989A JPH0312916A (en) | 1989-06-12 | 1989-06-12 | Electron beam lithography |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15009989A JPH0312916A (en) | 1989-06-12 | 1989-06-12 | Electron beam lithography |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0312916A true JPH0312916A (en) | 1991-01-21 |
Family
ID=15489489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15009989A Pending JPH0312916A (en) | 1989-06-12 | 1989-06-12 | Electron beam lithography |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0312916A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665495A (en) * | 1994-03-10 | 1997-09-09 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a semiconductor with a photomask |
| JP2006070537A (en) * | 2004-09-01 | 2006-03-16 | Mitsuo Yamamoto | Right-angled v-shaped energy dissipator, cascade work using the same, and stepped-down waterway using them |
-
1989
- 1989-06-12 JP JP15009989A patent/JPH0312916A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665495A (en) * | 1994-03-10 | 1997-09-09 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a semiconductor with a photomask |
| JP2006070537A (en) * | 2004-09-01 | 2006-03-16 | Mitsuo Yamamoto | Right-angled v-shaped energy dissipator, cascade work using the same, and stepped-down waterway using them |
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