JPS60136347A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60136347A JPS60136347A JP58244051A JP24405183A JPS60136347A JP S60136347 A JPS60136347 A JP S60136347A JP 58244051 A JP58244051 A JP 58244051A JP 24405183 A JP24405183 A JP 24405183A JP S60136347 A JPS60136347 A JP S60136347A
- Authority
- JP
- Japan
- Prior art keywords
- gel material
- wire
- resin
- lead frame
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/298—Semiconductor material, e.g. amorphous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特に樹脂封止型パッケージよりな
る半導体装置およびその製造技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device comprising a resin-sealed package and a manufacturing technique thereof.
樹脂封止型の半導体装置においては、４２７０イまたは
コバール等で作られたリードフレームとパッケージの樹
脂材料との界面等から水分がパッケージ内に浸入し易く
、その水分のためにアルミニウムまたは金等のワイヤあ
るいはアルミニウムの電極パッドが腐食され、ワイヤ切
れやボンディング部の剥れを生じることがありうる。ま
た、樹脂材料からのα線の影響でソフトエラーが発生す
るという問題もありうる。In resin-sealed semiconductor devices, moisture easily enters the package from the interface between the lead frame made of 4270I or Kovar and the resin material of the package. Corrosion of the wire or aluminum electrode pad may occur, resulting in wire breakage or peeling of the bond. Additionally, there may be a problem that soft errors may occur due to the influence of alpha rays from the resin material.
そこで、このような問題を解消すべく、ペレツト上にシ
リコンゲルの如きゲル材料をボッティングしてワイヤを
部分的にゲル材料で覆うことが考えられる。In order to solve this problem, it is conceivable to pot a gel material such as silicone gel onto the pellet to partially cover the wire with the gel material.
ところが、この場合には、ワイヤが部分的にしかゲル材
料で覆われておらず、ワイヤの残り部分ハハノケージの
樹脂材料で覆われることになるので、熱膨張係数の異な
るゲル材料と樹脂材料との界面においてワイヤ切れが発
生するという問題がある。However, in this case, the wire is only partially covered with the gel material, and the rest of the wire is covered with the resin material of the cage, so the gel material and the resin material have different coefficients of thermal expansion. There is a problem that wire breakage occurs at the interface.
本発明の目的は、ワイヤ切れや腐食を防止できる技術を
提供することにある。An object of the present invention is to provide a technique that can prevent wire breakage and corrosion.
本発明の他の目的は、樹脂材料からのα線の影響を低減
できる技術を提供することにある。Another object of the present invention is to provide a technique that can reduce the influence of alpha rays from resin materials.
本発明の他の目的は低コストで高信頼性の半導体装置を
得ることのできる技術を提供することにある。Another object of the present invention is to provide a technique that makes it possible to obtain a highly reliable semiconductor device at low cost.
本発明の前記ならびにその他の目的と新規な特徴は、不
明ａ書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of Book A and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、ワイヤを全体的にゲル材料で榎うことにより
、材料間の熱膨張係数の差に起因するワイヤ切れやα線
の影響等を防止できる。That is, by covering the entire wire with gel material, it is possible to prevent wire breakage caused by differences in thermal expansion coefficients between materials, the influence of alpha rays, and the like.
また、ワイヤを全体的にゲル材料で捷った後に樹脂封止
することにより、低コストで高信頼性の半導体装置を得
ることができる。Furthermore, by wrapping the entire wire with a gel material and then sealing it with resin, a highly reliable semiconductor device can be obtained at low cost.
〔実施例１〕
第１図〜第４図は本発明による半導体装置の製造方法の
一実施例を順次示す断面図である。[Embodiment 1] FIGS. 1 to 4 are cross-sectional views sequentially showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.
本実施例では、第１図に示すように、たとえば４２アロ
イまたはコバール等の金属で作られたリードフレーム１
のタブ２上にペレット３を取り付けた後、該ペレット３
０電極パツドとリードフレーム１のインナーリード部と
をワイヤ４で電気的に接続する。In this embodiment, as shown in FIG. 1, a lead frame 1 made of metal such as 42 alloy or Kovar is used.
After attaching the pellet 3 on the tab 2 of
The 0 electrode pad and the inner lead portion of the lead frame 1 are electrically connected with a wire 4.
次に、このリードフレーム１を逆さ状態に反転して該リ
ードフレームｌを型治具５の支持壁６上に支持させ、か
つビン孔７にピン８を挿通して位置決めを行う。この型
治具５の支持壁６の中央上部には表面をフッ素樹脂でコ
ーティングしたキャピテイ９が形成され、このキャピテ
イ９内にはシリコンゲルの如きゲル材料１０が予め充填
されている。また、キャビティ９の中央部がら型治具５
をその裏面まで貫通して形成された空気抜き孔にはピン
抜き治具１１のピン１２が挿脱自在に挿入されている。Next, the lead frame 1 is turned upside down, the lead frame 1 is supported on the support wall 6 of the mold jig 5, and the pin 8 is inserted into the pin hole 7 for positioning. A cavity 9 whose surface is coated with fluororesin is formed at the upper center of the support wall 6 of the mold jig 5, and this cavity 9 is filled in advance with a gel material 10 such as silicone gel. In addition, the empty mold jig 5 in the center of the cavity 9
A pin 12 of a pin extraction jig 11 is removably inserted into an air vent hole formed by penetrating the pin to the back surface thereof.
したがって、リードフレーム１の下側に位置するペレッ
ト３およびワイヤ４は全体的にゲル材料１０で覆われる
（第２図）。Therefore, the pellet 3 and the wire 4 located on the underside of the lead frame 1 are completely covered with the gel material 10 (FIG. 2).
このゲル材料１０はたとえば２００℃の温度で４時間程
度加熱処理することにより、硬化する。This gel material 10 is cured by heat treatment at a temperature of, for example, 200° C. for about 4 hours.
その後、ワイヤ４を硬化ゲル材料１ｏで完全に罹った状
態のリードフレーム１はビン抜キ治具１１を型治具５か
ら抜き出すことにより、型治具５上から容易に取り外す
ことができる。Thereafter, the lead frame 1 with the wire 4 completely covered with the hardened gel material 1o can be easily removed from the mold jig 5 by extracting the bottle removal jig 11 from the mold jig 5.
次いで、このリードフレームｌは再び第１図の如くペレ
ット３が上側に来る状態に戻され、通常の樹脂モールド
工程に送られる。Next, this lead frame 1 is returned to the state in which the pellet 3 is on the upper side as shown in FIG. 1, and sent to a normal resin molding process.
樹脂モールド工程では、リードフレーム１け第３図に示
すように、上型１３と下型１４との間に挾み込まれ、両
型のキャピテイ内には、図示しない樹脂源からエポキシ
樹脂等のパッケージ用樹脂１５が出入された後、熱硬化
される。In the resin molding process, one lead frame is inserted between an upper mold 13 and a lower mold 14, as shown in FIG. After the packaging resin 15 is taken in and out, it is thermally cured.
それにより、リードフレームｌの切断、折曲げを行い、
リード１人とした第４図に示すように、ワイヤ４をゲル
材料１ｏで完全に覆った上から樹脂１５で刺止された半
導体装置が得られる。As a result, the lead frame l is cut and bent,
As shown in FIG. 4 with only one lead, a semiconductor device is obtained in which the wire 4 is completely covered with the gel material 1o and the resin 15 is stuck thereon.
〔実施例２〕
第５図〜第９図は本発明の他の実施例による半導体装置
の製造過程を順次示す断面図である。[Embodiment 2] FIGS. 5 to 9 are cross-sectional views sequentially showing the manufacturing process of a semiconductor device according to another embodiment of the present invention.
この実施例では、第５図に示すように、まず最初Ｆｉｍ
１図と同じくリードフレーム１のタブ２上にペレット３
を取り付けかつワイヤ４をボンディングする。In this embodiment, as shown in FIG.
As in Figure 1, place pellet 3 on tab 2 of lead frame 1.
and bond the wire 4.
ソノ後、第６図に示す如く、リードフレーム１を裏返し
状態とし、ゲル被覆型１６と１７の間に挾み込む。After sowing, the lead frame 1 is turned over and inserted between the gel coating molds 16 and 17, as shown in FIG.
そして、第７図に示すように、ゲル被覆型１６゜１７の
キャビティ１８の中にゲル材料１０をボッティング等で
供給する。ゲル材料１０は本実施例ではワイヤ４の全体
は勿論、ベレット３とは反対側のリードフレーム面まで
完全に覆っている。このゲル材料１０は前記実施例１と
同様の処理方法等で硬化される。Then, as shown in FIG. 7, the gel material 10 is supplied into the cavity 18 of the gel coating mold 16° 17 by botting or the like. In this embodiment, the gel material 10 completely covers not only the entire wire 4 but also the surface of the lead frame opposite to the pellet 3. This gel material 10 is cured by the same treatment method as in Example 1 above.
その後は前記実施例１における第３図および第４図と同
様に、第８図の樹脂モールド工程を経て第９図に示すよ
うな半導体装置を製造することができる。Thereafter, a semiconductor device as shown in FIG. 9 can be manufactured through the resin molding process shown in FIG. 8 in the same manner as shown in FIGS. 3 and 4 in the first embodiment.
この実施例の場合も、ワイヤ４は完全にゲル材料１０で
覆われ、その上から樹脂１５で封止されている。In this embodiment as well, the wire 4 is completely covered with the gel material 10 and sealed with the resin 15 from above.
〔実施例３〕
第１０図は本発明のさらに他の実施例による半導体装置
の構造を示す断面図である。この実施例は、前記実施例
２の半導体装置に放熱用のスタッドをベレットの裏面に
さらに取り付けた例である。[Embodiment 3] FIG. 10 is a sectional view showing the structure of a semiconductor device according to still another embodiment of the present invention. This embodiment is an example in which a heat dissipation stud is further attached to the back surface of the pellet in the semiconductor device of the second embodiment.
したがって、前記実施例２と同一の部分の説明は省略す
る。Therefore, description of the same parts as in the second embodiment will be omitted.
この実施例では、前記実施例２と同一の製造工程に従う
。すなわち、第６図までの工程を行った後、タブ２の裏
面にスタッド１９を押圧する。スタッド１９は鉄−ニッ
ケル合金（４２７０イ）またはアルミニウム等からなる
。この状態で、第７図の工程を行う。スタッド１９の一
部がボッティングしたゲル材料１０により覆われる。こ
れにより、タブ２とスタッド１９の接着も同時に完了す
る。またスタッド１９とレジン１５の界面圧生じ易い剥
離等がゲル材料により、チップ近傍で防止される。This example follows the same manufacturing process as Example 2 above. That is, after performing the steps up to FIG. 6, the stud 19 is pressed against the back surface of the tab 2. The stud 19 is made of iron-nickel alloy (4270I), aluminum, or the like. In this state, the process shown in FIG. 7 is performed. A portion of the stud 19 is covered by the potted gel material 10. This completes the adhesion between the tab 2 and the stud 19 at the same time. In addition, the gel material prevents peeling, etc., which is likely to occur due to interfacial pressure between the stud 19 and the resin 15, in the vicinity of the chip.
この実施例の場合も、前記実施例１および２と同一の効
果が得られる。また、スタッド１９を設けたので、ベレ
ットからの放熱性が極めてよい。This embodiment also provides the same effects as those of the first and second embodiments. Furthermore, since the stud 19 is provided, heat dissipation from the pellet is extremely good.
スタッド１９とレジン１５との剥離もチップ近傍では防
止され、信頼性を損うことはない。Peeling between the stud 19 and the resin 15 is also prevented in the vicinity of the chip, and reliability is not impaired.
（１１ワイヤの全体がゲル材料で覆われ、そのゲル材料
が樹脂封止されることにより、材料間の熱膨張差による
ワイヤ切れや腐食を防止することができる、
（２） ワイヤが全体的にゲル材料で覆われていること
により、水分の浸入によるワイヤの腐食を防止できる。(11) By covering the entire wire with a gel material and sealing the gel material with resin, it is possible to prevent the wire from breaking or corroding due to the difference in thermal expansion between the materials. By being covered with gel material, corrosion of the wire due to moisture infiltration can be prevented.
（３）ベレット上面が全体的にゲル材料で覆われている
ことにより、パッケージ用樹脂からのα線の影響を低減
できる。(3) Since the top surface of the pellet is entirely covered with gel material, the influence of alpha rays from the packaging resin can be reduced.
（４） ワイヤの全体をゲル材料で覆った後に樹脂封止
することにより、低コストで高信頼性の半導体装置を得
ることができる。(4) By covering the entire wire with a gel material and then sealing it with resin, a highly reliable semiconductor device can be obtained at low cost.
（５） スタッドをゲル材料内に一部覆われるようにし
たことにより、安価で放熱性がよい牛導体装筋を得るこ
とができる。(5) By partially covering the stud in the gel material, it is possible to obtain a cow conductor reinforcing bar that is inexpensive and has good heat dissipation properties.
以上本発明者によってなされた発明を実施例にもとすき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもな−。Although the invention made by the present inventor has been specifically explained above using examples, the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.
たとえは、ワイヤをゲル劇料で覆う方式やゲル材料およ
び樹脂材料の種類等は前記実施例以外にも様々なものを
用いることができる。For example, various methods of covering the wire with the gel material, types of gel materials and resin materials, etc. may be used in addition to those described in the above embodiments.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるデュアルインライン
型パッケージよりなる半導体装置に適用した場合につい
て鰭明しこが、それに限定されるものでれ１なく、たと
えば、フラットパッケージ型半導体装置等に広く適用で
きる。The above explanation mainly describes the case where the invention made by the present inventor is applied to a semiconductor device consisting of a dual in-line package, which is the background field of application, but is not limited thereto. For example, it can be widely applied to flat package type semiconductor devices.
第１図〜第４図は本発明の一実施例である半導体装置の
製造方法を順次段階的に示す断面図、第５図〜第９図は
本発明の他の実施例を順次段４・・・ワイヤ、５・・・
型治具、６・・・支持壁、７・・・ピン孔、８・・・ピ
ン、９・・・キャビティ、１０・・・ゲル材料、１１・
・・ピン抜き治具、１２・・・ピン、１３・・・上型、
１４・・・下型、１５・・・樹脂、１６．１７・・・ゲ
ル被覆第 １ 図
Ｚ
第 ２ 図
笛３図
第 ４ 図
第 ５ 図
第 ０ 図
第 ７ 図
第 ８１ｖＩ
第 ９ 図
第１０図
第１頁の続き
０発 明 者 大 塚 寛 治 小平市上水本町発セン
タ内
０発 明 者 関 正 俊 小平市上水本町発センタ内1 to 4 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention step by step, and FIGS. 5 to 9 show steps 4 and 9 of another embodiment of the present invention. ...Wire, 5...
Mold jig, 6... Support wall, 7... Pin hole, 8... Pin, 9... Cavity, 10... Gel material, 11.
...Pin removal jig, 12...Pin, 13...Upper mold,
14... Lower mold, 15... Resin, 16.17... Gel coating No. 1 Fig. Z Fig. 2 Whistle Fig. 3 Fig. 4 Fig. 5 Fig. 0 Fig. 7 Fig. 81vI Fig. 9 Fig. 10 Continuing from Figure 1 Page 0 Inventor Hiroharu Otsuka Inside the Kamizu Honmachi Departure Center, Kodaira City 0 Inventor Masatoshi Seki Inside the Kamizu Honmachi Departure Center, Kodaira City
Claims (1)
リードフレームのインナーリード部とをワイヤで接続し
てなる半導体装置において、ワイヤの全体がゲル利料で
覆われ、かつ該ゲル材料が樹脂封止されてなることを特
徴とする半導体装置。 ２、 リードフレームに取り付けたペレットの電極部と
リードフレームのインナーリード部とをワイヤで接続し
てなる半導体装置の製造方法において、ワイヤの全体に
ゲル材料で覆った後、該ゲル材料を硬化させ、さらにそ
の硬化ゲル材料を樹脂封止することを特徴とする半導体
装置の製造方法。 ３、 ゲル材料によるワイヤの被覆は、予めキャビティ
内に充填されたゲル材料の中にワイヤを全体的に決める
ことにより行われることを特徴とする特許請求の範囲第
２項記載の半導体装置の製造方法。 ４、 ゲル材料によるワイヤの被覆は、リードフレーム
を所定位置に保持した状態でワイヤの全体にゲル材料を
ボッティングすることにより行われることを特徴とする
特許請求の範囲第２項記載の半導体装置の製造方法。[Claims] 1. In a semiconductor device in which an electrode portion of a pellet attached to a lead frame and an inner lead portion of the lead frame are connected by a wire, the entire wire is covered with a gel material, and the gel material is A semiconductor device characterized in that a material is sealed with a resin. 2. In a method for manufacturing a semiconductor device in which the electrode part of a pellet attached to a lead frame and the inner lead part of the lead frame are connected with a wire, the entire wire is covered with a gel material, and then the gel material is cured. A method for manufacturing a semiconductor device, further comprising encapsulating the cured gel material with a resin. 3. Manufacturing the semiconductor device according to claim 2, wherein the wire is coated with the gel material by placing the wire entirely in the gel material filled in the cavity in advance. Method. 4. The semiconductor device according to claim 2, wherein the wire is coated with the gel material by botting the entire wire with the gel material while the lead frame is held in a predetermined position. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58244051A JPS60136347A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58244051A JPS60136347A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60136347A true JPS60136347A (en) | 1985-07-19 |
Family
ID=17112992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58244051A Pending JPS60136347A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60136347A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0348361A2 (en) * | 1988-06-22 | 1989-12-27 | STMicroelectronics S.r.l. | Hollow plastic package for semiconductor devices |
| EP0361194A2 (en) * | 1988-09-30 | 1990-04-04 | Siemens Aktiengesellschaft | Method of enveloping electrical or electronic components or component assemblies, and envelope for electrical or electronic components or component assemblies |
| DE4022593A1 (en) * | 1990-07-16 | 1992-01-23 | Bock Martin Kunststoff | PLASTIC INJECTION, IN PARTICULAR ARMREST, WITH A CLOSED BASE AND METHOD FOR THE PRODUCTION THEREOF |
| US5106785A (en) * | 1989-01-16 | 1992-04-21 | Siemens Aktiengesellschaft | Method for encapsulating electronic components or assemblies using a thermoplastic encapsulant |
| EP0921565A3 (en) * | 1997-12-08 | 2005-07-27 | Kabushiki Kaisha Toshiba | Package for semiconductor power device and method for assembling the same |
| JP2007095932A (en) * | 2005-09-28 | 2007-04-12 | Sharp Corp | Semiconductor device, its manufacturing method, and electronic apparatus |
| DE102006012615A1 (en) * | 2006-03-20 | 2007-10-11 | Kromberg & Schubert Gmbh & Co. Kg | Enclosing unit, has intermediate layers enclosing electronic circuit, and claddings surrounding intermediate layers, where electronic circuit is surrounded by one intermediate layer |
| FR2919756A1 (en) * | 2007-07-31 | 2009-02-06 | Tacchini Sarl Ets | Electronic component e.g. radio frequency identification type microchip, protecting method for e.g. identification of object in industry, involves placing electronic component in chamber, covering component with resin, and drying resin |
-
1983
- 1983-12-26 JP JP58244051A patent/JPS60136347A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0348361A2 (en) * | 1988-06-22 | 1989-12-27 | STMicroelectronics S.r.l. | Hollow plastic package for semiconductor devices |
| EP0361194A2 (en) * | 1988-09-30 | 1990-04-04 | Siemens Aktiengesellschaft | Method of enveloping electrical or electronic components or component assemblies, and envelope for electrical or electronic components or component assemblies |
| US5106785A (en) * | 1989-01-16 | 1992-04-21 | Siemens Aktiengesellschaft | Method for encapsulating electronic components or assemblies using a thermoplastic encapsulant |
| US5376824A (en) * | 1989-01-16 | 1994-12-27 | Siemens Aktiengesellschaft | Method and an encapsulation for encapsulating electrical or electronic components or assemblies |
| DE4022593A1 (en) * | 1990-07-16 | 1992-01-23 | Bock Martin Kunststoff | PLASTIC INJECTION, IN PARTICULAR ARMREST, WITH A CLOSED BASE AND METHOD FOR THE PRODUCTION THEREOF |
| DE4022593C2 (en) * | 1990-07-16 | 2001-09-13 | Bock Martin Kunststoff | Injection molded plastic armrest and method of manufacturing the armrest |
| EP0921565A3 (en) * | 1997-12-08 | 2005-07-27 | Kabushiki Kaisha Toshiba | Package for semiconductor power device and method for assembling the same |
| JP2007095932A (en) * | 2005-09-28 | 2007-04-12 | Sharp Corp | Semiconductor device, its manufacturing method, and electronic apparatus |
| DE102006012615A1 (en) * | 2006-03-20 | 2007-10-11 | Kromberg & Schubert Gmbh & Co. Kg | Enclosing unit, has intermediate layers enclosing electronic circuit, and claddings surrounding intermediate layers, where electronic circuit is surrounded by one intermediate layer |
| DE102006012615A8 (en) * | 2006-03-20 | 2008-02-28 | Kromberg & Schubert Gmbh & Co. Kg | Enveloped component and method for its production |
| FR2919756A1 (en) * | 2007-07-31 | 2009-02-06 | Tacchini Sarl Ets | Electronic component e.g. radio frequency identification type microchip, protecting method for e.g. identification of object in industry, involves placing electronic component in chamber, covering component with resin, and drying resin |
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