JPS60134355A - System state displaying system - Google Patents
System state displaying systemInfo
- Publication number
- JPS60134355A JPS60134355A JP58239780A JP23978083A JPS60134355A JP S60134355 A JPS60134355 A JP S60134355A JP 58239780 A JP58239780 A JP 58239780A JP 23978083 A JP23978083 A JP 23978083A JP S60134355 A JPS60134355 A JP S60134355A
- Authority
- JP
- Japan
- Prior art keywords
- flop
- flip
- circuit
- failure
- system fault
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Exchange Systems With Centralized Control (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は緊急制御回路の起動要因を表示する方式に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a system for displaying activation factors of an emergency control circuit.
電子交換システム等は高度の実時間性か要求され、共通
制御装置は２重化されている。Electronic exchange systems and the like are required to have a high degree of real-time performance, and common control devices are duplicated.
通常の障害に対しては、すべてプログラム的な処理で障
害装置の識別とシステムからの切り離しが可能である。For normal failures, it is possible to identify the faulty device and disconnect it from the system through program-based processing.
しかしながらプログラム的な処理で障害装置のシステム
からの切り離しが不可能であるような障害の場合システ
ム全体の動作に重大な影響をおよぼす。このような場合
、金物によりシステム障害の検出からはじまって、プロ
グラム制御が可能なシステム構成ビ生み出す一通の緊急
制御動作（以下ＢＭＡと略す）が実行される。このよう
なシステム障害として、（１）障害検出タイマのオーバ
フロー（２） Ｃ０間のシステムモード不一致（３）プ
ロセッサモード不一致（４）クロック供給系の断等が対
象となるが従来技術では該システム障害の種別を切り分
ける手段がな（システムの保守性が悪い。以下４１１図
７用いて説明する。矛１図は従来技術の一例乞示し、１
はシステム障害Ａが検出されたとぎ、パルス性信号を作
成する微分回路、２はシステム障害Ｂが検出されたとぎ
、パルス往信号ｗ６成する微分回路、３はシステム障害
Ｃが検出されたとき、パルス性信号乞作成する微分回路
、４は微分回路１．２．３からのパルス性信号の論理和
ン取るオワ回路、５は各システム障害が発生したことを
保持するＥＩＶＩＡ中７リツプフロツプ、６はＢＭＡ中
７中ソリップフロップ５火したことで起動されるＥＭＡ
回路、７は中央制御装置１５に対する初期設定及びシス
テム再構成用の信号線、８はＢＮＡＮ表中７リツプフロ
ツプ５の初期設定用信号線である。However, in the case of a failure in which it is impossible to separate the failed device from the system through program processing, the operation of the entire system is seriously affected. In such a case, the hardware executes a series of emergency control operations (hereinafter abbreviated as BMA) starting from the detection of a system failure and creating a program-controllable system configuration. Such system failures include (1) an overflow of the failure detection timer, (2) a system mode mismatch between C0s, (3) a processor mode mismatch, and (4) a disconnection of the clock supply system. There is no means to distinguish between the types (system maintainability is poor.The explanation will be given below using Fig. 7. Fig. 1 shows an example of the prior art;
is a differentiating circuit that creates a pulsed signal when system failure A is detected, 2 is a differentiator circuit that creates a pulse outgoing signal w6 when system failure B is detected, and 3 is a differentiator circuit that creates a pulsed signal w6 when system failure C is detected. 4 is a differential circuit that generates pulsed signals; 4 is an OR circuit that takes the OR of the pulsed signals from the differentiating circuits 1, 2, and 3; 5 is a 7-lip flop in EIVIA that maintains that each system failure has occurred; 6 is a EMA triggered by 5 solip flops in 7 during BMA
7 is a signal line for initial setting and system reconfiguration for the central control unit 15, and 8 is a signal line for initial setting of the flip-flop 5 in the BNAN table.
ここで例えばシステム障害Ａが検出された場合、微分回
路１でパルス性信号化され、オワ回路４を経由しＥＮＡ
中フリフリップフロップ５火し、ＥＮＡ回路６′（１１
−起動する。ＥＮＡ回路６からの信号線７で中央制御装
置１５ン初期設定しかつシステム再構成を行い、この後
信号線８でＥＮＡ中フリフリップフロップ５期設定する
。For example, if a system failure A is detected, it is converted into a pulsed signal by the differentiating circuit 1 and sent to the ENA via the OVER circuit 4.
Inside flip-flop 5, ENA circuit 6' (11
-Start. A signal line 7 from the ENA circuit 6 is used to initialize the central control unit 15 and system reconfiguration, and then a signal line 8 is used to set the fifth stage of the ENA flip-flop.
尚システム障害Ａについて説明したが、システム障害Ｂ
、システム障害Ｃ１その他のシステム障害についても同
様に説明できる。Although we have explained system failure A, system failure B
, system failure C1 and other system failures can be similarly explained.
しかしながら、従来技術では、システム障害Ａ、Ｂ、Ｃ
，その他の障害の識別ができないため、障害箇所の検索
及び保全に多大の時間２要している。However, in the prior art, system failures A, B, and C
, and other failures cannot be identified, so it takes a lot of time to search for and maintain the failure location.
本発明の目的は、システム障−害Ａ、Ｂ、Ｃ。 The purpose of the present invention is to prevent system failures A, B, and C.
その他の障害の識別機能乞提供し、障害箇所の検索及び
保全における時間Ｙ低減することのできるシステム状態
表示方式を提供するにある。Another object of the present invention is to provide a system status display method that can provide the ability to identify other failures and reduce the time required to search and maintain failure locations.
このため、本発明では、システム障害毎にシステム障害
を保持するフリップ７０ツブと表示器を設け、ＥＮＡ回
路が起動されたときの障害原因を表示し、障害の識別を
可能とした。Therefore, in the present invention, a flip 70 tab for holding the system failure and a display are provided for each system failure to display the cause of the failure when the ENA circuit is activated, thereby making it possible to identify the failure.
本発明による実施例を第２図に示１−０第１図と重複す
る図の説明は省略する。９はシステムＨ害Ｃｙｘ保持す
るフリップフロップ、１０はシステム障害Ｂｉ保持する
フリップフロップ、１１はシステム障害Ａを保持するフ
リップ７０ツブ、１２はシステム障害Ｃの表示器、１３
はシステム障害Ｂの表示器、１４はシステム障害Ａの表
示器、１６は中央制御装置１５からの７リツプフロツプ
９゜１０、ｉｌのリセット信号線である。システム障害
Ａを例にあげ本発明を説明する。システム障害Ａが検出
された場合、微分回路１でパルス信号化され、フリップ
フロップ１１に保持され、表示器１４でシステム障害人
が表示される。フリップフロップ１１のリセットは中央
制御装置１５のソフト命令、又は電けん操作により発せ
られ、リセット信号線１６ｙＩｌ−介して行なわれる。An embodiment according to the present invention is shown in FIG. 2, and explanations of the same figures as those in FIG. 1 will be omitted. 9 is a flip-flop that holds the system fault Cyx; 10 is a flip-flop that holds the system fault Bi; 11 is a flip-flop that holds the system fault A; 12 is an indicator for the system fault C; 13
14 is a system fault B indicator; 14 is a system fault A indicator; 16 is a reset signal line for 7 lip-flops 9.10, il from the central control unit 15; The present invention will be explained using system failure A as an example. When a system failure A is detected, it is converted into a pulse signal by the differentiating circuit 1, held in the flip-flop 11, and the system failure person is displayed on the display 14. The reset of the flip-flop 11 is issued by a software command from the central controller 15 or by an electric power operation, and is carried out via the reset signal line 16yIl-.
尚オワ回路４ビ介しての動作は従来技術と同じである。Note that the operation via the O/W circuit 4B is the same as in the prior art.
システム障害Ｂ、Ｃ，その他の障害についても同様に説
明できる。System failures B, C, and other failures can be similarly explained.
以上の実施例で説明したように、本発明により、システ
ム障害が発生した場合のシステム障害の識別が可能とな
り、障害箇所の検索及び保全作業における時間を短縮で
き、システム信頼性の向上が計られる。As explained in the above embodiments, the present invention makes it possible to identify system failures when they occur, shorten the time required to search for failure locations and perform maintenance work, and improve system reliability. .
矛１図は従来のデータ処理装置Ｚ示す図、牙２図は本発
明によるシステム状態表示方式の１災施例ビ示す図であ
る。
１、２．３・・・微分回路 ４・・・オワ回路５．９〜
１１ ・・・フリップフロップ６・・・ＥＮＡ回路
７．８．１６ ・・・信号線
１２〜１４・・・表示器
１５・・・中央制御装置
代理人弁理士 高 橋 明 夫Figure 1 is a diagram showing a conventional data processing device Z, and Figure 2 is a diagram showing an example of a system status display method according to the present invention. 1, 2.3... Differential circuit 4... Owa circuit 5.9 ~
11...Flip-flop 6...ENA circuit 7.8.16...Signal lines 12-14...Display unit 15...Central control unit representative patent attorney Akio Takahashi
Claims (1)
検出し正常なプログラム処理が可能な金物構成を構築す
る回路を有するデータ処理装置において、該回路が起動
されたときの起動原因を保持１表示＼することＹ％徴と
するシステム状態表示方式。When a failure occurs that cannot be corrected by program processing, is the failure relevant?
In a data processing device having a circuit for constructing a hardware configuration capable of detection and normal program processing, a system status display method in which the cause of activation when the circuit is activated is held and displayed as a Y% sign.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58239780A JPS60134355A (en) | 1983-12-21 | 1983-12-21 | System state displaying system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58239780A JPS60134355A (en) | 1983-12-21 | 1983-12-21 | System state displaying system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60134355A true JPS60134355A (en) | 1985-07-17 |
Family
ID=17049778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58239780A Pending JPS60134355A (en) | 1983-12-21 | 1983-12-21 | System state displaying system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60134355A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57209553A (en) * | 1981-06-19 | 1982-12-22 | Nec Corp | Information processor |
| JPS58130661A (en) * | 1982-01-29 | 1983-08-04 | Fujitsu Ltd | Holding system of fault information |
-
1983
- 1983-12-21 JP JP58239780A patent/JPS60134355A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57209553A (en) * | 1981-06-19 | 1982-12-22 | Nec Corp | Information processor |
| JPS58130661A (en) * | 1982-01-29 | 1983-08-04 | Fujitsu Ltd | Holding system of fault information |
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