JPS6012827A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPS6012827A JPS6012827A JP58119672A JP11967283A JPS6012827A JP S6012827 A JPS6012827 A JP S6012827A JP 58119672 A JP58119672 A JP 58119672A JP 11967283 A JP11967283 A JP 11967283A JP S6012827 A JPS6012827 A JP S6012827A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- error signal
- level
- controlled oscillator
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008859 change Effects 0.000 claims abstract description 10
- 238000009499 grossing Methods 0.000 claims 1
- 230000010355 oscillation Effects 0.000 description 15
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 208000018583 New-onset refractory status epilepticus Diseases 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はＰＬＬ回路に係わシ、特に自走周波数を変更で
きる電圧制御発振器をＰＬＬループに設けたＰＬＬ回路
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL circuit, and more particularly to a PLL circuit in which a PLL loop is provided with a voltage controlled oscillator that can change the free running frequency.
従来のＰＬＬ回路は第１図に示すごとく、基準（ｉ号ｆ
、をＶＦＯ等の入力信号発生回路（図示してない〕から
端子ｌを介して入力される。基準信号ｆ、は位相比較器
３、ローパスフィルタ４、電圧制御発振器５を経由して
端子２から発振信号ｆ０として出力される。端子１から
入力される基準信号ｆｒの周波数変化中は電圧制御発振
器５の最低発振周波数と最高発振周波数によシ制限を受
ける。ロー・母スフィルタ４から電圧制御発振器５へ出
力される誤差信号Ｖｉが零のとき電圧制御発振器５は自
走周波数で発振する。基準信号ｆｒの周波数と自走周波
数との差が誤差信号Ｖｉのレベルを定める。電圧制御発
振器５から位相比較器３へ帰還されるフィードバック信
号ｆａ（゛第１図の例では発振信号ｆ。）と基準信号ｆ
ｒの周波数並びに位相が一致したときをロックされた状
態という。ＰＬＬ回路で取扱う周波数と基準信号ｆｒの
周波数範囲とを一致させたいときは前段に混合器（図示
してない）を設けて所望の周波数へ変換する。変換によ
シ基準信号ｆｒの周波数社化巾を拡大できない。As shown in Fig. 1, the conventional PLL circuit is based on the standard (i and f).
, is input from an input signal generation circuit (not shown) such as a VFO through terminal l. Reference signal f is input from terminal 2 via phase comparator 3, low-pass filter 4, and voltage-controlled oscillator 5. It is output as an oscillation signal f0.During the frequency change of the reference signal fr input from the terminal 1, it is limited by the lowest oscillation frequency and the highest oscillation frequency of the voltage controlled oscillator 5.The voltage is controlled from the low bus filter 4. When the error signal Vi output to the oscillator 5 is zero, the voltage controlled oscillator 5 oscillates at a free running frequency.The difference between the frequency of the reference signal fr and the free running frequency determines the level of the error signal Vi.Voltage controlled oscillator 5 The feedback signal fa (in the example of FIG. 1, the oscillation signal f) fed back to the phase comparator 3 and the reference signal f
When the frequency and phase of r match, it is called a locked state. If it is desired to match the frequency handled by the PLL circuit with the frequency range of the reference signal fr, a mixer (not shown) is provided at the front stage to convert the frequency to the desired frequency. The frequency range of the reference signal fr cannot be expanded by conversion.
第２図に示すように基準信号ｆ′を基準信号発生器（図
示してない〕で生成して端子ｌへ入力する適用方法もあ
る。この例では基準信号ｆ′ｒの周波数社変化しない。As shown in FIG. 2, there is also an application method in which the reference signal f' is generated by a reference signal generator (not shown) and inputted to the terminal l.In this example, the frequency of the reference signal f'r does not change.
電圧制御発振器５の自走周波数をプログラマブルカウン
タ７で分周したときのフィードバック信号ｆｄと基準信
−Ｑ ｆｌ、との周波数並びに位相が一致したとき誤差
信号ｖ１は零に近似する。When the free-running frequency of the voltage controlled oscillator 5 is divided by the programmable counter 7 and the frequency and phase of the feedback signal fd and the reference signal -Qfl match, the error signal v1 approximates zero.
分周比を変化させると変化に対応して誤差信号ｖｉのレ
ベルが変化する。プログラマブルカウンタ７の分周比を
定める分周比情報は分周比設定回路８で形成する。分周
比情報は通常バイナリモードで編成され、デコードする
ことによシ発振信号ｆ０の周波数を知ることができる。When the frequency division ratio is changed, the level of the error signal vi changes in accordance with the change. Frequency division ratio information for determining the frequency division ratio of the programmable counter 7 is formed by a frequency division ratio setting circuit 8. The frequency division ratio information is usually organized in a binary mode, and by decoding it, the frequency of the oscillation signal f0 can be found.
フィードバック信号ｆｄと基準信号ｆｌの周波数の差を
解消するにはローフ４スフイルタ４０時定数で決定され
る帰還ループ−逐時性に係わる追従時間が必要であシ、
この時間をロックアツプ時間という。当然のことである
が誤差イロ号Ｖｌのレベル範囲が増加するとロックアツ
プ時間＃′ｉ、ｔｒｄ加する。ＰＬＬ回路を組込む無線
通信機等のシステム全体の設計目標から見るとロックア
ツプ時間の長短は重要性の高いものである。ロックアツ
プ時間を短縮するには分周比設定回路８て生成された分
周比イメＩ報すなわち発＆佃号ｆ。の周波数情報を利用
して電圧制御発振器５の端子６の電圧ケラかじめ発振信
号ｆ０の周波数の誤差４８号Ｖｉに近似するレベルはで
グリセットする。In order to eliminate the frequency difference between the feedback signal fd and the reference signal fl, a follow-up time related to feedback loop-time-consecutiveness determined by the time constant of the loaf 4 filter 40 is required.
This time is called lock-up time. As a matter of course, when the level range of the error signal Vl increases, the lock-up time #'i, trd increases. From the viewpoint of the overall design goal of a system such as a wireless communication device incorporating a PLL circuit, the length of the lock-up time is highly important. In order to shorten the lock-up time, the frequency division ratio image signal generated by the frequency division ratio setting circuit 8, that is, the frequency division ratio image I, is used. Using the frequency information of the voltage control oscillator 5 at the terminal 6, the frequency error of the voltage vignetting pre-oscillation signal f0 is reset to a level approximating No. 48 Vi.
ＰＬＬ回路の他の設計目標にキャリヤ・ノイズ比（以下
、ｃ７ｒｑと記す〕がある、 ＰＬＬ回路の位相比較鈷
３、四−パスフィルタ４、電圧制御発振器５等の各部要
素および回路は各部の雑音指数、相互のかん渉、温度お
よび電源装動によるドリフト、動作特性等によ）取扱う
信号に対し付加的な雑音を発生ずる。特に電圧制御発振
器５では、自走周波数が誤差電圧ΔＴｖ’ｉによシロツ
クされるので発振信号ｆ。の変化周波数Δｆ０は非周期
性、非対称性をもつことになシいが悪化する傾向がある
。いを改善するには変化電圧Δｖ１に対する変化周波数
Δｆ０を少なく°すること、すなわち、電圧制御発振器
５の感度を下げればよい。電圧制御発振器５の感度を下
げると誤差信号Ｖ１と発振信号ｆ０の動作曲線が第３図
に示す６曲線から５曲線に変るので誤差信号ｖ１〜ｖ雰
の変化域に対し発振周波数変化域は発振周波数ｆ１〜ｆ
４からｆｓ＝ｆｓと狭くなる。発振周波数変化域は自走
周波数に依存しているから発振信号ｆ０の周波数に対応
して複数の自走周波数が設定できれば全体の発振周波数
範囲を保りたままいを改善できる。このため、第２図に
示す電圧制御発振器５に内蔵したりアクタンス素子を能
動とするため分周比設定回路８の端子Ａ１ｅＡ２・・・
をＸ、、Ｘ、・・・の結線を介して電圧制御発振器５へ
接続した回路が提案されている。この回路ではりアクタ
ンス素子を能動とすることによシ周波数イ′ＴＩ報に対
応した自走周波数を生成するようになっている。Another design goal of the PLL circuit is the carrier-to-noise ratio (hereinafter referred to as c7rq).Each component and circuit of the PLL circuit, such as the phase comparator 3, the four-pass filter 4, and the voltage controlled oscillator 5, has a noise reduction ratio of each part. (due to exponents, mutual interference, drift due to temperature and power supply, operating characteristics, etc.) that generate additional noise to the signals being handled. In particular, in the voltage controlled oscillator 5, the free running frequency is locked by the error voltage ΔTv'i, so that the oscillation signal f. Although the changing frequency Δf0 does not have non-periodicity or asymmetry, it tends to get worse. In order to improve this, it is sufficient to reduce the change frequency Δf0 with respect to the change voltage Δv1, that is, to lower the sensitivity of the voltage controlled oscillator 5. When the sensitivity of the voltage controlled oscillator 5 is lowered, the operating curves of the error signal V1 and the oscillation signal f0 change from the 6 curves shown in FIG. Frequency f1~f
4, it becomes narrower as fs=fs. Since the oscillation frequency change range depends on the free-running frequency, if a plurality of free-running frequencies can be set corresponding to the frequency of the oscillation signal f0, the overall oscillation frequency range can be maintained and improved. For this reason, terminals A1eA2, .
A circuit has been proposed in which the voltage-controlled oscillator 5 is connected to the voltage-controlled oscillator 5 through connections X, , X, . This circuit generates a free-running frequency corresponding to the frequency I'TI signal by activating the actance element.
上述したりアクタンスの接続にょシ自走周波数が変化す
る電圧制御発振器５を周波数情報で制御するには周波数
情報を形成する分周比設定回路８等の予想された周波数
情報が必要であシ周波数情報が得られない第１図の回路
では電圧制御発振器５を制御できない欠点を有している
。In order to control the voltage controlled oscillator 5 whose free-running frequency changes using frequency information, as described above and the actance connection, predicted frequency information such as the frequency division ratio setting circuit 8 that forms the frequency information is required. The circuit of FIG. 1 in which no information is obtained has the disadvantage that the voltage controlled oscillator 5 cannot be controlled.
本発明は上述した点にかんがみなされたもので、無線通
信機等のシステムに組込みＶＦＯ等の信号のスプリアス
を除去し、かつ、キャリヤ・ノイズ比を改善したＰＬＬ
回路を提供することを目的とする。The present invention has been made in consideration of the above-mentioned points, and is a PLL that is incorporated into a system such as a wireless communication device, removes spurious signals from VFO, etc., and improves the carrier-to-noise ratio.
The purpose is to provide circuits.
本発明にはりアクタンス素子を能動とすることによシ自
走周波数が変化する電圧制御発振器を設けである。また
、誤差信号が所定の範囲外のレベルとなりたことを判別
する誤差信号レベル範囲判別手段と、誤差信号が所定の
範囲外となったときりアクタンス素子を電圧制御発振器
へ接続する栴造となっている。The present invention provides a voltage controlled oscillator whose free running frequency changes by activating the actance element. Additionally, there is provided an error signal level range determining means for determining when the error signal has reached a level outside a predetermined range, and a circuit that connects the actance element to the voltage controlled oscillator when the error signal is outside the predetermined range. There is.
以下、本発明になるＰＬＬ回路の一実施例ｔ−第４図に
したがって説明する。An embodiment of the PLL circuit according to the present invention will be described below with reference to FIG.
第４図に示すごとく、本発明のＰＬＬ回路は電圧制御発
振器９、誤差信号レベル範囲判別器１２、リアクタンス
切換器１６を有し、電圧制御発振器９の出力側からＹ−
Ｙ’結紗を介して位相比較器３への帰還ルーノを形成す
る。As shown in FIG. 4, the PLL circuit of the present invention has a voltage controlled oscillator 9, an error signal level range discriminator 12, and a reactance switch 16.
A feedback loop to the phase comparator 3 is formed via the Y' wire.
誤差信号レベル範囲判別器１２は下限用コン・９レータ
１３、上限用コンパレータ１４および比較電圧１５で構
成されている。ローノやスフイルタ４の出力側は電圧制
御発振器９および誤差信号レベル範囲判別器１２の端子
９ａおよび１２ｃへそれぞれ接続されている。誤差信号
レベル範囲判別器１２の端子１２ ｃは下限用コンパレ
ータ１３の一方の入側並びに上限用コン・ぐレータ１４
の一方の入側へ接続されている。また、下限用コンａ４
＋／ −タ１３の他方の入側は比較電圧の端子１５ａ
と、上限用コンパレータ１４の他力の太細ｊは比較＋ｉ
ｊ、ｔＪ二の端子１５ｂと接続されている。下限用コン
・ぐレータ１３は一方の入側へ入力される誤差信号Ｖｌ
のレベルが比較電圧の端子１５ａから他方の入側へ印加
されている下限比較電圧のレベルよシ低いときは出側の
論理を″０ｍから′ｌ”へ変化する。上限用コン・臂レ
ータ１４は一方の入側へ入力される誤差信号Ｖｌのレベ
ルが比較電圧の端子１５ｂから他方の入側へ印加されて
いる上限比較電圧のレベルより高いときは出側の論理を
“０″からｌ″へ変化する。The error signal level range discriminator 12 is composed of a lower limit comparator 13, an upper limit comparator 14, and a comparison voltage 15. The output side of the filter 4 is connected to the voltage controlled oscillator 9 and the terminals 9a and 12c of the error signal level range discriminator 12, respectively. The terminal 12 c of the error signal level range discriminator 12 is connected to one input side of the lower limit comparator 13 and the upper limit comparator 14
is connected to one input side of the In addition, the lower limit controller A4
The other input side of the +/- terminal 13 is a comparison voltage terminal 15a.
And, the thickness j of the other force of the upper limit comparator 14 is compared +i
It is connected to the second terminal 15b of j and tJ. The lower limit converter 13 receives an error signal Vl input to one input side.
When the level of is lower than the level of the lower limit comparison voltage applied from the comparison voltage terminal 15a to the other input side, the logic on the output side changes from "0m" to "l". When the level of the error signal Vl inputted to one input side is higher than the level of the upper limit comparison voltage applied from the comparison voltage terminal 15b to the other input side, the upper limit controller/arm regulator 14 outputs the output logic. changes from "0" to l".
リアクタンス切換器１６はアンド回路１７と１８、パル
ス晩生回路１９およびアップダウンカウンタ２０で構成
されている。誤差信号レベル範囲判別器１２の端子１２
１Ｌとリアクタンス切換器１６の端子１６ａおよび端子
１２ｂと端子１６ｂとは接続され、更に、端子１６ａ並
びに端子１６ｂはそれぞれアンド回路ｔ７，１８の一方
の入側へ接続されている。また、アンド回路１７．１８
の他方の入側はノｅルス発生回路１９の出側と接続され
ている。誤差信号レベル範囲判別器１２の下限用コン・
ンレータ１３が能動となるとアンド回路１７′の一方の
入側がＨレベルとなシ・９ルス発生回路１９から出力さ
れるパルスをアップダウンカウンタ２０のＤ端子へ送出
する。下限用二ンノクレータ１３が非能動となるとａ４
ルスの送出を停止する。The reactance switch 16 is composed of AND circuits 17 and 18, a pulse late generation circuit 19, and an up/down counter 20. Terminal 12 of error signal level range discriminator 12
1L and the terminal 16a of the reactance switch 16, and the terminal 12b and the terminal 16b are connected, and furthermore, the terminal 16a and the terminal 16b are connected to one input side of AND circuits t7 and 18, respectively. Also, AND circuit 17.18
The other input side of is connected to the output side of the e-norse generating circuit 19. Lower limit controller for error signal level range discriminator 12
When the inverter 13 becomes active, one input side of the AND circuit 17' becomes H level, and the pulse output from the pulse generating circuit 19 is sent to the D terminal of the up/down counter 20. When the lower limit double crater 13 becomes inactive, a4
Stop sending out pulses.
上限用コンパレータ１４が能動となシアンド回路１８の
一方の入側がＨレベルとなるとパルス発生回路１９から
出力されるパルスを他方の入側を介してアップダウンカ
ウンタ２０のＵ端子へ送出する。アップダウンカウンタ
２０はＤ端子またはＵ端子へ入力されるノｆルスを計数
する。計数値に応じてリアクタンス切換器１６の端子Ｂ
１．Ｂ２・・・Ｂｎのいずれか１″：）をＨレベルに切
換える。なお、端子Ｂ１がＬＳＢ、端子ＢｎがＭＳＢで
あシ計数値零のときはすべての端子がＬレベルとなる。When the upper limit comparator 14 is active and one input side of the shand circuit 18 reaches H level, the pulse output from the pulse generation circuit 19 is sent to the U terminal of the up/down counter 20 via the other input side. The up/down counter 20 counts the pulse input to the D terminal or the U terminal. Terminal B of the reactance switch 16 according to the count value.
1. B2...Bn (1":) is switched to the H level. Note that when the terminal B1 is the LSB and the terminal Bn is the MSB and the count value is zero, all the terminals are set to the L level.
リアクタンス切換器１６の端子Ｂ１〜Ｂｎは電圧制御発
振器９の端子Ｐ１〜Ｐｎと接続されている。端子Ｐ！〜
ＰｎがＨレベルとなるとダイオードＤ！〜Ｄｎが導通し
コイルし１〜Ｌｎが能動となる。電圧制御発振器９の誤
差信号ｖ１と発振信号ｆ０の動作特性が第５図ｂｏ ％
ｂｎ曲線となるようコイルＬｏ−Ｌｎのインダクタン
スを定める。なお、第４図中、符号１１は電界効果トラ
ンジスタ、ｌＯは可変容量ダイオード、Ｃ１〜Ｃｎは高
周波用ノ４スコンである。Terminals B1 to Bn of the reactance switch 16 are connected to terminals P1 to Pn of the voltage controlled oscillator 9. Terminal P! ~
When Pn becomes H level, diode D! ~Dn becomes conductive and the coil becomes conductive, and 1~Ln becomes active. The operating characteristics of the error signal v1 and the oscillation signal f0 of the voltage controlled oscillator 9 are shown in FIG.
The inductance of the coil Lo-Ln is determined so as to form a bn curve. In FIG. 4, reference numeral 11 is a field effect transistor, lO is a variable capacitance diode, and C1 to Cn are high frequency nozzles.
ここで、基準信号ｆｒと発振信号ｆ０との周波数並びに
位相が一致し第５図に示す１１曲線上の誤差信号Ｖｉの
レベルｖ１〜ｖ２の間の１点でロックされていると誤差
信号レベル範囲判別器１２の下限用コン・９レータ１３
および上限用コンパレータ１４の出側の論理は共にθ′
となりておシ、リアクタンス切換器１６のアップダウン
カウンタ２０は端子Ｂ１はＨレベルに保持されている。Here, if the frequency and phase of the reference signal fr and the oscillation signal f0 match and are locked at one point between the levels v1 and v2 of the error signal Vi on the 11 curve shown in FIG. 5, the error signal level range Lower limit converter 13 of discriminator 12
and the output logic of the upper limit comparator 14 are both θ'
Therefore, the terminal B1 of the up/down counter 20 of the reactance switch 16 is held at H level.
ＶＦＯを操作しく図示してない）基準信号ｆｒの周波数
を増加させると誤差信号ｖ１はレーベルｖ２の方へ増加
する。誤差信号Ｖｌが更に増加してレベルｖ２よシ高く
なると上限用コンパレータ１４が能動となる。このため
、リアクタンス切換器１６のアンド回路１８が能動とな
シアツブダウンカウンタ２０のＵ端子へパルスが送出さ
れる。したがって、端子ｂ１はＬレベル、端子ｂ２がＨ
レベルとなる。端子ｂ２がＨレベルとなるとコイルＬ２
が能動となシ、動作特性はｂ１曲線よシ高い発振周波数
を取扱うｂ２曲線（図示は省略されている）に切換えら
れる。切換えによシミ圧制御発振器９の自走周波数は高
くなシレベルｖ２よシ高かった誤差−信号Ｖ１のレベル
はレベルｖ１の近傍へ移動する。このため、上限用コン
／ぐレータ１４は非能動となシ、アッグダウンカウンタ
２０は計数を中止し端子Ｂ２がＨレベルのままとなる。When the frequency of the reference signal fr (VFO operation not shown) is increased, the error signal v1 increases toward the label v2. When the error signal Vl further increases and becomes higher than the level v2, the upper limit comparator 14 becomes active. For this reason, a pulse is sent to the U terminal of the shear down counter 20 in which the AND circuit 18 of the reactance switch 16 is active. Therefore, terminal b1 is at L level and terminal b2 is at H level.
level. When terminal b2 becomes H level, coil L2
When becomes active, the operating characteristics are switched to the b2 curve (not shown) which handles an oscillation frequency higher than that of the b1 curve. Due to the switching, the free running frequency of the stain pressure control oscillator 9 becomes high, and the level of the error signal V1, which was higher than the level v2, moves to the vicinity of the level v1. Therefore, the upper limit converter 14 becomes inactive, the up-down counter 20 stops counting, and the terminal B2 remains at the H level.
−母ルス発生周期は上記遷移過程を保証するよう定めで
ある。切換後、誤差信号Ｖｌが引続きレベルＶ、よシ高
いときは、つきのａＪ？ルス周期によシ更に上位のコイ
ルＬ３〜Ｌｎへ切換えられる。なお、誤差信号ｖ１の下
限のレベル■１と上限のレベルｖ２に対するそれぞれの
す、曲線〜ｂｎ曲線の受持範囲を一方の受持範囲の上限
と他方の受持範囲の下限とが互いにオーバーラツプする
よう形成し、上限および下限における受持範囲を２Ｍ化
すれば上限および下限近傍における不規則動作が防止で
きる。- The mother russe generation cycle is determined to ensure the above transition process. After switching, if the error signal Vl continues to be higher than the level V, the aJ? The coils are switched to higher-order coils L3 to Ln according to the pulse cycle. Note that the upper limit of one of the lower limit of the error signal v1 and the lower limit of the other of the lower limit of the lower limit of the error signal v1 and the lower limit of the other curve overlap each other. If the support range at the upper and lower limits is set to 2M, irregular operations near the upper and lower limits can be prevented.
上記実施例ではアップダウンカウンタ２０を単一出力と
したが、パリナリモード等で複数出力となし複数のりア
クタンス素子を同時に能動とするよう形成してもよい。In the above embodiment, the up/down counter 20 has a single output, but it may be formed to have multiple outputs in a parallel mode or the like so that a plurality of actance elements are activated at the same time.
また、アップダウンカウンタ２０から出力される情報を
ＲＯＭ等を介して所望の形式の情報にデコードしてもよ
い。また、アップダウンカウンタ２０から出力される情
報をマイクロコンピュータ等で処理してもよい。Furthermore, the information output from the up/down counter 20 may be decoded into information in a desired format via a ROM or the like. Further, the information output from the up/down counter 20 may be processed by a microcomputer or the like.
また、帰還ループにプログラマブルカウンタ等の発振４
ｕ号の周波数をプログラムする手段−を設けてもよい。In addition, the oscillation 4 of a programmable counter etc. is added to the feedback loop.
Means for programming the frequency of number u may be provided.
本発明によるＰＬＬ回路は誤差信号がＰ１ｒ足の範囲外
のレベルとなったことを判別する誤差信号レベル範囲判
別手段と、判別に応じて電圧制御発振器の自走周波数を
他の自動周波数へ変更すべく電圧制御発振器へりアクタ
ンス素子を接続する接続手段と、を具備した構成としで
あるため、自走周波数を切換える情報を誤差信号から得
られる特長を有している。このため、ｖＦＯ等によシ基
準信号が変化するＰＬＬ回路に適用すれば誤差信号以外
の情報によシ切換情報を得る方法に比べて回路構成が簡
単となる効果がある。The PLL circuit according to the present invention includes an error signal level range determining means for determining when the error signal has reached a level outside the range of P1r, and a means for changing the free running frequency of the voltage controlled oscillator to another automatic frequency according to the determination. Since this configuration is equipped with connection means for connecting the actance element to the voltage controlled oscillator, it has the advantage that information for switching the free-running frequency can be obtained from the error signal. Therefore, if this method is applied to a PLL circuit in which the reference signal changes due to vFO or the like, the circuit configuration can be simplified compared to a method of obtaining switching information using information other than an error signal.
第１図および第２図は従来のＰＬＬ回路のブロック図、
第３図は電圧制御発振器の動作特性を示すグラフ、第４
図は本発明になるＰＬＬＮ路の一実施例を示す一部回路
図をふくむブロック図、第５図は第４図の電圧制御発振
器の動作特性を示すグラフである。図中符号１．２は端
子、３は位相比較器、４はロー２４スフイルタ、５，９
は電圧制御発振器、７はプログラマブルカウンタ、ｌＯ
は可変容量ダイオード、１１は電界効果トランジスタ、
１２は誤差信号レベル範囲判別器、１３は下限用コン／
平レータ、１４は上限用コンパレータ、１５は比較電圧
、１６はりアクタンス切換器、１７．１８はアンド回路
、１９はｔＪ？ルス発生回路、２０はアップダウンカウ
ンタ、Ｌ０〜Ｌｎはコイル、Ｃ１〜Ｃｎはパスコン、Ｄ
１〜Ｄｎはダイオードである。
特許出願人 八重洲無線株式会社
第 １ 図
第２図
第 ５ 図
ＶＩ Ｖ２1 and 2 are block diagrams of conventional PLL circuits,
Figure 3 is a graph showing the operating characteristics of a voltage controlled oscillator.
The figure is a block diagram including a partial circuit diagram showing an embodiment of the PLLN path according to the present invention, and FIG. 5 is a graph showing the operating characteristics of the voltage controlled oscillator of FIG. 4. In the figure, 1 and 2 are terminals, 3 is a phase comparator, 4 is a low 24 filter, 5, 9
is a voltage controlled oscillator, 7 is a programmable counter, lO
is a variable capacitance diode, 11 is a field effect transistor,
12 is an error signal level range discriminator, 13 is a lower limit controller/
14 is an upper limit comparator, 15 is a comparison voltage, 16 is an actance switch, 17.18 is an AND circuit, and 19 is tJ? 20 is an up/down counter, L0 to Ln are coils, C1 to Cn are bypass capacitors, D
1 to Dn are diodes. Patent applicant Yaesu Musen Co., Ltd. Figure 1 Figure 2 Figure 5 Figure VI V2
Claims (1)
電圧制御発振器と、上記電圧制御発振器の出力信号と基
準信号との位相差を検出する位相比較器と、位相比較器
の出力信号を平滑して誤差信号を生成し上記電圧制御発
振器へ出力するローパスフィルタと、を具備したＰＬＬ
回路において、上ｇｂ誤差侶号のレベルがＦＡ足の範囲
外のレベルとなったことを判別する誤差信号レベル範囲
判別手段と、上記誤差信号レベル範囲判別手段の判別に
応じて上記自走周波数を他の自走周波数へ変更すべく上
記リアクタンスを上記電圧制御発振器へ接続する接続手
段と、を具備し、上記電圧制御発振器の出力信号に係わ
る周波数に応じて上記自走周波数を変更するよう＃Ｉ成
したことを特徴とするＰＬＬ回路。1. A voltage controlled oscillator whose free running frequency changes due to the connection of a reactance, a phase comparator that detects the phase difference between the output signal of the voltage controlled oscillator and a reference signal, and an error by smoothing the output signal of the phase comparator. A PLL comprising a low pass filter that generates a signal and outputs it to the voltage controlled oscillator.
In the circuit, there is an error signal level range determining means for determining that the level of the upper gb error signal is outside the range of the FA foot, and the free running frequency is determined according to the determination by the error signal level range determining means. connecting means for connecting the reactance to the voltage controlled oscillator in order to change the free running frequency to another free running frequency; A PLL circuit characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119672A JPS6012827A (en) | 1983-07-01 | 1983-07-01 | Pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119672A JPS6012827A (en) | 1983-07-01 | 1983-07-01 | Pll circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6012827A true JPS6012827A (en) | 1985-01-23 |
| JPH0318774B2 JPH0318774B2 (en) | 1991-03-13 |
Family
ID=14767189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58119672A Granted JPS6012827A (en) | 1983-07-01 | 1983-07-01 | Pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6012827A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04183117A (en) * | 1990-11-19 | 1992-06-30 | Matsushita Electric Ind Co Ltd | Clock regenerating circuit |
| JPH04117693U (en) * | 1991-04-04 | 1992-10-21 | 株式会社サンライク | Puppet made of air-filled bodies |
| EP1514351A1 (en) * | 2002-06-10 | 2005-03-16 | GCT Semiconductor, Inc. | Lc oscillator with wide tuning range and low phase noise |
| US7902934B2 (en) | 2004-11-09 | 2011-03-08 | Renesas Electronics Corporation | Variable inductor, and oscillator and communication system using the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51150956A (en) * | 1975-06-20 | 1976-12-24 | Hitachi Ltd | Phase control oscillator |
| JPS5846729A (en) * | 1981-09-12 | 1983-03-18 | Japan Radio Co Ltd | Variable frequency oscillator capable of frequency band automatic tuning |
-
1983
- 1983-07-01 JP JP58119672A patent/JPS6012827A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51150956A (en) * | 1975-06-20 | 1976-12-24 | Hitachi Ltd | Phase control oscillator |
| JPS5846729A (en) * | 1981-09-12 | 1983-03-18 | Japan Radio Co Ltd | Variable frequency oscillator capable of frequency band automatic tuning |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04183117A (en) * | 1990-11-19 | 1992-06-30 | Matsushita Electric Ind Co Ltd | Clock regenerating circuit |
| JPH04117693U (en) * | 1991-04-04 | 1992-10-21 | 株式会社サンライク | Puppet made of air-filled bodies |
| EP1514351A1 (en) * | 2002-06-10 | 2005-03-16 | GCT Semiconductor, Inc. | Lc oscillator with wide tuning range and low phase noise |
| EP1514351A4 (en) * | 2002-06-10 | 2005-12-07 | Gct Semiconductor Inc | Lc oscillator with wide tuning range and low phase noise |
| US7902934B2 (en) | 2004-11-09 | 2011-03-08 | Renesas Electronics Corporation | Variable inductor, and oscillator and communication system using the same |
| US8502614B2 (en) | 2004-11-09 | 2013-08-06 | Renesas Electronics Corporation | Variable inductor, and oscillator and communication system using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0318774B2 (en) | 1991-03-13 |
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