JPS60100453A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPS60100453A JPS60100453A JP20772283A JP20772283A JPS60100453A JP S60100453 A JPS60100453 A JP S60100453A JP 20772283 A JP20772283 A JP 20772283A JP 20772283 A JP20772283 A JP 20772283A JP S60100453 A JPS60100453 A JP S60100453A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wirings
- substrate
- external terminal
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 239000010949 copper Substances 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000005476 soldering Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 8
- 239000010409 thin film Substances 0.000 description 5
- 238000007639 printing Methods 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 241000277269 Oncorhynchus masou Species 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置用パッケージに関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a package for a semiconductor device.
半導体装置用パッケージとしては、従来からセラミック
、金属、樹−脂などが用いられており、これらのうちで
セラミックを用いたパッケージは、その特長の１つとし
て外部端子ピンを平面上に縦横一定のピッチで配列する
ことができるために、多信号端子の要求されるＬＳＩな
どの実装に好適している。そしてこのセラミックを用い
たパッケージは、セラミックの薄板に厚膜印刷などによ
って必要な配線を形成させ、かつこれに穿孔して導電性
ペーストを充填させることにより薄板内にスルーホール
を構成させる手法が採用されている。Ceramics, metals, resins, etc. have traditionally been used as packages for semiconductor devices, and one of the features of packages using ceramics is that the external terminal pins can be arranged on a flat surface in a constant manner. Since they can be arranged at pitches, they are suitable for mounting LSIs that require multi-signal terminals. Packages using this ceramic employ a method in which the necessary wiring is formed on a thin ceramic plate by thick-film printing, and then through-holes are formed within the thin plate by drilling holes and filling them with conductive paste. has been done.
こ＼で従来例によるこの種の半導体装置用パッケージの
外観斜視図、およびそのＩＩ−ＩＩ線部の断面図を第１
図、および第２図に、またその製造説明のだめの分解断
面図を第３図に示しである。すなわち、まず第１図、お
よび第２図構成において、パッケージ基板１には半導体
チップを搭載するためのダイボンド面２．ワイヤボンド
用配線パッド３、パッケージ封止用蓋付けのだめのシー
ルリング４．および信号数シ出しのだめの外部端子ピン
５をそれぞれに設け、パッケージ内のグイボンド面２は
、その配線２ａおよびスルーホール２ｂを経て外部端子
ピン５ａに、また同様にワイヤボンド用配線パッド３は
、その配線３ａおよびスルーホール３ ｂ ｔ ３ ｃ
を経て外部端子ピン５ｂにそれぞれ接続させたものであ
る。Here, the external perspective view of this type of semiconductor device package according to the conventional example and the sectional view taken along the line II-II are shown in the first part.
2, and an exploded sectional view for explaining its manufacture is shown in FIG. 3. That is, first, in the configurations shown in FIGS. 1 and 2, the package substrate 1 has a die bonding surface 2.0 on which a semiconductor chip is mounted. Wire bond wiring pad 3, package sealing cap seal ring 4. and an external terminal pin 5 for outputting the number of signals, and the wire bond surface 2 in the package is connected to the external terminal pin 5a via the wiring 2a and through hole 2b, and similarly, the wire bond wiring pad 3 is connected to the external terminal pin 5a through the wiring 2a and through hole 2b. Its wiring 3a and through hole 3 b t 3 c
The external terminal pins 5b are connected to the external terminal pins 5b through the terminals.
さらに詳細には、第３図からも明らかなように、セラミ
ックからなるパツクージ基板１は、中央部に所定の開口
部を形成して、同開口部の上面周囲にシールリング４を
設けた第１層１ａと、同様に中央部に半導体チップの受
け入れ開口部を形成すると共に、上面の所定位置にワイ
ヤボンド用配線パッド３．これに連なる配線３ａ ｌお
よび同配腺３ａ端部から下面に貫通するスルーホール３
ｂを設けた第２層１ｂと、上面の所定位置にダイボンド
面２．こ九に連なる配線２ａ＋同配線２ａ端部から下面
に貫通するスルーホール２ｂ 、および同スルーホール
２ｂ下面のランド２Ｃを有し、それに前記スルーホール
３ｂに接するスルーホール３ｃ。More specifically, as is clear from FIG. 3, the package substrate 1 made of ceramic has a predetermined opening in the center and a seal ring 4 around the upper surface of the opening. Similarly, an opening for receiving a semiconductor chip is formed in the center of the layer 1a, and wiring pads 3 for wire bonding are formed at predetermined positions on the upper surface. The wiring 3a l connected to this and the through hole 3 penetrating from the end of the same wiring gland 3a to the lower surface
a second layer 1b provided with a die-bonding surface 2.b, and a die-bonding surface 2. A through hole 3c has a through hole 2b penetrating from the end of the interconnect 2a and the interconnect 2a to the lower surface, and a land 2C on the lower surface of the through hole 2b, and is in contact with the through hole 3b.
および同スルーホール３Ｃ下面のランド３ｄを設けた第
３層ＩＣとからなっておシ、これらの各層１”＋１ｂ７
ｉ（を接着焼成して一体化されたセラミックパッケージ
を構成させ、かつ各下面のランド２ｃｔ３ｄに外部端子
ピン５ａ、５ｂを半田などによシ接着させたものであシ
、前記ダイボンド面２およびワイヤボンド用配線パッド
３などの各配線部はモリブデン、タングステンなどの金
属粒子のペーストをスクリーン印刷などで印刷形成させ
るのである。and a third layer IC provided with a land 3d on the bottom surface of the through hole 3C, each of these layers 1"+1b7
(i) is bonded and fired to form an integrated ceramic package, and external terminal pins 5a, 5b are bonded to the lands 2ct3d on each lower surface by solder or the like, and the die bonding surface 2 and the wire Each wiring portion such as the bond wiring pad 3 is formed by printing a paste of metal particles such as molybdenum or tungsten by screen printing or the like.
従ってこのように形成される従来例によるセラミックパ
ッケージにおいては、セラミックの薄板に所定の穿孔、
スルーホールを打ち抜く工程、多層の配線バター／の印
刷工程、多数のセラミック薄板の積層接着とその焼成工
程などを必要とし、製造コストが高いばか多か、スルー
ホールの打ち抜き、スクリーン印刷配線のためにその配
線の微細化ができず、さらには配線がモリブデン、タン
グステンなどの金属粒子の焼結であるだめに配線抵抗が
高いなどの不都合を有するものであった。Therefore, in the conventional ceramic package formed in this way, predetermined perforations and
It requires the process of punching through holes, the printing process of multilayer wiring butter/printing, the lamination bonding of many ceramic thin plates and the firing process, etc., and the manufacturing cost is high. The wiring cannot be miniaturized, and furthermore, since the wiring is made of sintered metal particles such as molybdenum or tungsten, the wiring resistance is high.
この発明は従来のこのような欠点に鑑み、平板状をした
絶縁基板の表面に堆積した金属薄膜を整形して、ダイボ
ンド面およびワイヤボンド用配線パッドなどの配線を形
成させ、この配線の端部に外部端子ピンを基板表面に垂
直に接合させたものである。In view of these conventional drawbacks, the present invention shapes a metal thin film deposited on the surface of a flat insulating substrate to form wiring such as a die bonding surface and a wiring pad for wire bonding. The external terminal pins are connected perpendicularly to the board surface.
以下この発明に係る半導体装置用パッケージの一実施例
１１′ｉ：′）き、第４図および第５図を参照して詳細
に説明する。Hereinafter, an embodiment 11'i:') of a package for a semiconductor device according to the present invention will be described in detail with reference to FIGS. 4 and 5.
これらの第４図および第５図はこの実施例による半導体
装置用パッケージの外観斜視図、およびその■−■線部
の断面図を示しておシ、この実施例では、セラミック、
ガラスなどの平板状をした絶縁基板６を用い、この絶縁
基板６の一方の表面に、銅、アルミニュームなどを主体
とする電気抵抗の低い金属薄膜を、蒸着、スパッタなど
によシ堆積させた上で”、これを写真蝕刻などによジノ
＜ターニング整形することにより、ダイボンド面１と、
ワイヤボンド用配線パッドから延びる配線８などの、半
導体チップの搭載に必要な各配線を形成さぜると共に、
これらの配線８の端部、つまシ外部取シ出し用端部に外
部端子ピン９を、半田などで絶縁基板６を貫通させるこ
と汝しに、同基板表面に垂直に接続接合させたものであ
る。These FIGS. 4 and 5 show an external perspective view of the package for a semiconductor device according to this embodiment, and a sectional view taken along the line ■-■.
A flat insulating substrate 6 made of glass or the like is used, and on one surface of this insulating substrate 6, a thin metal film with low electrical resistance mainly made of copper, aluminum, etc. is deposited by vapor deposition, sputtering, etc. On the top of the die bond surface 1, the die bond surface 1 and
In addition to forming each wiring necessary for mounting the semiconductor chip, such as the wiring 8 extending from the wiring pad for wire bonding,
External terminal pins 9 are connected to the ends of these wirings 8, the ends for taking out the outside of the tab, and are connected perpendicularly to the surface of the board by soldering or the like to penetrate the insulating board 6. be.
また前記実施例構成において、絶縁基板６上へのダイボ
ンド面７および配線８は、前記したように、電気抵抗の
低い金属薄膜を蒸着、スパッタなどによシ基板６の全面
に一旦堆積させるが、このとき基板と金属薄膜との密着
性を強化させるために、同基板６上には予めクロム、チ
タンなどの酸化性の強い金属を薄く形成させておくのが
よく、かつ才た同金属薄膜は複数層による多層構造であ
ってもよい。そしてこのようにして得た金属薄膜は写真
製版手法によシ配線その他に必要な部分をマスキングし
た上で、余分な部分をエッヂング除去することによって
、電気抵抗の小さい、しかも微細化された配線を形成で
きるのである。Furthermore, in the configuration of the above embodiment, the die bonding surface 7 and the wiring 8 on the insulating substrate 6 are formed by depositing a metal thin film with low electrical resistance on the entire surface of the substrate 6 by vapor deposition, sputtering, etc., as described above. At this time, in order to strengthen the adhesion between the substrate and the metal thin film, it is recommended to form a thin layer of highly oxidizing metal such as chromium or titanium on the substrate 6 in advance. A multilayer structure including multiple layers may be used. The metal thin film obtained in this way is then masked by photolithography to mask wiring and other necessary parts, and the excess parts are removed by etching to create finer wiring with low electrical resistance. It can be formed.
以上詳述したようにこの発明によれば、平板状をした絶
縁基板を設け、この絶縁基板の一方の表面ＫＮ電気抵抗
低い金属薄膜を蒸着、スパッタなどで堆積させ、かつこ
の金属ＲＭを写真蝕刻などによりパターニング整形させ
て、グイボンド面およびワイヤボンド用配線パッドなど
の、半導体チップの搭載に必要な各配線を形成させ、各
配線の外部取シ出し用端部に外部端子ピンを、基板を貝
通させることなしに同基板表面に半田などで垂直に接続
接合させて、目的とするパッケージを構成させたから、
電気抵抗が小さくて微細化された配線を、極めて単純な
プロセスで容易かつ安価に形成でき、しかも絶縁基板に
はスルーホールなどを穿孔する必要が全くなくて構成自
体を簡単にし得るほか、場合によっては絶縁被覆板とか
ホーロー基板などの内部が導体製の基板をも使用できる
などの特長を有するものである。As described in detail above, according to the present invention, a flat insulating substrate is provided, a metal thin film with low electrical resistance KN is deposited on one surface of the insulating substrate by vapor deposition, sputtering, etc., and this metal RM is photo-etched. The wiring necessary for mounting the semiconductor chip, such as the wire bonding surface and wiring pad for wire bonding, is formed by patterning, etc., and external terminal pins are attached to the ends of each wiring for external extraction. By connecting and bonding vertically to the surface of the same board with solder etc. without passing it through, the desired package was constructed.
Miniaturized wiring with low electrical resistance can be formed easily and inexpensively using an extremely simple process, and there is no need to drill through holes in the insulating substrate, which simplifies the configuration itself. This has the advantage that it can also use substrates whose interior is made of a conductor, such as an insulating coating plate or a hollow substrate.
第１図は従来例による半導体装置用パッケージの概要を
示す外観斜視図、第２図は第１図１ｔ−１線部の断面図
、第３図は同上分解断面図、第４図はこの発明の一実施
例による半導体装量用パッケージの概要を示す外観斜視
図、第５図は第４図■−Ｖ線部の断面図である。
６・・・・絶縁基板、７・・赤−ダイボンド面、８・・
・・配線、９・・・・外部端子ピン。
代理人 大 岩 増 地
第１図
Ｆ′５２ 図
第３ 図
第４図
只
第５図FIG. 1 is an external perspective view showing an outline of a conventional semiconductor device package, FIG. 2 is a sectional view taken along line 1t-1 in FIG. 1, FIG. 3 is an exploded sectional view of the same, and FIG. 4 is the invention FIG. 5 is a sectional view taken along the line 2--V in FIG. 4. FIG. 6... Insulating substrate, 7... Red-die bonding surface, 8...
...Wiring, 9...External terminal pin. Agent Masu Oiwa Figure 1 F'52 Figure 3 Figure 4 Figure 5
Claims (1)
面に蒸着、スパッタなどで堆積させた電気抵抗の低い金
属薄膜を、写真蝕刻などにより／（ターニング整形させ
てダイボンド面およびワイヤボンド用配線パッドなどの
、半導体チップの搭載に必要な各配線を形成させると共
に、各配線の外部数シ出し用端部のそれぞれに外部端子
ピンを、半田などで基板を貫通させずに同基板表面に垂
直に接続接合させたことを特徴とする半導体装置用パッ
ケージ。Using a flat insulating substrate, a thin metal film with low electrical resistance is deposited on one surface of the insulating substrate by vapor deposition, sputtering, etc., and is then shaped by photolithography (turning) to form the die bond surface and wire bond wiring. In addition to forming each wiring necessary for mounting a semiconductor chip such as a pad, external terminal pins are attached to each end of each wiring for external wiring perpendicular to the surface of the board without penetrating the board with solder etc. A semiconductor device package characterized by being connected and bonded to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20772283A JPS60100453A (en) | 1983-11-05 | 1983-11-05 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20772283A JPS60100453A (en) | 1983-11-05 | 1983-11-05 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60100453A true JPS60100453A (en) | 1985-06-04 |
Family
ID=16544461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20772283A Pending JPS60100453A (en) | 1983-11-05 | 1983-11-05 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60100453A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2617335A1 (en) * | 1987-05-26 | 1988-12-30 | Matsushita Electric Works Ltd | CERAMIC CONNECTION SUBSTRATE PROVIDED WITH CONNECTION PROTUBERANCES TO THE INTEGRATED CIRCUIT PELLET |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126951A (en) * | 1980-03-12 | 1981-10-05 | Hitachi Ltd | Semicondutor device |
-
1983
- 1983-11-05 JP JP20772283A patent/JPS60100453A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126951A (en) * | 1980-03-12 | 1981-10-05 | Hitachi Ltd | Semicondutor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2617335A1 (en) * | 1987-05-26 | 1988-12-30 | Matsushita Electric Works Ltd | CERAMIC CONNECTION SUBSTRATE PROVIDED WITH CONNECTION PROTUBERANCES TO THE INTEGRATED CIRCUIT PELLET |
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