JPS5997230A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5997230A
JPS5997230A JP57205956A JP20595682A JPS5997230A JP S5997230 A JPS5997230 A JP S5997230A JP 57205956 A JP57205956 A JP 57205956A JP 20595682 A JP20595682 A JP 20595682A JP S5997230 A JPS5997230 A JP S5997230A
Authority
JP
Japan
Prior art keywords
inverter
mos
stages
inverters
invs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57205956A
Other languages
Japanese (ja)
Inventor
Norimitsu Uematsu
植松　紀光
Taku Kawahara
卓 河原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP57205956A priority Critical patent/JPS5997230A/en
Publication of JPS5997230A publication Critical patent/JPS5997230A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate the difference of signal propagation time between inverter rows, by equalizing sums of products between output resistances of MOS inverters in preceding stages and input capacities of MOS inverters in succeeding stages in respective inverter rows. CONSTITUTION:MOS inverters INVs C1-C4 and D1-D3 are connected successively in the first and the second inverter rows, respectively. INVs C1 and D1 in the first stages of both INV rows are connected to a common input terminal, and INVs C4 and D3 in the last stages are connected to output terminals Cout and Dout, respectively. The first INVs of the same structure are used as INVs C1-C4, D1, and D3. The second INV where the gate length of a constituting FET is 3/2 times as long as that of the FET constituting the first INV is used as the INVD2. By this constitution, sums of products between output resistances of INVs in preceding stages and input capacities of INVs in succeeding stages are equalized in respective INV rows.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、信号入力端子を共通にし、入力信号と同相の
波形を出力する第１のインバータ列と入力信号と逆相の
波形を出力する第２のインバータ列とを有し、各インバ
ータにＭＯ３電界効果トランクスタ即ちＭＯＳＦＥＴで
構成したＭＯＳインバータを使用した半導体集積回路に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention has a first inverter array that shares a signal input terminal and outputs a waveform that is in phase with the input signal, and a second inverter array that outputs a waveform that is in opposite phase to the input signal. The present invention relates to a semiconductor integrated circuit having a row of inverters, each inverter using a MOS inverter constituted by an MO3 field effect trunk transistor, that is, a MOSFET.

従来例の構成とその問題点 共通の信号入力端子を有し、入力信号と同相の波形を出
力する第１のインパーク列および入力信号と逆相の波形
を出力する第２のインバータ列とを有する回路は、通常
第１図に示すように構成されていて、インバータＸ１、
Ｘ２、Ｘ３、Ｘ４およびＹ】、Ｙ２、Ｙ３がそれぞれ縦
続接続されて第１および第２のインバータ列が構成され
、各々の初段のインバータＸ１およびＹｌがそれぞれ共
通の入力端子に接続されている。そして、両インバータ
列の最後段のインバータＸ４およびＹ３がそれぞれ出力
端子ＸｏｕｔおよびＹｏｕｔに接続されていて、偶数段
のインバータを有する第１のインバータ列の出力端子Ｘ
。ｕｔからは入力信号と同相の波形が出力され、奇数段
のインバータを有する第２のイン・ぐ−夕刊の出力端子
Ｙｏｕｔからは入力信号と逆相の波形が出力される。The structure of the conventional example and its problems A first imper array that has a common signal input terminal and outputs a waveform that is in phase with the input signal, and a second inverter array that outputs a waveform that is in opposite phase to the input signal. The circuit is usually configured as shown in FIG. 1, and includes an inverter X1,
X2, X3, X4, and Y], Y2, and Y3 are connected in cascade to form first and second inverter columns, and the first-stage inverters X1 and Yl are respectively connected to a common input terminal. Inverters X4 and Y3 at the last stage of both inverter rows are connected to the output terminals Xout and Yout, respectively, and the output terminal X of the first inverter row having an even number of stages of inverters
. A waveform in phase with the input signal is output from ut, and a waveform in phase with the input signal is output from the second output terminal Yout having an odd number of stages of inverters.

従来、この回路にＭＯＳＦＥＴを用いて第２図に示すよ
うな半導体集積回路が構成されていた。第２図において
、各インバータＸ１１Ｘ２、Ｘ３、Ｘ４、Ｙｌ、Ｙ２お
よびＹ３には、ＰチャンネルＭＯ８ＦＥＴおよびＮチャ
ンネルＭＯ８ＦＥＴの相補形のＭＯＳＦＥＴ　、即ちＣ
ＭＯ８によシ構成され、各々同一特性を有するＭＯＳイ
ンパークＡＩ　、Ａ２　、Ａ３　、Ａ４　Ｎ　　Ｂｌ　
　、Ｂ２およびＢ３がそれぞれ使用されている。ここで
、通常この種の回路は第１および第２のインバータ列の
それぞれのインバータの段数に奇数段の差を有するので
、縦続接続された各インバータ間の、前段のインバータ
の出力抵抗と後段のインバータの入力容量との積のイン
バータ列ごとの総和によって決定される信号伝搬時間が
、第１のインバータ列と第２のインバータ列とでは相異
が生じる。Conventionally, a semiconductor integrated circuit as shown in FIG. 2 has been constructed using MOSFETs in this circuit. In FIG. 2, each inverter X11X2, X3,
MOS Impark AI, A2, A3, A4 N Bl composed of MO8 and each having the same characteristics
, B2 and B3 are used, respectively. Here, since this type of circuit normally has an odd number of stages difference between the number of inverter stages in each of the first and second inverter rows, the output resistance of the preceding stage inverter and the succeeding stage's The signal propagation time determined by the sum of the product with the input capacitance of the inverter for each inverter row differs between the first inverter row and the second inverter row.

従って、ＭＯＳインバータＡｉ　、Ａ２　、Ａ３および
Ａ４からなる第１のインバータ列と、ＭＯＳインバータ
Ｂ１、Ｂ２およびＢ３からなる第２のインバータ列とに
おいて、各々のインバータの段数差によシ、両インバー
タ列の出力端子ＡｏｕｔおよびＢ。ｕｔ間で信号伝搬時
間の差に起因する出力信号の遅れが生じる等の欠点があ
った。Therefore, in the first inverter row consisting of MOS inverters Ai, A2, A3, and A4 and the second inverter row consisting of MOS inverters B1, B2, and B3, depending on the difference in the number of stages of each inverter, both inverter rows output terminals Aout and B of. There were drawbacks such as a delay in the output signal due to a difference in signal propagation time between the UTs.

発明の目的 本発明は、上記従来例の欠点に鑑みてなされたもので、
両インバータ列間のインバータの段数差によって生じる
信号伝搬時間の差を無くしだ半導体集積回路を提供する
ものである。Purpose of the Invention The present invention has been made in view of the drawbacks of the above-mentioned conventional examples.
The present invention provides a semiconductor integrated circuit that eliminates the difference in signal propagation time caused by the difference in the number of inverter stages between both inverter rows.

発明の構成 上記目的を達成するために、本発明は第１および第２の
インバータ列において、各段間における前段のＭＯＳイ
ンバータの出力抵抗と後段のＭＯＳインパークの入力容
量との積の各インバータ列ごとの総和が、第１のインバ
ータ列と第２のインバータ列とで相等しくなるように、
各段のＭＯＳインバータを構成したものである。Structure of the Invention In order to achieve the above object, the present invention provides, in the first and second inverter rows, the product of the output resistance of the preceding MOS inverter and the input capacitance of the succeeding MOS inverter between each stage. So that the total sum for each column is equal between the first inverter column and the second inverter column,
This is a configuration of MOS inverters at each stage.

実施例の説明 以下、図面によシ本発明の実施例を詳細に説明する。第
３図は、本発明の一実施例の回路を示す図である。第３
図において、第１および第２のインバータ列は、各々同
一特性のＰチャンネルＭＯ８ＦＥＴおよびＮチャンネル
ＭＯ８ＦＥＴからなるＣＭＯ８で構成されたＭＯＳイン
バータＣ１１Ｃ２、Ｃ３、Ｃ４およびＤｌ、Ｂ２、Ｂ３
がそれぞれ縦続的に接続されていて、両インバータ列の
各初段のＭＯＳインバータＣ１およびＤＩがそれぞれ共
通の入力端子に接続され、両インバータ列の各最後段の
ＭＯＳインバータＣ４およびＢ３がそれぞれ出力端子Ｃ
３ｕｔおよびり。ｕｔにそれぞれ接続されている。この
時、ＭＯＳインバータＣ１、Ｃ２＼　Ｃ３＼Ｃ。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 3 is a diagram showing a circuit according to an embodiment of the present invention. Third
In the figure, the first and second inverter rows are MOS inverters C11C2, C3, C4, and Dl, B2, B3 each composed of CMO8s consisting of a P-channel MO8FET and an N-channel MO8FET with the same characteristics.
are connected in series, the first-stage MOS inverters C1 and DI of both inverter rows are connected to a common input terminal, and the last-stage MOS inverters C4 and B3 of both inverter rows are connected to an output terminal C, respectively.
3ut and bird. ut, respectively. At this time, MOS inverters C1, C2\C3\C.

ＤｌおよびＢ３は、それぞれ同一構造の第１のＭＯＳイ
ンバータが使用されている。またＭＯＳインパークＢ２
は、それを構成するＭＯＳＦＥＴのダート長が、第１の
ＭＯＳインバータを構成するＭＯ８ＦＥＴＯケ９−ト長
の３／２倍の長さを有する第２のＭＯＳインパークが使
用されていて、第１のＭＯＳインバー１と比較して入力
容量および出力抵抗がそれぞれ３／２倍の値を有してい
る。ここで、ＰチャンネルＭＯ８ＦＥＴおよびＮチャン
ネルＭＯ８ＦＥＴの個々のオン抵抗および形状をそれぞ
れ等しく設計した場合、ＭＯＳインバータＣ１の出力抵
抗とＭＯＳインバータＣ２の入力容量との積をτとする
と、第１のインバータ列の各インバータＣ１、Ｃ２、Ｃ
３およびＣ４間でその積τはそれぞれ等しく、第１のイ
ンバータ列における総和は３τとなる。一方、第２のイ
ンバータ列において、ＭＯＳイン・ぐ−タＤ１の出力抵
抗とＭＯＳインバータＢ２の入力容量との積ＭＯＳイン
バータＢ３の入力容量との積は丁τとなリ、その総和は
３τとなって第１のインバータ列と等しくなる。従って
、第１列のインバータ列と第２のインバータ列とで、両
者の信号伝搬時間の差が生じなくなる。First MOS inverters having the same structure are used for D1 and B3. Also MOS Impark B2
In this case, a second MOS impark is used in which the dart length of the MOSFET constituting it is 3/2 times as long as the MO8FETO gate length constituting the first MOS inverter. The input capacitance and output resistance each have 3/2 times the value of the MOS Inverter 1. Here, if the individual on-resistances and shapes of the P-channel MO8FET and the N-channel MO8FET are designed to be equal, and if the product of the output resistance of the MOS inverter C1 and the input capacitance of the MOS inverter C2 is τ, then the first inverter string Each inverter C1, C2, C
The products τ are equal between 3 and C4, and the total sum in the first inverter row is 3τ. On the other hand, in the second inverter row, the product of the output resistance of MOS inverter D1 and the input capacitance of MOS inverter B2, and the product of the input capacitance of MOS inverter B3, is equal to τ, and the total sum is 3τ. Therefore, it becomes equal to the first inverter row. Therefore, there is no difference in signal propagation time between the first inverter row and the second inverter row.

また、本発明は、各インバータ列のインバータの段数を
増やして構成することもでき、その場合、第１のインバ
ータ列は、３ｎ＋ｍ（ｍ、ｎは自然数）段の第１のＭＯ
Ｓインパークを縦続接続し、第２のインバータ列は、ｍ
−１−ｎ段の第１のＭＯＳインバータおよびｎ段の第２
のＭＯＳインバータを、第１のＭＯＳインバータを初段
としてｎ段の第２のＭＯＳインバータを第１のＭＯＳイ
ンバータでそれぞれ挾むように縦続接続して構成すれば
よく、その際、各インバータ列の出力信号の位相は各々
のインバータの段数によって決定される。Further, the present invention can also be configured by increasing the number of inverter stages in each inverter row, in which case the first inverter row has a first MO of 3n+m (m, n is a natural number) stages.
S in parks are connected in cascade, and the second inverter row is m
-1-n stage first MOS inverter and n stage second MOS inverter
MOS inverters may be configured by cascade-connecting the first MOS inverter as the first stage and the n-stage second MOS inverters sandwiched between the first MOS inverters. The phase is determined by the number of stages of each inverter.

発明の詳細 な説明したように、本発明は、入力信号と同相の波形を
出力するイン・ぐ−夕刊と、入力信号と逆相の波形を出
力するインバータ列との信号伝搬時間を等しくすること
ができ、ロノック回路に用いて高速性能の向上を図るこ
とができる。As described in detail, the present invention is to equalize the signal propagation time of an inverter array that outputs a waveform that is in phase with the input signal and an inverter array that outputs a waveform that is opposite in phase to the input signal. It can be used in Ronok circuits to improve high-speed performance.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、共通の信号入力端子を有し、入力信号と同相
および逆相の波形をそれぞれ出力する回路の一般的なブ
ロック図、第２図は、第１図の回路をＭＯＳインバータ
を用いて構成した従来例の回路図、第３図は、本発明の
一実施例の回路図である。 ＡＩ　％　Ａ２　ｘ　Ａ３　ＸＡ４＼　Ｂ１）Ｂ２＼　
Ｂ３％ＣｌＸＣ２＼Ｃ３＼　Ｃ４１ＤＩ　％　Ｄ２　Ｘ
Ｄ３　°°・ＭＯＳインバータ。 第１図 第２図 ｓｓ ｉ　　　　　　第３図Figure 1 is a general block diagram of a circuit that has a common signal input terminal and outputs waveforms in-phase and anti-phase with the input signal, respectively. Figure 2 shows the circuit in Figure 1 using a MOS inverter. FIG. 3 is a circuit diagram of an embodiment of the present invention. AI % A2 x A3 XA4\ B1) B2\
B3%ClXC2\C3\C41DI % D2 X
D3 °°・MOS inverter. Figure 1 Figure 2 ss i Figure 3

Claims (3)

【特許請求の範囲】[Claims] （１）　　ＭＯＳインパークを偶数段縦続的に接続した
第］のインパーク列と、ＭＯＳインバータを奇数段縦続
的に接続した第２のインバータ列とを有し、各段間にお
ける前段のＭＯＳインバータの出力抵抗と後段のＭＯＳ
インバータの入力容量との積を前記のインバータ列と前
記第２のインバータ列とで相等しくなるように前記各段
のＭＯＳインバータを構成したことを特徴とする半導体
集積回路。(1) It has a first inverter row in which an even number of MOS inverters are connected in series, and a second inverter row in which an odd number of MOS inverters are connected in series, and the previous stage MOS inverter between each stage. output resistance and subsequent MOS
A semiconductor integrated circuit characterized in that the MOS inverters in each stage are configured so that the product of the inverter input capacitance is equal between the inverter row and the second inverter row. （２）前記第１のインバータ列は、３ｎ＋ｍ（ｍ。 ｎは耐然数）段の第１のＭＯＳインバータを縦続接続し
、前記第２のインバータ列は、ｍ＋１段の前記第１のＭ
ＯＳインバータおよびｎ段の第２のＭＯＳインバータを
、前記第１のＭＯＳインバータを初段として前記第２の
ＭＯＳインバータを前記第１のＭＯＳインパークで挾む
ように縦続接続したことを特徴とする特許請求の範囲第
（１）項記載の半導体集積回路。(2) The first inverter row has 3n+m (m. n is a natural number) stages of first MOS inverters connected in cascade, and the second inverter row has m+1 stages of the first MMOS inverters connected in cascade.
An OS inverter and n stages of second MOS inverters are connected in cascade such that the first MOS inverter is the first stage and the second MOS inverter is sandwiched between the first MOS inverters. A semiconductor integrated circuit according to scope (1). （３）前記第２のＭＯＳインバータは、それを構成する
ＭＯＳＦＥＴが前記第１のＭＯＳインバータを構成する
ＭＯＳＦＥＴのｒ−ト長の３／２倍のタート長を有する
ことを特徴とする特許請求の範囲第（２）項記載の半導
体集積回路。(3) The second MOS inverter is characterized in that the MOSFETs constituting it have a tart length that is 3/2 times the length of the MOSFETs constituting the first MOS inverter. A semiconductor integrated circuit according to scope (2).
JP57205956A 1982-11-26 1982-11-26 Semiconductor integrated circuit Pending JPS5997230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57205956A JPS5997230A (en) 1982-11-26 1982-11-26 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57205956A JPS5997230A (en) 1982-11-26 1982-11-26 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5997230A true JPS5997230A (en) 1984-06-05

Family

ID=16515481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57205956A Pending JPS5997230A (en) 1982-11-26 1982-11-26 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5997230A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0583881A1 (en) * 1992-08-07 1994-02-23 Lsi Logic Corporation CMOS differential driver circuit for high offset ground
WO2004001971A1 (en) * 2002-06-20 2003-12-31 Infineon Technologies Ag Logic circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0583881A1 (en) * 1992-08-07 1994-02-23 Lsi Logic Corporation CMOS differential driver circuit for high offset ground
WO2004001971A1 (en) * 2002-06-20 2003-12-31 Infineon Technologies Ag Logic circuit
US7132858B2 (en) 2002-06-20 2006-11-07 Infineon Technologies Ag Logic circuit

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