JPS5987698A - Shift register - Google Patents

Shift register

Info

Publication number
JPS5987698A
JPS5987698A JP57197108A JP19710882A JPS5987698A JP S5987698 A JPS5987698 A JP S5987698A JP 57197108 A JP57197108 A JP 57197108A JP 19710882 A JP19710882 A JP 19710882A JP S5987698 A JPS5987698 A JP S5987698A
Authority
JP
Japan
Prior art keywords
signal
mos
controlled
mos fet
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57197108A
Other languages
Japanese (ja)
Other versions
JPS6236314B2 (en
Inventor
Hideji Koike
秀治 小池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57197108A priority Critical patent/JPS5987698A/en
Publication of JPS5987698A publication Critical patent/JPS5987698A/en
Publication of JPS6236314B2 publication Critical patent/JPS6236314B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers

Landscapes

  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To obtain a shift register of small pattern area and quick signal transfer time by constituting a self latch circuit by connecting an N channel enhancement type MOS FET which is conducted and controlled by inversion signal of controlling signal between connection point of the MOS FET and signal input terminal. CONSTITUTION:The fifth MOS FETQ5 of enhancement type and P channel type conducted and controlled by a controlling signal phi is connected between the connection point of the first and second MOS FET Q1, Q2 and an output terminal A2 (input terminal of next stage). At the same time, the sixth MOS FET Q6 of enhancement type and N channel type conducted and controlled by an inversion signal phi is connected between the connection point of the third and fourth MOS FET Q3, Q4 and an output terminal A2 to constitute a self latch circuit. The self latch circuit is cascade connected to constitute a shift register having state holding function for each transfer gate. By this constitution, the circuit performs transfer and holding of signals efficiently. The number of elements is smaller (about 3/4) than conventional circuit. As configuration is relatively simple, the area can be made small.

Description

【発明の詳細な説明】 １１発明の技術分野〕 この発明は、ＣＭＯ８論理回路に係り、特にスタティッ
ク形のシフトレジスタに関する。DETAILED DESCRIPTION OF THE INVENTION 11. Technical Field of the Invention The present invention relates to a CMO8 logic circuit, and particularly to a static type shift register.

〔発明の技術的背景〕[Technical background of the invention]

従来、スタティック形のシストレジスタは第１図に示す
ように構成されている。図において、１１１〜１１４は
信号線上に縦続接続されたｌ・ランスファゲート、１２
１〜１２４ｕインバ一タ回路、φ、５Ｉｌ−Ｌ制御信号
、ＩＮは入力信号、Ａ、−Ａ３は信号入力端であり、例
えば２個のトランスファゲート１１＋＋１１２　と２個
のインバータ回路１２ｔ＋Ｊ２２　とで１つのラッチ回
路が構成される。上記のような構成において、制御信号
（クロック信号）φが論理ＩＩ　Ｏ”、　”　ｉ　”を
周期的に繰り返すことにより、信−り入力端Ａ、に供給
された入力信号ＩＮの電圧（論理パ０′″）はＡ２．Ａ
３へと順次伝搬して行く。Conventionally, a static type system register is configured as shown in FIG. In the figure, 111 to 114 are l transfer gates connected in cascade on the signal line, and 12
1 to 124u inverter circuit, φ, 5Il-L control signal, IN is input signal, A, -A3 are signal input terminals, for example, two transfer gates 11++112 and two inverter circuits 12t+J22 form one A latch circuit is configured. In the above configuration, the control signal (clock signal) φ periodically repeats the logic IIO", "i", so that the voltage (logic pulse) of the input signal IN supplied to the signal input terminal A increases. 0′″) is A2. A
It propagates sequentially to 3.

例えば、第２図のタイミングチャートに示すように入力
端Ａ１に入力信号ＩＮが供給されると、クロック信号φ
によってトランスファゲート１１４．１１２が閉じてい
る時は、インバータ回路１２１．１２２を介してトラン
スファゲート１１１と１１□との接続点に」二記信号Ｉ
Ｎが供給される。そして、トランスファゲート１１１゜
１１２が開くと、上記インバータ回路１２２の出力はト
ランスファゲート１１１を介してインバータ回路１２１
に帰還されてラッチされるととも援、インバータ回路１
２３　　＋　１２４を介してトランスファゲート１１３
．１１４の接続点に供給される。次にトランスフアゲ−
Ｆｌｌｌ　＊１１２が閉じると（この時トランスファゲ
ート１１３＋１１４は開く）上記信号がトランスファゲ
ート１１３を介してインバータ回路１１３に帰還されて
ラッチされる。上述した動作を順次繰り返すことにより
、信号入力端ＡＩから供給された入力信−ＱＩＮがＡ２
　、Ａ３へと順次転送される。For example, when the input signal IN is supplied to the input terminal A1 as shown in the timing chart of FIG. 2, the clock signal φ
When the transfer gates 114 and 112 are closed, the signal I is sent to the connection point between the transfer gates 111 and 11□ via the inverter circuits 121 and 122.
N is supplied. Then, when the transfer gates 111 and 112 open, the output of the inverter circuit 122 is transferred to the inverter circuit 121 via the transfer gate 111.
Inverter circuit 1 is fed back and latched.
Transfer gate 113 via 23 + 124
．． 114 connection points. Next, the transfer game
When FLll *112 is closed (transfer gates 113+114 are open at this time), the above signal is fed back to inverter circuit 113 via transfer gate 113 and latched. By sequentially repeating the above operations, the input signal -QIN supplied from the signal input terminal AI becomes A2.
, A3.

〔背景技術の問題点〕[Problems with background technology]

ところで、近年ＣＭＯ８論理回路においては、高集積化
および動作速度の高速化が強く望まれており、上述した
シフトレジスタにおいてモ同様な要求がなされている。Incidentally, in recent years, there has been a strong desire for higher integration and higher operating speed in CMO8 logic circuits, and similar demands have been made for the shift registers described above.

しかし、上記のような構成では、ノリーン面積が比較的
大きく、また各ラッチ回路毎に３段のダートを通るので
入力信号ＩＮの転送時間が遅く、消費電力も多い欠点が
ある。However, the above-described configuration has disadvantages in that the Noreen area is relatively large, and since each latch circuit passes through three stages of darts, the transfer time of the input signal IN is slow and power consumption is high.

〔発明の目的〕[Purpose of the invention]

この発明は上記のような事情に鑑みてなされたもので、
その目的とするところは、・クターン面槓を小さくでき
、信号の転送時間が早く、かつ低消費′電力なシフトレ
ジスタを提供することである。This invention was made in view of the above circumstances,
The purpose is to provide a shift register that can reduce the size of the cut-out surface, has a fast signal transfer time, and has low power consumption.

〔発明の概豊〕[Summary of inventions]

すなわち、この発明においては、一端が電源に接続され
入力信号で導通制御されるＮチャンネル形のデプリーシ
ョン形相１　ＭＯＳ　ＦＥＴ　＋７）　（Ｉｈ　端と信
号入力端間にＰチャンネル形のエンハンスメント形相２
　ＭＯＳ　ＦＥＴを接続して制御信号で導通制御する。That is, in this invention, an N-channel type depletion type MOS FET 1 whose one end is connected to a power supply and whose conduction is controlled by an input signal (MOS FET +7) (P-channel type enhancement type 2 is connected between the Ih end and the signal input terminal)
Connect a MOS FET and control conduction using a control signal.

まだ、一端が接地され入力信号で導通制御されるＰチャ
ンネル形のデプリーション形相３　ＭＯＳ　ＦＥＴの他
端と信号入力端間にＮチャンネル形ノエンハンスメン）
　形相４　ＭＯＳ　ＦＥＴを接続して制御信号の反転信
号で導通制御する。There is still a P-channel type depletion type 3 whose one end is grounded and conduction is controlled by the input signal.N-channel type no enhancement between the other end of the MOS FET and the signal input terminal)
Type 4 MOS FET is connected and conduction is controlled by the inverted control signal.

さらに、第１．第２　ＭＯＳ　ＰＥＴの接続点と信号入
力端間に、制御信号で導通制御されるＰチャンネル形の
エンハンスメント形相５　ＭＯＳ　ＦＥ’ｌ’を接続す
るとともに、第３．第４　ＭＯＳ　ＦＥＴの接続点と信
号入力端間に上記制御信号の反転信号で導通制御される
Ｎチャンネル形のエンハンスメント形相６　ＭＯＳ　Ｆ
ＥＴを接続してセルフラッチ回路を構成する。そして、
上記セルフラッチ回路を縦続接続して各転送ダートに状
態保持機能を持たせたシフトレジスタを構成したもので
ある。Furthermore, the first. Between the connection point of the second MOS PET and the signal input terminal, a P-channel type enhancement type 5 MOS FE'l' whose conduction is controlled by a control signal is connected, and the third MOS PET is connected between the connection point of the second MOS PET and the signal input terminal. N-channel enhancement type 6 MOS F whose conduction is controlled by the inverted signal of the above control signal between the connection point of the 4th MOS FET and the signal input terminal.
Connect ET to configure a self-latch circuit. and,
The above self-latch circuits are connected in cascade to form a shift register in which each transfer dart has a state holding function.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例について図面を参照して説明
する。第３図はその構成を示すもので、一端が第１の電
位供給源（電源ｖｃｅ）に接続され入力信号ＩＮで導通
制御されるデシリ−ジョン形の第１導１ｂ゛、形（Ｎチ
ャンネル形）第１ＭＯ８ＦＥＴ　Ｑ　１の他端と信号入
力端Ａ１間に１エンハンスメント形で第２導電形（Ｐチ
ャンネル形）の第２　ＭＯＳ　ＦＥＴ　Ｑ　ｚを接続し
て制御信号Ｔで導通制御する。また、一端が第２の電位
供給源ｖｓｓ（接地点）に接続され入力信号ＩＮで導通
制御されるデシリージョン形でＰチャンネル形の第３　
ＭＯＳ　ＦＥＴ　Ｑ　ａの他端と入力端Ａ１間にエンハ
ンスメント形でＮチャンネル形の第４ＭＯ８ＦＥ１’　
Ｑ　、を接続して上記制御信号■の反転信号φで導通制
御する。さらに、第１．第２ＭＯ８ＦＥＴ　Ｑ＋　　、
　Ｑ２の接続虚と出力端Ａ２　（次段の入力端）間に制
御信号■で導通制御されるエンハンスメント形でＰチャ
ンネル形の第５Δｉｏｓ　ＦＥＴ　Ｑ　６を接続すると
ともに、第３．第４Ｎｉｓｓ　ＦＥＴ　Ｑ　ａ　　、　
Ｑ　４の接続点と出力端Ａ２間に反転信号φで導通制御
されるエンハンスメント形でＮチャンネル形の第６　Ｍ
ＯＳ　ＦＥＴ　Ｑ　６を接続してセルフラッチ回路を構
成する。イーして、上記セルフラッチ回路を縦続接続し
て各転送ｒ−ト毎に状態保持機能を有するシフトレジス
タを構成する。An embodiment of the present invention will be described below with reference to the drawings. Fig. 3 shows its configuration, in which the first conductor 1b, type (N-channel type) of the decision type, whose one end is connected to the first potential supply source (power supply VCE) and whose conduction is controlled by the input signal IN, is shown in Fig. 3. ) A second MOS FET Qz of an enhancement type and a second conductivity type (P channel type) is connected between the other end of the first MO8FET Q1 and the signal input terminal A1, and conduction is controlled by a control signal T. In addition, a third P-channel type which is a decision type whose one end is connected to the second potential supply source vss (ground point) and whose conduction is controlled by the input signal IN is connected.
Between the other end of MOS FET Qa and the input end A1, there is an enhancement type N-channel type 4th MO8FE1'
Q is connected and conduction is controlled by an inverted signal φ of the control signal ①. Furthermore, the first. 2nd MO8FET Q+,
A fifth Δios FET Q6, which is an enhancement type P-channel type whose conduction is controlled by a control signal ■, is connected between the connection point of Q2 and the output terminal A2 (input terminal of the next stage), and a fifth Δios FET Q6 is connected between the third. 4th Niss FET Q a ,
An enhancement type, N-channel type, 6th M, whose conduction is controlled by an inverted signal φ between the connection point of Q4 and the output terminal A2.
A self-latch circuit is constructed by connecting OS FET Q6. The above self-latch circuits are connected in cascade to form a shift register having a state holding function for each transfer rout.

上記の様な構成におい゛Ｃ動作を説明する。今、入力端
Ａｌ＝″１”レベル　Ａ　、　＝Ｈｏ　ｒルベルで、制
御信号φが１１０　ｕから°ｔｘｊｌに変化したとする
。この時、デシリージョン形でＰチャンネル形のＭＯＳ
　ＦＥＴ　Ｑ　ｓのソース電圧ｖＸ１は、ＭＯＳ　Ｆ’
ＥＴ　Ｑ　３　Ｏしきい値電圧をＶＴＩＩＰＤとすると
１−　Ｖｘｌ＞　Ｖｃｃ　−ＶＴＨＰＤ　Ｊ　テある。The operation of C in the above configuration will be explained. Now, suppose that the control signal φ changes from 110 u to °txjl at the input terminal Al=“1” level A,=Hor level. At this time, a decision region type P channel type MOS
The source voltage vX1 of FET Qs is MOS F'
If ETQ3O threshold voltage is VTIIPD, then 1-Vxl>Vcc-VTHPDJ.

従ってＮチャンネル形ＭＯ８ＦＥＴ　Ｑ　４　ノしきい
値電圧ＶＴｆ（Ｎが下式（１）を満たずならば、ＭＯＳ
　ＦＥＴ　Ｑ　３　　ｒ　Ｑ　４によって構成された直
列回路は遮断される。Therefore, the threshold voltage VTf of the N-channel MO8FET Q4 (if N does not satisfy the following formula (1), the MOS
The series circuit formed by FETs Q 3 r Q 4 is interrupted.

Ｖｔｙｎｉ）　ＶＴＨＰＤ　　　　−・”　−（１）一
方、デフ０リージヨン形でＮチャンネル形のＭＯＳ　Ｆ
Ｅ’ｒ　Ｑ　ｔおよびＰチャンネル形ＭＯ８ＦＥＴ　Ｑ
２は；＃逆状態となるので、入力端Ａ１は論理゛１″レ
ベルが保持される。すなわち、Δ１０８　ＦＥＴ　Ｑ’
　ｔ〜Ｑ４から成る直列回路にょっでラッチ回路（メ峯
り回路−）が構成される。１だ、この時ＭＯ８ＦＥＴ　
Ｑｓ　　、Ｑ６　も同時に導通しており、出力端（次段
の入ツバ７Ａｉ　）　Ａ　２にはＡ１の入力信号ＩＮが
転送される。(1) On the other hand, a differential 0 region type N-channel type MOS F
E'r Q t and P channel type MO8FET Q
2 is in the reverse state, so the input terminal A1 is held at the logic "1" level. That is, Δ108 FET Q'
The series circuit consisting of t to Q4 constitutes a latch circuit (memory circuit). 1, at this time MO8FET
Qs and Q6 are also conductive at the same time, and the input signal IN of A1 is transferred to the output terminal (next stage input cap 7Ai) A2.

次に、入力端Ａ、　：＝＝　ＩＩ　ｏ　″レベル、Ａ２
＝°°１”レベルで制御信号φが０”から１″に変化し
たとする。この時、Ｍｏ８　ＦＥＴ　Ｑ　１のソース’
亀圧Ｖｙ　１は、Ｍｏ８　ＦＥＴ　Ｑ　ｔのしきい値電
圧をＶＴＲＮＤとすれば、ｒ　Ｖｙｌ　＜　ＶＴＨＮＤ
　Ｊ　ｆある。Next, input terminal A, :== II o ″ level, A2
Suppose that the control signal φ changes from 0" to 1" at the =°°1" level. At this time, the source of Mo8 FET Q1'
Tortoise pressure Vy 1 is determined by r Vyl < VTHND, where VTRND is the threshold voltage of Mo8 FET Q t.
There is J f.

Ｍｏ８　ＦＥＴ　Ｑ　２　ノしきい値電圧ＶＴＨＰが下
式（２）の関係式ヲｄｈ　タセｉＪ：、Ｍｏ８　ＦＥＴ
　Ｑｔ　　、　Ｑ２によって構成された直列回路は遮断
される。The threshold voltage VTHP of Mo8 FET Q 2 is expressed by the relational expression (2) below.
The series circuit formed by Qt and Q2 is interrupted.

ＶＴＨＰ　＜　ＶＴＨＮＤ　　　・−−（２）この時、
Ｍｏ８　ＦＥＴ　Ｑｓ　　、　Ｑ４は導通しており、入
力端ＡＩは論理°′０”レベルに保持され、出力端（次
段の入力端子）Ａ２には、Ｍｏ８Ｆ、ＥＴＱ３゜Ｑ６を
介して入力端Ａｌと同じ電圧が得られる。VTHP < VTHND ・--(2) At this time,
Mo8 FETs Qs and Q4 are conductive, the input terminal AI is held at the logic °'0'' level, and the output terminal (input terminal of the next stage) A2 is connected to the input terminal Al through Mo8F and ETQ3゜Q6. The same voltage is obtained.

以上の様に、この発明による回路は信号の転送保持を効
率よく行なえる。そして、素子数も従来回路より少々く
（約３／４）構成が比較的チーｉ単であるのでパターン
化した場合に面積を小さくできる。また、特性的には１
段当りのダート数が少ない（約１／３）ので転送速度が
速く、かつ低消費電力化できる。As described above, the circuit according to the present invention can transfer and hold signals efficiently. The number of elements is also a little smaller (about 3/4) than that of the conventional circuit, and the structure is relatively simple, so the area can be reduced when patterned. Also, characteristically 1
Since the number of darts per stage is small (about 1/3), the transfer speed is high and power consumption can be reduced.

第４図は、この発明の他の実施例を示すもので、上記第
３図におけるＭｏ８　ＦＥＴ　Ｑｔ　　、　Ｑｓのバッ
クゲート（基板端子）をそれぞれのゲート電極（信号入
力端）に接続したものである。図において、第３図と同
一構成部は同じ符号を伺してその説明は省略する。この
ような構成によれ１．、　ＸＭｏ５Ｆｈ’ｒ　Ｑ　１　
　＋　Ｑ　３はそれぞれ横形のバイポーラＮＰＮ　）ラ
ンジスタおよびＰＮＰ　）ランジスタ構成となるため電
流供給能力が増大し、動作速度とリーク電流の特性をさ
らに改善できる。FIG. 4 shows another embodiment of the present invention, in which the back gates (substrate terminals) of the Mo8 FETs Qt and Qs in FIG. 3 are connected to their respective gate electrodes (signal input ends). . In the figure, the same components as in FIG. 3 are denoted by the same reference numerals, and their explanation will be omitted. With such a configuration, 1. , XMo5Fh'r Q 1
+Q3 has a horizontal bipolar NPN) transistor and a PNP) transistor configuration, respectively, so the current supply capability is increased and the operating speed and leakage current characteristics can be further improved.

例えば、入力端Ａ！が論理“°１″レベルの場合、Ｍｏ
８　ＦＥＴ　Ｑ　Ｉ側の基板電位は電源電圧ＶＣＣレペ
／ ルとなり、このＭＵＳ　ＦＥＴ　Ｑ　、のしきい値電圧
は低下する。一方、Ｍｏ８　ＦＥＴ　Ｑ　３の基板電位
もＶＣＣレベルとなるので、Ｍｏ８　ＦＥＴ　Ｑ　ｓの
しきい値電圧も低くなり、深く遮断される。For example, input terminal A! If is at the logical “°1” level, then Mo
The substrate potential on the 8 FET Q I side becomes the power supply voltage VCC level, and the threshold voltage of this MUS FET Q decreases. On the other hand, since the substrate potential of Mo8 FET Q 3 also becomes VCC level, the threshold voltage of Mo8 FET Q s also becomes low and is deeply cut off.

第５図は、さらにこの発明の他の実施例を示すもので、
上記第３図の回路におけるＭｏ８　ＦＥＴＱｓ　　、Ｑ
ｓに代えてＭｏ８　ＦＥＴ　Ｑ２　　、Ｑ４の接続点と
出力端（次段の入力端）Ａ２間に制御信号φで制御され
転送回路として働くエンハンスメント形でＮチャンネル
形のＭｏ８　ＦＥＴ　Ｑ　、を設けたものである。この
ような構成によれば回路を構成する素子数をＪ！に低減
できる。FIG. 5 further shows another embodiment of the invention,
Mo8 FETQs, Q in the circuit shown in Fig. 3 above
In place of Mo8 FET Q2 and Q4, an enhancement type N-channel type Mo8 FET Q, which is controlled by a control signal φ and functions as a transfer circuit, is provided between the connection point of Mo8 FET Q2 and Q4 and the output terminal (input terminal of the next stage) A2. It is. According to such a configuration, the number of elements constituting the circuit can be reduced to J! can be reduced to

なお、上記転送回路はＮチャンネル形のＭ０８ＦＥ１’
で構成したが、Ｐチャンネル形のＭｏ８　ＦＥＴで構成
して制御信号７で導通制御しても良く、棟だ、Ｎチャン
ネル形のＭｏ８　ＦＥＴとＰチャンネル形のＭｏ８　Ｆ
ＥＴとを並列接続したトランスファケ゛−トで構成して
も良い。The above transfer circuit is an N-channel type M08FE1'.
However, it is also possible to configure it with a P-channel type Mo8 FET and conduction control using the control signal 7.
It may also be configured with a transfer gate in which the ET and the ET are connected in parallel.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明によれば、パターン面積を
小さくでき、信号の転送時間が早く、かつ低消費電力な
シフトレジスタが得られる。As described above, according to the present invention, a shift register with a small pattern area, fast signal transfer time, and low power consumption can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

産１図は従来のシフトレジスタを示す回路図、第２図は
上記第１図の回路の動作を曲、明するためのタイミング
チャート、第３図はこの発明の一実施例に係るシフトレ
ジスタを示す回路図、第４図および第５図はそれぞれこ
の発明の他の実施例を示す回路図である。 ＶＣＣ・・・第１の電１位供給源、ＩＮ・・・入力信号
、Ｑｌ−Ｑｙ・・・Ｍｏ８ＦＥＴ、Ａ、、Ａ２　、Ａ３
・・・信号入力端、Ｖ８Ｂ・・・第２の電位供給源、φ
、■・・・制御信号。 出願人代理人　　弁理士　鈴　江　武　彦！ 第１図 第２図 第３図 第５図Figure 1 is a circuit diagram showing a conventional shift register, Figure 2 is a timing chart to explain the operation of the circuit shown in Figure 1, and Figure 3 is a shift register according to an embodiment of the present invention. The circuit diagrams shown in FIGS. 4 and 5 are circuit diagrams showing other embodiments of the present invention, respectively. VCC...first potential supply source, IN...input signal, Ql-Qy...Mo8FET, A, , A2, A3
...Signal input terminal, V8B...Second potential supply source, φ
,■...control signal. Applicant's agent, patent attorney Takehiko Suzue! Figure 1 Figure 2 Figure 3 Figure 5

Claims (9)

【特許請求の範囲】[Claims] （１）一端が第１の電位供給源に接続され信号入力端に
入力される入力信号で導通制御される第１導市形のデプ
リーション形相１　ＭＯＳ　ＦＥＴと、この第１　ＭＯ
Ｓ　ＦＥＴの他端と信号入力端間に接続され制御信号で
導通制御される第２導電形のエンハンスメント形第２　
ＭＯＳ　ＦＥＴと、一端が第２の電７位供給源に接続さ
れ入力信号で導通制御される第２導電形のデグリーショ
ン形相３　ＭＯＳ　ＦＥＴと、この第３　ＭＯＳ　ＦＥ
Ｔの他端と信号入力端間に接続され上記制御信号の反転
信号で導通制御される第１導電形のエンハクスメント形
第４　ＭＯＳＦＥＴと、上記第１．第２　ＭＯＳ　ＦＥ
Ｔの接続点と信号出力端間に接続され制御信号で導通制
御される第２導１４Ｉ、形のエンハンスメント形第５　
ＭＯＳ　ＦＥＴと、上記第３．第４　ＭＯＳ　ＦＥＴの
接続点と信号出力端間に接続され上記制御信号の反転信
号で導通制御される第１導重、形のエンハンスメント形
第５　ＭＯＳ　ＦＥＴとから成るセルフラッチ回路を縦
続接続して構成したことを特徴とするシフトレジスタ。(1) A first conductive type depletion type 1 MOS FET whose one end is connected to a first potential supply source and whose conduction is controlled by an input signal input to a signal input terminal, and this first MO
Enhancement type 2 of the second conductivity type connected between the other end of the S FET and the signal input terminal and conduction controlled by the control signal.
A MOS FET, a degree type 3 MOS FET of a second conductivity type whose one end is connected to a second potential supply source and whose conduction is controlled by an input signal, and this third MOS FE.
a fourth enhancement type MOSFET of a first conductivity type connected between the other end of the T and the signal input terminal and whose conduction is controlled by an inverted signal of the control signal; 2nd MOS FE
The second conductor 14I is connected between the connection point of T and the signal output terminal and conduction is controlled by the control signal.
MOS FET and the above 3. A self-latch circuit consisting of a fifth enhancement-type MOS FET connected in cascade between the connection point of the fourth MOS FET and a fifth MOS FET of the first conductive type and whose conduction is controlled by an inverted signal of the control signal is connected in cascade. A shift register characterized by comprising: （２）上記セルフラッチ回路を構成する第２゜第５　Ｍ
ＯＳ　ＦＥＴおよび第４．第６　ＭＯＳ　ＦＥＴに供給
される制御信号およびその反転信号はそれぞれ、隣接す
るセルフラッチ回路間で互いに逆相の関係にあることを
特徴とする特許請求の範囲第１項記載のシフトレジスタ
。(2) 2nd and 5th M constituting the above self-latch circuit
OS FET and 4th. 2. The shift register according to claim 1, wherein the control signal and its inverted signal supplied to the sixth MOS FET have opposite phases between adjacent self-latch circuits. （３）上記第１　ＭＯＳ　ＦＥＴのしきい値電圧は第２
ＭＯ８ＦＥＴのしきい値電圧より高く、第３　ＭＯＳ　
ｌｉ’ＥＴのしきい値電圧は第４　ＭＯＳ　ＦＥＴのし
きい値市、圧よシ低い関係を満たすことを特徴とする特
許請求の範囲第１項または第２項記載のシフトレジスタ
。(3) The threshold voltage of the first MOS FET is the same as that of the second MOS FET.
Higher than the threshold voltage of MO8FET, the third MOS
3. The shift register according to claim 1, wherein the threshold voltage of the li'ET satisfies a lower relationship than the threshold voltage of the fourth MOS FET. （４）上記第１．第３　ＭＯＳ　ＦＥＴの基板端子を信
号入力端に接続したことを特徴とする特許請求の範囲第
１項ないし第３項のいずれかのシフトレジスタ。(4) Item 1 above. 4. The shift register according to claim 1, wherein a substrate terminal of the third MOS FET is connected to a signal input terminal. （５）一端が第１の電位供給源に接続され信号入力端に
入力される入力信号で導通制御される第１導霜１形のデ
グリーション形相１　ＭＯＳ　ＦＥＴと、この第１　Ｍ
ＯＳ　ＦＥＴの他端と信号入力端間に接続され制御信号
で導通制御される第２導電形のエンハンスメント形相２
　ＭＯＳＦＥＴと、一端が第２の電位供給源に接続され
入力信号で導通制御される第２導電形のデシリージョン
形相３　ＭＯＳ　ＦＩＧＴと、この第３　ＭＯＳ　ＦＥ
Ｔの他端と信号入力端間に接続され上記制御信号の反転
信号で導通制御される第１導電形のエンハンスメント形
相４　ＭＯＳＦＥＴと、上記第２．第４　ＭＯＳ　ＦＥ
Ｔの接続点と信号出力端間に配設され制御信号あるいは
その反転信号で導通制御される転送回路とから成るセル
フラッチ回路を縦続接続して構成したことを特徴とする
シストレジスタ。(5) A first degreation type 1 MOS FET with one end connected to the first potential supply source and whose conduction is controlled by an input signal input to the signal input terminal;
Enhancement form 2 of the second conductivity type connected between the other end of the OS FET and the signal input terminal and conduction controlled by the control signal
A MOSFET, a second conductivity type decimation type 3 MOS FIG whose one end is connected to a second potential supply source and whose conduction is controlled by an input signal, and this third MOS FE.
an enhancement type 4 MOSFET of a first conductivity type connected between the other end of the T and a signal input terminal and whose conduction is controlled by an inverted signal of the control signal; 4th MOS FE
1. A system resistor characterized in that it is constructed by cascade-connecting self-latch circuits each comprising a transfer circuit disposed between a connection point of T and a signal output terminal and whose conduction is controlled by a control signal or its inverted signal. （６）上記セルフラッチ回路を構成する第２゜第４　Ｍ
ＯＳ　ＦＥＴおよび転送回路に供給される制御信号ある
いはその反転信号はそれぞれ、隣接するセルフラッチ回
路間で互いに逆相の関係にあることを特徴とする特許請
求の範囲第５項記載のシストレジスタ。(6) 2nd and 4th M constituting the above self-latch circuit
6. The system register according to claim 5, wherein the control signals or their inverted signals supplied to the OS FETs and the transfer circuits have opposite phases between adjacent self-latch circuits. （７）上記第１　ＭＯＳ　ＦＥＴのしきい値箱゛１圧は
第２ＭＯ８ＦＥＴのしきい値電圧より高く、第３１−動
Ｓ　ＦＥＴのしきい値電圧は第４　ＭＯＳ　ＦＥＴのし
きい値電圧より低い関係を満たすと七を特徴とする特許
Ｈ／Ｊ求の範囲第５項または第６項記載のシフトレジス
タ。(7) The threshold voltage of the first MOSFET is higher than the threshold voltage of the second MO8FET, and the threshold voltage of the thirty-first MOSFET is lower than the threshold voltage of the fourth MOSFET. The shift register according to item 5 or 6 of the scope of patent H/J, characterized in that the following relationship is satisfied. （８）上記第１．第３　ＭＯＳ　ＦＥＴの基板端子を信
号入力端に接続したことを特徴とする特許請求の範囲第
５項ないし第７項のいずれかのシフトレジスタ。(8) Paragraph 1 above. 8. The shift register according to claim 5, wherein a substrate terminal of the third MOS FET is connected to a signal input terminal. （９）上記転送回路は、エンハンスメント形のＭＯＳ　
ＰＥＴから成ることを特徴とする特許請求の範囲第５項
ないし第８項のいずれかのシフトレジスタ。 ０（）　　上記転送回路は、Ｎチャンネル形のｈｑｏＢ
ＦＥＴとＰチャンネル形のＭＯＳ　ＦＥＴとを並列接続
しそれぞれのダートに逆相の制御信号を印加したトラン
スファゲートから成ることを特徴とする特許請求の範囲
第５珀ないし第８項のいずれかのシフトレジスタ。(9) The above transfer circuit is an enhancement type MOS
The shift register according to any one of claims 5 to 8, characterized in that it is made of PET. 0() The above transfer circuit is an N-channel hqoB
The shift according to any one of claims 5 to 8, characterized in that it is comprised of a transfer gate in which a FET and a P-channel type MOS FET are connected in parallel and a control signal of an opposite phase is applied to each dart. register.
JP57197108A 1982-11-10 1982-11-10 Shift register Granted JPS5987698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57197108A JPS5987698A (en) 1982-11-10 1982-11-10 Shift register

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57197108A JPS5987698A (en) 1982-11-10 1982-11-10 Shift register

Publications (2)

Publication Number Publication Date
JPS5987698A true JPS5987698A (en) 1984-05-21
JPS6236314B2 JPS6236314B2 (en) 1987-08-06

Family

ID=16368859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57197108A Granted JPS5987698A (en) 1982-11-10 1982-11-10 Shift register

Country Status (1)

Country Link
JP (1) JPS5987698A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0242572A2 (en) * 1986-03-27 1987-10-28 Kabushiki Kaisha Toshiba Delay circuit of a variable delay time

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0242572A2 (en) * 1986-03-27 1987-10-28 Kabushiki Kaisha Toshiba Delay circuit of a variable delay time

Also Published As

Publication number Publication date
JPS6236314B2 (en) 1987-08-06

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