JPS5986330A - Analog-digital converting system - Google Patents
Analog-digital converting systemInfo
- Publication number
- JPS5986330A JPS5986330A JP19659782A JP19659782A JPS5986330A JP S5986330 A JPS5986330 A JP S5986330A JP 19659782 A JP19659782 A JP 19659782A JP 19659782 A JP19659782 A JP 19659782A JP S5986330 A JPS5986330 A JP S5986330A
- Authority
- JP
- Japan
- Prior art keywords
- variable
- voltage
- attenuation
- conversion
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 2
- 241000219112 Cucumis Species 0.000 description 1
- 235000015510 Cucumis melo subsp melo Nutrition 0.000 description 1
- FJJCIZWZNKZHII-UHFFFAOYSA-N [4,6-bis(cyanoamino)-1,3,5-triazin-2-yl]cyanamide Chemical compound N#CNC1=NC(NC#N)=NC(NC#N)=N1 FJJCIZWZNKZHII-UHFFFAOYSA-N 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、高周波のレベルを、デシベル値で測定するΔ
／［）変換方式に関するちのである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a Δ
/[) This is about the conversion method.
従来のＡ／Ｄ変換方式では、高周波信号を増幅、検波し
、この倹波電口：を対数変換回路により、デシベル値に
変換後、Ａ／Ｄ変挽回路１： Ｊ、す、高周波レベルを
デシベル値にて測定することが多い。In the conventional A/D conversion method, a high frequency signal is amplified and detected, and after converting this signal into a decibel value using a logarithmic conversion circuit, the A/D conversion circuit 1 converts the high frequency level into a decibel value. It is often measured in decibels.
基本的には、例えば、第１図に示ｔ Ｊ、うに、人力端
子１より人力された高周波信号は、増幅器２および検波
回路３により、増幅、検波され、検波電圧は対数変換器
４ににす、１ジベル１「１で表わされる電圧に変換され
る。この電圧は、電圧比較器５、制御器６、レジスタ７
および１〕／Ａ変ＪＡ器８を含むΔ／Ｄ変換回路により
Ａ／Ｄ変換され、Ｎピッ１−のＡ／Ｄ変換値として出力
端子９１〜９Ｎに出力されるのである。Basically, for example, as shown in FIG. This voltage is converted into a voltage represented by 1 dB, 1 dB, and 1 dB.
and 1] is A/D converted by a Δ/D conversion circuit including an A/A converter 8, and outputted to output terminals 91 to 9N as an A/D converted value of N pins 1-.
しかしながら、このｊ：うなＡ／Ｄ変換方式では、Ａ／
Ｄ変換を広範囲なレベルに渡って行なう条件において、
対数変換器４の精度を良く覆る必要があり、調整が複層
になり、また、ロス１〜アツプにもなる。更に、△／Ｄ
変換の分ＶＲ度を小さく覆るためには、Ｄ／△変挽器８
にＪ５いて微少な電圧、変化を処理づ−るため、消１音
などの影響を受【〕るａりそれがある。However, in this j:una A/D conversion method, the A/D conversion method is
Under conditions where D conversion is performed over a wide range of levels,
It is necessary to better match the accuracy of the logarithmic converter 4, which requires multiple adjustments and also increases the loss. Furthermore, △/D
In order to reduce the VR degree by the conversion, D/△ converter 8
Because the J5 handles minute voltage changes, it may be affected by things like muting.
本発明は、上記事情にもとづいてなされｉこもので、Ａ
／Ｄ変換を広範間なレベルｔこ渡って、しかも所要の分
解能で１１えるＡ／川用変換方式を提供しようとするも
のである。The present invention was made based on the above circumstances, and
The purpose of this invention is to provide an A/D conversion method that can perform A/D conversion over a wide range of levels t and at the required resolution.
この目的のため、本発明は高周波信号を、複数の可変減
衰回路または利１７可変増幅器に通し、この可変減衰回
路または利得可変増幅器の出力信号を検波し、この検波
？ｆｆ Ｈ−が所定の１１１ど−Ｊ＆するにうに、上記
可変減衰回路の減衰量また番、１利檜！１可変増幅器の
４・１日ｑを制ｔｅｌｌ Ｌ、」上記検波電圧が所定値
と一致した時の−に記旬変減衰回路の減衰用または利４
Ｗｉ ｉｉｌ変１１９幅器の利得にり相対的に高周波信
号の１ノベルをデシベル値にて測定Ｊることを精微どす
るものである１゜
ｍ Ｆ、本発明の一実施例を第２図を参照し−（具体的
に説明り−る。なおここでは、第１図にＪ３いて説明し
た部分ど同一部分については、同−符号をイ」シて説明
を省略覆る。そして図中、符号１０１ないし１（）Ｎは
、ｉｉｌ変減衰器であっ゛Ｃ１各々の減衰量はＡ／１〕
変換の分解度に応じて分解度ＸＡ（ここでＡ＝２” 、
＋＋ ＝１〜Ｎの整数） ｄｒ３どなって、４３す、
検波器３の出ノＪ電圧は、レジスタ７の制御によりデ゛
ジベルｔｉｌで変化する。また、電圧比較器５は基準”
Ｔｉ １．１＝ １１と検波器３の出力電圧を比較し、
基ジスタフに出力され、Ａ／１〕変換が完了づる。For this purpose, the present invention passes a high frequency signal through a plurality of variable attenuation circuits or variable gain amplifiers, detects the output signal of the variable attenuation circuits or variable gain amplifiers, and detects the output signal of the variable attenuation circuit or variable gain amplifier. When ff H- is a predetermined 111-J&, the attenuation amount of the variable attenuation circuit is 1 Ryu! 1 to control the 4.1 day q of the variable amplifier.
One embodiment of the present invention is shown in FIG. Referring to (a detailed explanation will be given). In this case, the same reference numerals are used to omit the explanations for the same parts as those explained with reference to J3 in FIG. 1. to 1()N are variable attenuators (the attenuation amount of each C1 is A/1)
Depending on the resolution of the conversion, the resolution XA (where A=2",
++ = integer from 1 to N) dr3, 43,
The output J voltage of the detector 3 changes in decibels under the control of the register 7. In addition, the voltage comparator 5 is the reference
Compare Ti 1.1= 11 and the output voltage of detector 3,
The A/1] conversion is completed.
このような構成では、高周波信号は入力端ｒ１より入力
され、増幅器２にて増幅され、可変減衰器１０１〜１Ｏ
Ｎの出力信号は検波器３にＪ：り検波され、検波電圧を
４ｇる。この検波′ｔｒｉＪ１は電圧比較器５にて基準
電圧１１ど比較され、上記検波電圧が基準電圧と一致づ
るｊ：でｉｌｉ！制御器（１どレジスタ７は可変減衰器
１０１〜１ＯＮの減衰量を切り替える。上記検波電圧が
基準電圧と一致りるど、電圧比較器！１の出力により、
制御器６と１ノジスタ７の動作を停止しＡ／Ｄ変挽は完
了する。In such a configuration, a high frequency signal is input from the input terminal r1, is amplified by the amplifier 2, and is amplified by the variable attenuators 101 to 1O.
The output signal of N is detected by the detector 3, and the detected voltage is 4g. This detected wave 'triJ1 is compared with a reference voltage 11 in a voltage comparator 5, and if the detected voltage matches the reference voltage, j: is ili! The controller (1 register 7 switches the amount of attenuation of the variable attenuators 101 to 1ON. When the detected voltage matches the reference voltage, the output of the voltage comparator !1
The operation of the controller 6 and the nozzle 7 is stopped, and the A/D conversion is completed.
このような△／Ｄ変換方式に、Ｊこれば、基１１１ｉ電
圧１１を、検波器３０人力レベルｒ３ｄｓの時の検波器
３の出力電圧ど一致ＪるＪ、うに設定Ｊることにより、
高周波入力レベルＳｏは次のように測定さ４する。In such a Δ/D conversion method, by setting the base 111i voltage 11 to match the output voltage of the detector 3 at the human power level r3ds of the detector 30,
The high frequency input level So is measured as follows.
Ｓｏ ＝［３−Ｃ＋ｌ）
ここで、Ｃは増幅器２の利ｉｉ１．１つは可変減衰器１
０１〜１ＯＮの減衰量の和であるＩＩ ＞ｌ：た、出力
幅；；子９ｌ−９ＮにはΔ／Ｄ変換値が次のＪこうにＮ
ピッ１への並列信ＹＪ（−出ノノされる。So = [3-C+l) Here, C is the gain of amplifier 2 ii1.1 is the gain of variable attenuator 1
II which is the sum of the attenuation amount of 01 to 1ON
Parallel signal YJ to pin 1 (- is output.
Ｓｏ−Σ Ｌ＋＋（分解瓜×２″−１）ｎてｌ
ここｐ、１−ｎはΔ／Ｄ変換値の ピッｔ−１＋のロジ
ック状態であり、１１１１１または“′０″である。So-Σ L++ (decomposed melon x 2''-1) ntel Here, p and 1-n are the logic states of pit t-1+ of the Δ/D conversion value, which is 11111 or "'0".
なお、上記実り色間ではＮ個の可変減衰器１（）１〜１
ＯＮを設【ノだが、Ｎ個の利得可変増幅器に代え−Ｃも
よく、この場合は、その利得の変動量を制御器６とレジ
スタ７で切り換えられる。In addition, between the above-mentioned fruit colors, N variable attenuators 1()1 to 1 are used.
Although ON is provided, -C may be used instead of N variable gain amplifiers, and in this case, the amount of gain variation can be switched by the controller 6 and the register 7.
以上のように、本発明ににれば、Ａ／Ｄ変操の結果が可
変減資器の減衰用または利４ｒｔ可変増幅器の変動量の
和より求められるため、従来のように対数変換器、Ｄｙ
Δ変換器が不要どなり、」ス１−が低減され、また、調
整が容易になるという利点カアル。１ ｋ、検波ａ ニ
ハ、ｌ！ ｆ％ｔ １１？Ｈイｔ ＞１ タｔｊテ直線
性が必要とされるため、従来方式におりる検波器に比べ
簡単な検波器で充分目的を達することができ、また、基
準電圧を充分大きくすることにより雑音などの影響を回
避Ｊることができる。As described above, according to the present invention, the result of A/D conversion is obtained from the sum of the attenuation of the variable capital reducer or the variation amount of the 4rt variable amplifier.
This has the advantage of eliminating the need for a Δ converter, reducing noise and making adjustment easier. 1 k, detection a Niha, l! f%t 11? Hit > 1 Since linearity is required, a detector that is simpler than conventional detectors is sufficient to achieve the purpose, and by making the reference voltage sufficiently large, noise can be reduced. It is possible to avoid the effects of
また、Ａ／１〕変換を広範囲なレベルに渡−）て行なえ
るので、可変減衰器あるいは利得可変増幅器の増設のみ
で、種々の適用が可能２゛ある。Furthermore, since A/1 conversion can be performed over a wide range of levels, a variety of applications are possible by simply adding a variable attenuator or variable gain amplifier.
第１図は従来の△／′Ｄ変挽方式の構成図、第２図は本
発明の一実施例を示Ｕ’ Ｊｆ＆成図である。
１・・・入力端子、２・・・増幅器、３・・・検波器、
４・・・対数変換器、５・・・電圧比較器、６・・・制
御器、７・・・レジスタ、８・・・Ｄ／△変ＪＡ ？４
ｇ、９１・−〇Ｎ・・・出力端子、１０１−１ＯＮ・・
・可変減衰器、１１・・・基準電圧。
特ＥＩ丁出順人 バイＡニア株式会ン１代理人弁理
士 小 橋 信 淳
同 弁理士 祠 月 進FIG. 1 is a block diagram of a conventional Δ/'D variable grinding system, and FIG. 2 is a diagram showing an embodiment of the present invention. 1...Input terminal, 2...Amplifier, 3...Detector,
4... Logarithmic converter, 5... Voltage comparator, 6... Controller, 7... Register, 8... D/△variable JA? 4
g, 91・-〇N...Output terminal, 101-1ON...
- Variable attenuator, 11... reference voltage. Special EI Chode Junto Buy A Near Co., Ltd. 1 Representative Patent Attorney Jundo Kobashi Patent Attorney Susumu Tsuki
Claims (1)
幅器に通し、この可変減衰回路または利得可変増幅器の
出力信号を検波し、この検波用圧が所定の値と一致する
ように、上記可変減衰回路の減衰量または利４ｆ７ ｉ
ｊｌ変増変器幅器得を制御し、上記検波電圧が所定値と
一致した時の上記可変１Ｉｉｌｉ衰回路の減衰■１また
は利得可変増幅器の利得ｊ；り相対的にａＦｌ波信号の
レベルをデシベル値にて測定することを特徴とするＡ／
Ｄ変換方式。The high frequency (g) is passed through a plurality of variable attenuation circuits or variable gain amplifiers, the output signal of this variable attenuation circuit or variable gain amplifier is detected, and the variable attenuation is Attenuation or gain of the circuit 4f7 i
jl variable transformer width gain is controlled, and the level of the aFl wave signal is relatively controlled by the attenuation of the variable attenuation circuit 1 or the gain j of the variable gain amplifier when the detected voltage matches a predetermined value. A/ characterized by measuring in decibel value
D conversion method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19659782A JPS5986330A (en) | 1982-11-09 | 1982-11-09 | Analog-digital converting system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19659782A JPS5986330A (en) | 1982-11-09 | 1982-11-09 | Analog-digital converting system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5986330A true JPS5986330A (en) | 1984-05-18 |
Family
ID=16360383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19659782A Pending JPS5986330A (en) | 1982-11-09 | 1982-11-09 | Analog-digital converting system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5986330A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5034772A (en) * | 1973-08-01 | 1975-04-03 | ||
| JPS5787237A (en) * | 1980-11-18 | 1982-05-31 | Matsushita Electric Ind Co Ltd | Nonlinear analogue-digital converting circuit |
-
1982
- 1982-11-09 JP JP19659782A patent/JPS5986330A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5034772A (en) * | 1973-08-01 | 1975-04-03 | ||
| JPS5787237A (en) * | 1980-11-18 | 1982-05-31 | Matsushita Electric Ind Co Ltd | Nonlinear analogue-digital converting circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7405683B1 (en) | Extending the dynamic range in an energy measurement device | |
| JPH0766744A (en) | Electric field detecting circuit | |
| US4475398A (en) | Successive approximation envelope detection for estimating the amplitude of a plurality of successively occurring electrical pulses | |
| US20030006839A1 (en) | Extended range power detector and amplifier and method | |
| JPS5986330A (en) | Analog-digital converting system | |
| CA1115788A (en) | Level selective a-c monitoring circuit | |
| KR100390666B1 (en) | Method and apparatus for providing gain control feedback in rf amplifiers | |
| US3217247A (en) | System for measurement of attenuation taken directly in decibels at radio frequencies utilizing logarithmic circuits | |
| JPH0575362A (en) | Balanced amplifier | |
| US5221907A (en) | Pseudo logarithmic analog step adder | |
| JPS6211170A (en) | Power detection circuit | |
| JPH07177045A (en) | Power consumption reducing system for high frequency amplifier circuit | |
| SU1030748A1 (en) | Device for checking linear integrated circuit parameters | |
| US20060108992A1 (en) | System for regulating the level of an amplified signal in an amplification chain | |
| KR100282398B1 (en) | Base station transmitter | |
| JPH06177806A (en) | Power sum fixed agc circuit | |
| JP3074890B2 (en) | Power amplifier | |
| JPS5846707A (en) | Control circuit of output level | |
| US2887658A (en) | Frequency response determining apparatus | |
| SU1636785A2 (en) | Device for wide band ac-to-dc conversion | |
| SU881627A1 (en) | Device for measuring uhf four terminal network amplitude characteristics | |
| JPS6331057B2 (en) | ||
| JPS5856540A (en) | Detecting circuit for incoming signal level | |
| JP2001343408A (en) | Signal intensity detector | |
| JPH0157308B2 (en) |