JPS5986241A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS5986241A JPS5986241A JP19637182A JP19637182A JPS5986241A JP S5986241 A JPS5986241 A JP S5986241A JP 19637182 A JP19637182 A JP 19637182A JP 19637182 A JP19637182 A JP 19637182A JP S5986241 A JPS5986241 A JP S5986241A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- groove
- region
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置及びその製造方法の改良に関する
・
〔発明の技術的背景とその問題点〕
従来、半導体としてシリコンを用いた半導体装置、特に
ＭＯ８型半導体装置においては、寄生チャネルによる絶
縁不良をなくし、かつ寄生容量を小さくするために素子
間の所謂フィールド領域に厚い絶縁膜を形成することが
行われている。このような厚い絶縁膜を素子分離領域に
形成する方法としては、代表的には次の３つの方法が良
く知られている。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to improvements in a semiconductor device and a method for manufacturing the same. In MO8 type semiconductor devices, a thick insulating film is formed in a so-called field region between elements in order to eliminate insulation defects caused by parasitic channels and to reduce parasitic capacitance. The following three methods are typically well known as methods for forming such a thick insulating film in the element isolation region.
まず、第一の方法はｒ、ｏｃｏｓ法（例えば：文献Ｐｈ
１１１ｐｓ Ｒｅｓ、Ｒｅｐｔｓ、２５，１１８−１３
２（１９７０））として知られ、耐酸化性の膜で素子形
成領域を覆い、素子分離領域のシリコン基板を熱酸化し
て選択的に厚い酸化膜を形成する方法である。First, the first method is the r, ocos method (for example: literature Ph
111ps Res, Repts, 25, 118-13
2 (1970)), this method covers the element formation region with an oxidation-resistant film and selectively forms a thick oxide film by thermally oxidizing the silicon substrate in the element isolation region.
第二の方法は、代表的にはＲＥＯＸ法（例えば：文献Ｉ
ＥＤＭ Ｔｅｃｈｎ、 Ｄｌｇｅｓｔ、 １７７−１８
０（１９７８））として知られ、素子分離領域のシリコ
ン基板中に基板と同導電型の不純物層とシリコン基板上
に素子分ｂＩＵ用のＣＶＤ −５ｓｏ２膜とを自己整合
的に形成する方法である。The second method is typically the REOX method (for example: Ref. I
EDM Techn, Dlgest, 177-18
0 (1978)) is a method in which an impurity layer of the same conductivity type as the substrate is formed in a silicon substrate in an element isolation region, and a CVD-5SO2 film for element bIU is formed on the silicon substrate in a self-aligned manner. .
第三の方法は、代表的にはＢＯＸ法（例えば：文献ＩＥ
ＤＭＴｅｃｈｎ、 Ｄｉｇｅｓｔ、 ３８４−３８７（
１９８１））として知られ、素子分離領域のシリコン基
板を少なくとも一部工、チングとして溝部を形成し、こ
の溝部を絶縁膜で埋め込む方法である。The third method is typically the BOX method (for example: Reference IE
DMTechn, Digest, 384-387 (
1981)) is a method in which at least a portion of a silicon substrate in an element isolation region is etched to form a trench, and this trench is filled with an insulating film.
しかし、上記いずれの素子分離法を用いても、素子を形
成する領域は素子分離用の酸化膜でとシ囲まれた半導体
基板表面のみに限定されている。また、ダイナミックＲ
ＡＭ等に代表される高密度メモリデバイスは、その集積
密度を上げるため微細化される傾向にあり、従って素子
形成領域の面積は益々小さくなっている。このため、Ｍ
ＯＳ ）ランジスタのチャネル幅が狭くナリ、トランジ
スタの十分な電流駆動力（チャネルコンダクタンス）が
得られなくなる。さらに、ＭＯＳキャパシタにおいては
、キャノＪ？シタ面積が小さくなるため、十分な、キャ
パシタ容量が得られないという問題が生じてきている。However, no matter which of the above element isolation methods is used, the region in which elements are formed is limited to only the surface of the semiconductor substrate surrounded by an oxide film for element isolation. Also, dynamic R
High-density memory devices typified by AM and the like tend to be miniaturized to increase their integration density, and therefore the area of the element formation region is becoming smaller and smaller. For this reason, M
OS) The channel width of the transistor is narrow, making it impossible to obtain sufficient current driving power (channel conductance) of the transistor. Furthermore, in MOS capacitors, Cano J? Since the area of the capacitor becomes smaller, a problem has arisen in that sufficient capacitor capacity cannot be obtained.
特に、前記ＬＯＣＯ８法においては、素子分離用酸化膜
が周辺から１．０〔μｍ〕程度素子形成領域に侵入する
ため、素子形成領域の面積の減少は著しく、上記チャネ
ルコンダクタンスの低下とキャパシタ容量の低下は深刻
な問題となっている。逆にいえば、十分なチャネルコン
ダクタンス及びキャノやシタ容１′を得るには素子形成
領域の面積を広くする必要があり、これが素子の微細化
及び高密度化を妨げる大きな要因となる。In particular, in the LOCO8 method, the element isolation oxide film invades the element formation region by about 1.0 [μm] from the periphery, so the area of the element formation region is significantly reduced, resulting in the decrease in channel conductance and capacitance. The decline has become a serious problem. Conversely, in order to obtain sufficient channel conductance and capacitance 1', it is necessary to widen the area of the element formation region, and this becomes a major factor hindering miniaturization and higher density of elements.
一方、相補型ＭＯ８（Ｃ−ＭＯＳ）インノ々−夕等にお
いては、Ｐチャネルトランジスタのソースの耐圧及びに
チャネルト°ランジスタのソースとＮ型基板との耐圧を
保つために、これらの間隔をある基準以上必要とする。On the other hand, in the complementary MO8 (C-MOS) industry, in order to maintain the breakdown voltage of the source of the P-channel transistor and the breakdown voltage between the source of the channel transistor and the N-type substrate, the distance between them is set at a certain level. Requires more than the standard.
また、Ｎチャンネルトランジスタのチャネル幅とＰチャ
ネルトランジスタのチャネル幅もトランジスタに流れる
電流値を大きくするためにある基準以上必要とする。し
たがって、こ、−場合も素子形成領域の面積を広くする
必要かあシ、これが微細化及び高集積化をはかる上で大
きな障害となっている。Further, the channel width of the N-channel transistor and the channel width of the P-channel transistor are also required to exceed a certain standard in order to increase the value of current flowing through the transistor. Therefore, in this case as well, it is necessary to widen the area of the element formation region, which is a major obstacle in achieving miniaturization and high integration.
本発明の目的は、素子形成領域の面積を大きくすること
なく、十分大きなチャネルコンダクタンス及びキャパシ
タ容量等を得ることができ、素子の微細化及び高密度化
をはかシ得る半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that can obtain sufficiently large channel conductance, capacitor capacity, etc. without increasing the area of the element formation region, and can facilitate miniaturization and high density of elements. It is in.
また、本発明の他の目的は、上記微細化及び高密度化に
を与し得る半導体装置の製造方法を提供することにある
。Another object of the present invention is to provide a method for manufacturing a semiconductor device that can achieve the above-mentioned miniaturization and high density.
本発明の骨子は、素子分離領域に設けた溝部の側壁にも
薄い絶縁膜を介して電極材料を形成することにある。The gist of the present invention is to form electrode material also on the side walls of the groove provided in the element isolation region via a thin insulating film.
すなわち本発明は、半導体基板上の素子分離領域をエツ
チングして形成された溝部に、第１の絶縁膜を埋め込ん
で素子分離をはかった半導体装置において、上記第１の
絶縁膜の一部を除去し上記溝部の側壁を露出し、この露
出した側部及び基板の素子形成領域上に第２の絶縁膜を
形成し、この第２の絶縁膜上に電極月利を被着するよう
にしたものでおる。That is, the present invention provides a semiconductor device in which element isolation is achieved by burying a first insulating film in a trench formed by etching an element isolation region on a semiconductor substrate, in which part of the first insulating film is removed. The side wall of the groove is exposed, a second insulating film is formed on the exposed side and the element forming area of the substrate, and an electrode is deposited on the second insulating film. I'll go.
また、本発明は上記半導体装１ｄヲ製造するに際し、半
導体基板の素子形成領域上にマスク材ｖｉ−被着したの
ち、このマスク材を用い′上記基板の素子分離領域を選
択エツチングして溝部を形成し、次いで全面に上記溝部
の深さと略同じ膜厚の第１の絶縁膜を堆積し、次いで段
差部に堆積した絶縁膜のエツチング速度が平坦部に堆積
した絶縁膜のエツチング速度よシ速くなるエツチング条
件で上記第１の絶縁膜全工、チングして前記溝部の側壁
を露出せしめ、次いで前記マスク材を除去することによ
シ該マスク材上の第１の絶縁膜を除去して素子形成領域
を露出せしめ、次いで上記露出した素子形成領域及び前
記溝部の側壁に第２の絶縁膜を形成し、しかるのち上記
第２の絶縁膜上に電極材料を被着するようにした方法で
ある。Further, in manufacturing the semiconductor device 1d, the present invention deposits a mask material vi on the element formation region of the semiconductor substrate, and then selectively etches the element isolation region of the substrate using this mask material to form a groove. Then, a first insulating film having a thickness substantially the same as the depth of the groove is deposited on the entire surface, and the etching rate of the insulating film deposited on the stepped portion is faster than the etching rate of the insulating film deposited on the flat portion. The entire first insulating film is etched under etching conditions to expose the side walls of the trench, and then the mask material is removed, thereby removing the first insulating film on the mask material and forming the device. In this method, a formation region is exposed, a second insulating film is formed on the exposed element formation region and the side wall of the groove, and then an electrode material is deposited on the second insulating film. .
トランジスタを形成すると、実効的なチャネル幅が島状
素子領域の上面の部分と側面の部分との和になる。この
ため、実効的なチャネル幅は従来の場合に比べて側面の
部分だけ大きくなシ、これによりチャネルコンダクタン
スを大きくすることができる。また、ＭＯ８キャノ臂シ
タを形成すれば、実効的なキャパシタンス面積が島状素
子領域の上面の部分と側面の部分との和になる。When a transistor is formed, the effective channel width becomes the sum of the top surface portion and side surface portion of the island-shaped element region. Therefore, the effective channel width is larger only at the side surfaces than in the conventional case, and thereby the channel conductance can be increased. Furthermore, if an MO8 canopy is formed, the effective capacitance area will be the sum of the top surface and side surface portions of the island-like element region.
このため、やはり実効的なキャパシタンス面積は従来の
場合に比べて側面の部分だけ大きくなシ、キャパシタン
ス面積を大きくすることができる。したがって、従来と
同じチャネルコンダクタンス及びキャノ臂シタ容景にお
ｈては孝子形成領域の面積全大幅に狭くすることができ
、素子の微細化及び高密度化をはがシ得る。Therefore, the effective capacitance area is only larger at the side surface area compared to the conventional case, and the capacitance area can be increased. Therefore, while maintaining the same channel conductance and canopy shape as in the prior art, the total area of the diaphragm formation region can be significantly reduced, making it possible to miniaturize and increase the density of the device.
第１図（ａ）〜（ｆ）は本発明の一実施例を説明するた
めの工程断面図である。まず、第１図（ａ）に示す如く
、半導体基板、例えば面方位（１００）比抵抗５〜５０
（Ωｍ〕のＰ型シリコン基板１を用意し、この基板１の
素子形成領域上に厚さ５００ （Ｘ）程度の熱酸化膜２
を介して、シリコン基板１のエツチングのマスクとな多
、かつ後の工程です７トオフ加工全可能にするマスク材
、例えばＡｔ膜３を被着する。次いで、第１図（ｂ）に
示す如＜Ａｔ＠、９をマスクとして素子分離領域（フィ
ールド領域）のシリコン基板１を深さ、例えば１．０Ｃ
μｍ）程麿工、チングして溝部４を形成する。その後、
同じＡｔ膜３をマスクに用いて、フィード領域の溝部４
にフィールド反転防止のためのゼロンのイオン注入を行
ないＰ＋層５をつくる。FIGS. 1(a) to 1(f) are process cross-sectional views for explaining one embodiment of the present invention. First, as shown in FIG.
(Ωm) P-type silicon substrate 1 is prepared, and a thermal oxide film 2 with a thickness of about 500 (X) is provided on the element formation region of this substrate 1.
A mask material, for example, an At film 3, which serves as a mask for etching the silicon substrate 1 and also enables the subsequent process 7, is deposited through the etching process. Next, as shown in FIG. 1(b), using <At@, 9 as a mask, the silicon substrate 1 in the element isolation region (field region) is heated to a depth of, for example, 1.0C.
μm) The groove portion 4 is formed by cutting and cutting. after that,
Using the same At film 3 as a mask, the groove 4 in the feed area is
Then, a P+ layer 5 is formed by implanting zero ions to prevent field reversal.
次に、第１図（ｃ） ＪＣ示す如く段差部に堆積した膜
のエツチング速度が平坦部に堆積した膜のエツチング速
度より速くなる性質を持つ膜、代表的にはプラズマ雰囲
気中で形成したＣＶＤ −５ｌｙ２膜（第１の絶縁膜）
６を例えば１．１〔μｍ〕程度全面に堆積する。次いで
、第１図（ｄ）に示す如く緩衝弗酸液で上記プラズマＣ
ＶＤ −８３０２＆ ６を例えば１分程エツチングする
と、Ｐｌａｓｍａ ＣＶＤ −８ｉ０２膜りの上記性質
により溝部４の側壁部に堆積したプラズマＣＶＤ −８
１０２膜６は選択的忙除去され、溝部側壁のシリコン基
板１と少なくともＡｔ膜３の側壁の一部が露出される。Next, as shown in FIG. 1(c) JC, a film that has the property that the etching rate of a film deposited on a stepped portion is faster than that of a film deposited on a flat portion, typically a CVD film formed in a plasma atmosphere. -5ly2 film (first insulating film)
6 is deposited, for example, on the entire surface to a thickness of about 1.1 [μm]. Next, as shown in FIG. 1(d), the plasma C was removed using a buffered hydrofluoric acid solution.
When VD-8302&6 is etched for about 1 minute, the plasma CVD-8 deposited on the side wall of the groove 4 due to the above-mentioned properties of the Plasma CVD-8i02 film is etched.
The 102 film 6 is selectively removed to expose the silicon substrate 1 on the side wall of the trench and at least a part of the side wall of the At film 3.
このとき、平坦邪に堆積したプラズマＣＶＤ −８１０
２膜６は約１０００（芙〕程度工、チングされ膜厚は１
．０〔μｍ〕程度になる。次に、例えば硫酸と過酸化水
素水との混液で処理するとＡｔ膜３は工、チンチされ同
時にＡｔ膜膜上上堆積していたプラズマＣＶＤ −５Ｉ
Ｏ２膜も除去される。その後、第１図（ｅ）に示す如く
熱酸化膜２を除去すると、溝部４内に素子分離用の酸化
膜（ＣＶＤ −５ｔｏ２膜）６が残置した構造で島状の
素子領域が形成される。このとき、素子形成領域の表面
と素子分離用酸化膜６の表面の高さが略等しくなるよう
にすることがてきる。その後、第１図α）に示す如く素
子形成領域の上面及び側面に薄い酸化膜（第２の酸化膜
）７を形成し、続いて通常の製造工程によ、りＭＯＳＭ
ＯＳキャパシタＳ ）ランジスタ等が作成されることに
なる。At this time, plasma CVD-810 deposited on a flat surface
The second film 6 is etched and etched to a thickness of about 1,000.
．． It becomes about 0 [μm]. Next, when treated with a mixture of sulfuric acid and hydrogen peroxide, for example, the At film 3 is chipped and chipped, and at the same time the plasma CVD-5I deposited on the At film is
The O2 film is also removed. Thereafter, as shown in FIG. 1(e), when the thermal oxide film 2 is removed, an island-shaped element region is formed with a structure in which an oxide film (CVD-5to2 film) 6 for element isolation remains in the trench 4. . At this time, the heights of the surface of the element formation region and the surface of the element isolation oxide film 6 can be made approximately equal. Thereafter, as shown in FIG. 1 α), a thin oxide film (second oxide film) 7 is formed on the top and side surfaces of the element forming area, and then a MOSM is formed by a normal manufacturing process.
OS capacitor S) transistor, etc. will be created.
第２図（ａ）は標準的なダイナミックＲＡＭのセル構造
を示す平面図で、図中８はＭＯＳキャパシタの電極を示
し、９はＭＯＳ ）ランジスタのダート電極ケ示してい
る。FIG. 2(a) is a plan view showing the cell structure of a standard dynamic RAM, in which reference numeral 8 indicates an electrode of a MOS capacitor, and reference numeral 9 indicates a dirt electrode of a MOS transistor.
第２図（ｂ）は同図（、）の矢視Ａ−Ａ断面図で、上記
実施例方法ケ用いて作成したＭＯ８キャノ（シタを示し
ている。映厚ｌｏ ｏ （：ｌ）のシリコン酸化膜７を
用いた一辺が３．４〔μｍ〕の方形のＭＯＳキャパシタ
を考えると、従来の素子分離構造、例えばＢＯＸ法やＲ
ＥＯＸ法を用いた場合にはキャノヤシタンス容曾は４０
［ｆＦ）ＫＬかならなかった。さらに、従来法のＬＯＣ
Ｏ８法を用いた場合は実効的なＭＯＳキャパシタ面積は
バーズビークによシ減少するため、さらにキセノ４シタ
ンス容量は２８．８［ｆＦ］に減少してしまう。しかし
ながら、本実施例方法を用いれば第２図（ｂ） Ｋ示し
たように島状素子領域の表面のみならず側面にもキャパ
シタが形Ｂｙされるため、実効的なキャパシタ面積が増
大して、キャ／ＩＰシタ答量は２倍以上の８７．１〔ｆ
Ｆ〕にもなった。FIG. 2(b) is a cross-sectional view taken along arrow A-A in FIG. Considering a rectangular MOS capacitor with a side of 3.4 μm using the oxide film 7, conventional element isolation structures such as BOX method and R
When using the EOX method, the canopy palm diameter is 40
[fF) KL didn't happen. Furthermore, the LOC of the conventional method
When the O8 method is used, the effective MOS capacitor area is reduced due to the bird's beak, so the xeno4 capacitance is further reduced to 28.8 [fF]. However, if the method of this embodiment is used, the capacitor is formed not only on the surface but also on the side surface of the island-like element region as shown in FIG. 2(b), so the effective capacitor area increases. The answer amount for IP address is more than double 87.1 [f
It also became F.
第２図（ｃ）は同図（ａ）の矢視Ｂ−Ｂ断面図で、上記
実施例方法を用いて作成したＭＯＳ ）ランジスタのチ
ャネル幅方向を示している。例えば従来のＢＯＸ法やＲ
ＥＯＸ法を用いて素子分離を１−［ないチャネル幅１．
０〔μｍ〕、チャネル長さ１．０〔μｍ〕のＭＯＳ ）
ランジスタを形成した場合を仮定すると、同じトランジ
スタを従来のＬＯＣＯ８法で製造すればバーズビークの
ため実効的なチャネル幅は消滅し、チャネルコンダクタ
ンスｇｍは零になる。FIG. 2(c) is a sectional view taken along the line B--B in FIG. 2(a), showing the channel width direction of the MOS transistor fabricated using the method of the above embodiment. For example, the conventional BOX method and R
Element isolation is performed using the EOX method with a channel width of 1-[no channel width.
0 [μm], channel length 1.0 [μm])
Assuming that a transistor is formed, if the same transistor is manufactured using the conventional LOCO8 method, the effective channel width will disappear due to the bird's beak, and the channel conductance gm will become zero.
これに対して本実施例方法を用いれば、第２図（ｃｌに
示したように島状素子領域の表面のみならず側面にもチ
ャネルが形成されるため実効的なチャネル幅が増大して
、チャネルコンダクタンス１ｍは従来ＢＯＸ法又はＲＥ
ＯＸ法の場合の約３倍にもなる。On the other hand, if the method of this embodiment is used, channels are formed not only on the surface but also on the side surfaces of the island-shaped element region, as shown in FIG. Channel conductance of 1m is conventional BOX method or RE
It is about three times as much as in the case of the OX method.
かくして本実施例によれば、島状に分離された素子領域
の島表面のみならず島側面にも例えハＭＯ８キャノ臂シ
タやＭＯＳ ）ランジスタを形成する牢が可能になシ、
上述のようにキャパシタ面積の増大やトランジスタ特性
の改讐をはかることができる。Thus, according to this embodiment, it is possible to form a cell, for example, a MO8 canopy or a MOS transistor, not only on the island surface of the element region separated into islands, but also on the island side surface.
As described above, it is possible to increase the capacitor area and improve transistor characteristics.
第３図（、）〜（ｆ）は他の実施例全説明するための工
程断面図でめる。まず、第３図（ａ）に示す如くＮ型シ
リコン基板１１中にＰウェル１２ｒ形成したのち、基板
１１の表面を酸化し酸化膜１３を形成し、さらにこの酸
化膜１３上にＡｔ膜（マスク材）ｆ４’に蒸着する。続
いて、周知の方法により素子形成領域上の部分を残し、
Ａｔ膜１４及び酸化膜１３を選択的に除去する。次いで
、第３図（ｂ）に示す如く上記Ａｔ膜１４をマスクとし
て基板ノーを選択エツチングしてチー／’Ｐ断面金有す
る溝部１５を形成する。その後、第３図（ｅ）に示す如
（先の実施例と同様に５ＩＯ２膜１６を全面に堆積する
。次いで、希釈した弗酸を用い８１０膜１６を全面エツ
チングすることによシ、第３図（ｄ）に示す如く溝部１
５の側壁の５ｉ０２膜１６’ｊｋ除去する。その後、Ａ
ｔ膜１４を除去することによりＡＡ膜１４上の５ｔＯ２
膜を除去する。次いて酸化膜１３を除去したのち、第３
図（、）に示す如くダート酸化膜（第２の絶縁膜）１７
を形成する。続いて、第３図（ｆ）に示す如く全面に多
結晶シリコン膜１８を堆積する。その後、多結晶シリコ
ン膜１８のノ臂ターニングヲ行い、Ｎチャネルトランジ
スタ、Ｐチャネルトランジスタのソース・ドレイン領域
への不純物拡散、保睦膜形成、電榊取シ出しを行うこと
によってＣ−ＭＯＳインバータが作成されることになる
。FIGS. 3(a) to 3(f) are process sectional views for explaining all other embodiments. First, as shown in FIG. 3(a), a P well 12r is formed in an N-type silicon substrate 11, the surface of the substrate 11 is oxidized to form an oxide film 13, and an At film (mask) is formed on this oxide film 13. Material) Deposit on f4'. Next, a part above the element formation area is left by a well-known method,
The At film 14 and the oxide film 13 are selectively removed. Next, as shown in FIG. 3(b), the substrate layer is selectively etched using the At film 14 as a mask to form a groove portion 15 having a chi/'P cross section. Thereafter, as shown in FIG. 3(e), a 5IO2 film 16 is deposited over the entire surface (as in the previous embodiment).Then, the 810 film 16 is etched over the entire surface using diluted hydrofluoric acid. Groove 1 as shown in figure (d)
The 5i02 film 16'jk on the side wall of 5 is removed. After that, A
By removing the t film 14, 5tO2 on the AA film 14 is removed.
Remove membrane. Next, after removing the oxide film 13, the third
As shown in the figure (,), a dirt oxide film (second insulating film) 17
form. Subsequently, as shown in FIG. 3(f), a polycrystalline silicon film 18 is deposited over the entire surface. Thereafter, the polycrystalline silicon film 18 is turned, the impurity is diffused into the source/drain regions of the N-channel transistor and the P-channel transistor, a protective film is formed, and the electric current is removed, thereby converting the C-MOS inverter. will be created.
かくして本実施例によれば、Ｐウェル１２とＰウェル１
２外に形成場れる各トランジスタのソース若しくはドレ
インとの距離を短くすることができる。さらに、各トラ
ンジスタのチャネル幅も素子形成領域に比して十分大き
くすることができる。したがって、先の実施例と同様に
素子の微細化及び高密度化をはかり得る。Thus, according to this embodiment, P well 12 and P well 1
The distance from the source or drain of each transistor formed outside the transistor can be shortened. Furthermore, the channel width of each transistor can also be made sufficiently larger than the element formation region. Therefore, as in the previous embodiment, it is possible to miniaturize and increase the density of the element.
なお、本発明は上述した各実施例に限定されるものでは
ない。例えば、前記マスク材ｔまＡｔに限るものではな
く、シリコン基板エツチングのマスクとして作用し、か
つその後の１ノフトオフ加工を可能とする衣のであれば
よい。また、溝部に埋め込む絶縁膜はプラズマＣＶＤ
−８１０２膜に限るものでなく、スノ（ツタ蒸着による
５１０２膜、プラズマＣＶＤ −Ｓ １ｓ ／’／ ４
膜、或いはＰＳＧ膜であってもよい。また、ＭＯＳトラ
ンジスタ、５ｔｏｓキャノ’１１シタ或いハＣ−ＭＯＳ
インノぐ一夕に限ら−Ｊ′″、各種の半導体装置に適用
することが可能である。Note that the present invention is not limited to the embodiments described above. For example, the mask material is not limited to the above-mentioned mask material T or At, but any material may be used as long as it acts as a mask for silicon substrate etching and enables subsequent one-noft-off processing. In addition, the insulating film buried in the trench is made by plasma CVD.
-8102 film, but also 5102 film by Suno (ivy deposition), plasma CVD -S 1s/'/4
It may be a film or a PSG film. Also, MOS transistor, 5tos cano'11shita or ha C-MOS
It is possible to apply it to various semiconductor devices only by innovating -J'''.
その他、本発明の要旨を逸脱しない範囲で、植種変形し
て実施することができる。Other modifications may be made without departing from the spirit of the present invention.
第１図（ａ）〜（ｆ）は本発明の一実施例を説明するた
めの工程断面図、第２図（ａ）〜（ｃ）は上記実施例を
用いて作成したダイナミ、りＲＡＭセルを示すもので第
２図（ａ）は平面図、第２図（ｂ）は同図（ａ）の矢視
Ａ−Ａ断面図、第２図（ｅ）は同図（ａ）の矢視Ｂ−Ｂ
断面図、第３図（ａ）〜（ｆ）は他の実施例を説明する
ための工程断面図である。
１．１１・・・シリコン基板、２．１３・・・熱酸化Ｂ
ｎ、３１１４・・・アルミニウム膜（マスク材）、４．
１５°“°溝部、５・・・イオン注入ｊ℃、６．１６・
・・５ｉ０２膜（第１の絶縁膜）、７．１７・・・ダー
ト酸化膜（第２の絶縁膜）、８・・・キャノヤシタ電極
、９．１８・・・ダート電極、１２・・・〆ウエル。
第３図
第３図FIGS. 1(a) to (f) are process cross-sectional views for explaining one embodiment of the present invention, and FIGS. 2(a) to (c) are dynamic RAM cells produced using the above embodiment. Fig. 2(a) is a plan view, Fig. 2(b) is a sectional view taken along the arrow A-A in Fig. 2(a), and Fig. 2(e) is a sectional view taken in the direction of the arrow in Fig. 2(a). B-B
The sectional views and FIGS. 3(a) to 3(f) are process sectional views for explaining another embodiment. 1.11...Silicon substrate, 2.13...Thermal oxidation B
n, 3114...aluminum film (mask material), 4.
15°"°groove, 5...Ion implantation j℃, 6.16.
...5i02 film (first insulating film), 7.17... dirt oxide film (second insulating film), 8... Canoyashita electrode, 9.18... dirt electrode, 12...〆 Well. Figure 3Figure 3
Claims (3)
成された溝部と、仁の溝部に該溝部の側壁が露出するよ
う埋め込まれた第１の絶縁膜と、前記半導体基板の素子
形成領域上及び上記側壁上に形成された第２の絶縁膜と
、この第２の絶縁膜上に被着された電極材料とを具備し
てなることを特徴とする半導体装置。(1) A groove formed by etching an element isolation region on a semiconductor substrate, a first insulating film buried in the groove so that the sidewall of the groove is exposed, and a groove formed on the element formation region of the semiconductor substrate. A semiconductor device comprising: a second insulating film formed on the side wall; and an electrode material deposited on the second insulating film.
る工程と、上記マスク材を用いて上記基板の素子分離領
域を選択エツチングして溝部を形成する工程と、次いで
全面に上記溝部の深さと略同じ膜厚の第１の絶縁膜を堆
積する工程と、段差部に堆積した絶縁膜のエツチング速
度が平坦部に堆積した絶縁膜のエツチング速度より速く
なるエツチング条件て上記第１の絶縁膜をエツチングし
て前記溝部の側壁を露出せしめる工程と、次いで前記マ
スク材を除去することによシ該マスク材上の第１の絶縁
膜を除去して素子形成領域を露出せしめる工程と、上記
臨出した素子形成領域及び前記溝部の側壁に第２の絶縁
膜を形成する工程と、上記第２の絶縁膜上に電極材料を
被着する工程とを具備したことを特徴とする半導体装置
の製造方法。(2) A step of depositing a mask material on the element formation region of the semiconductor substrate, a step of selectively etching the element isolation region of the substrate using the mask material to form a groove, and then a step of forming a groove on the entire surface. The step of depositing a first insulating film having a thickness that is approximately the same as the depth, and the etching conditions such that the etching rate of the insulating film deposited on the stepped portion is faster than the etching rate of the insulating film deposited on the flat portion, are used to form the first insulating film. a step of etching the film to expose the sidewalls of the trench, and then removing the first insulating film on the mask material by removing the mask material to expose the element forming region; A semiconductor device comprising the steps of: forming a second insulating film on the sidewalls of the exposed element formation region and the groove; and depositing an electrode material on the second insulating film. Production method.
したＣＶＤ −５ｔｏ２膜、ス）４ツタ蒸着した５１０
２膜、減圧雰囲気中で形成したＰＳＧ膜、或いはプラズ
マ雰囲気中で形成したＣＶＤ −Ｓｔ、、Ｎ４膜を用い
、そのエツチング法として化学エツチング法を用いたこ
とを特徴とする特許請求の範囲第２項記載の半導体装置
の製造方法。(3) CVD-5to2 film formed in a plasma atmosphere as the first insulating film;
Claim 2, characterized in that a PSG film formed in a reduced pressure atmosphere, or a CVD-St, N4 film formed in a plasma atmosphere is used, and a chemical etching method is used as the etching method. A method for manufacturing a semiconductor device according to section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19637182A JPS5986241A (en) | 1982-11-09 | 1982-11-09 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19637182A JPS5986241A (en) | 1982-11-09 | 1982-11-09 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5986241A true JPS5986241A (en) | 1984-05-18 |
Family
ID=16356742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19637182A Pending JPS5986241A (en) | 1982-11-09 | 1982-11-09 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5986241A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6182458A (en) * | 1984-09-29 | 1986-04-26 | Toshiba Corp | Semiconductor memory device |
| US4679299A (en) * | 1986-08-11 | 1987-07-14 | Ncr Corporation | Formation of self-aligned stacked CMOS structures by lift-off |
| JPH01241868A (en) * | 1988-03-23 | 1989-09-26 | Nec Corp | Semiconductor device |
| US4979014A (en) * | 1987-08-10 | 1990-12-18 | Kabushiki Kaisha Toshiba | MOS transistor |
| JP2001035913A (en) * | 1999-07-16 | 2001-02-09 | Mitsubishi Electric Corp | Semiconductor device and fabrication thereof |
-
1982
- 1982-11-09 JP JP19637182A patent/JPS5986241A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6182458A (en) * | 1984-09-29 | 1986-04-26 | Toshiba Corp | Semiconductor memory device |
| US4679299A (en) * | 1986-08-11 | 1987-07-14 | Ncr Corporation | Formation of self-aligned stacked CMOS structures by lift-off |
| US4979014A (en) * | 1987-08-10 | 1990-12-18 | Kabushiki Kaisha Toshiba | MOS transistor |
| JPH01241868A (en) * | 1988-03-23 | 1989-09-26 | Nec Corp | Semiconductor device |
| JP2001035913A (en) * | 1999-07-16 | 2001-02-09 | Mitsubishi Electric Corp | Semiconductor device and fabrication thereof |
| JP4649006B2 (en) * | 1999-07-16 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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