JPS59745A - Failure detector - Google Patents

Abstract

PURPOSE:To make troubleshooting of the state of a failure and a failed part easy, by inputting respectively each output of a parallel redundant circuit to a separate exclusive OR circuit together with a reference signal for obtaining the OR of the output. CONSTITUTION:A signal 1 passes through redundant circuits 2-4 and outputs 2a-4a are inputted to a 2-out-of-3 circuit 5. Further, the outputs 2a-4a are inputted respectively to one terminal of the exclusive OR circuits 31-33 and a reference signal ircuit 20. The reference signal 20 is inputted to the other terminal of the exclusive OR circuits 31-33. When the redundant circuits 2-4 are normal, a control signal 5a is outputted but no failed signals 31a-33a are outputted. For example, if the circuit 4 is failed, the control signal 5a is outputted as it is, the exclusive OR circuit 33 outputs the signal 33a to activate a display 43, and an OR circuit 17 gives an output to inform the failure. Thus, the troubleshooting of the redundancy circuit is made easy and the repair is performed quickly.

Description

【発明の詳細な説明】 この発明は並列冗長回路を具える装置の故障検出装置に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure detection device for a device including a parallel redundant circuit.

第１図に、この種の装置の従来例を回路図で示す。図に
おいて、１は並列冗長回路の入力信号、２．３及び４は
並列する信号発生回路で、共通の入力信号１に応答して
同一の回路信号（パルス）２ａ。FIG. 1 shows a circuit diagram of a conventional example of this type of device. In the figure, 1 is an input signal of a parallel redundant circuit, 2, 3 and 4 are parallel signal generation circuits, and in response to a common input signal 1, the same circuit signal (pulse) 2a is generated.

３ａ及び４ａｔ夫々発生する。５ｔＪ：２アウトオブ３
回路で構成された出力部でろって、回路信号２ａ。3a and 4at occur respectively. 5tJ: 2 out of 3
The circuit signal 2a is an output section composed of a circuit.

３ａ及び４ａが導かれ、その出力５ａは図示しない回路
装ｒＩｔを制御する為の信号として用いられる。3a and 4a are led, and the output 5a thereof is used as a signal for controlling a circuit device rIt (not shown).

６＃−１故障検出装置でろって、回ＩＮ！ｒ悟号２ａと
３８を受ける排他的崗埋祁素子７９回１６ｏｇ号３ａと
４ａを受ける排他的論理素子８及び回路信号４ａと２ａ
金受ける排他的論理和素子９．併他的繊埋和累子１，８
及び９の夫々の出カフａ、＄ａ及び９ａを結合して故障
信号１０ａを出力する論理和素子１０を具えている。排
他的Ｗｉｉｉ埋叩索子７，８及び９の出力は図示しない
が夫々ラッチして対応する表示素子に導かれる。6#-1 It's time to use the failure detection device! Exclusive logic element 79 times 16 which receives R 2a and 38 Exclusive logic element 8 which receives 3a and 4a and circuit signals 4a and 2a
Exclusive OR element 9. 1, 8
and 9, respectively, and an OR element 10 which combines the output signals a, $a and 9a and outputs a failure signal 10a. Although not shown, the outputs of the exclusive Wii pads 7, 8, and 9 are each latched and guided to the corresponding display element.

？ｙ：、Ｖｃ１　この装置の動作を第２図を参照して説
明する。? y:, Vc1 The operation of this device will be explained with reference to FIG.

信号発生回路２は正常時に入力信号１を受けると第２図
に示す如き時間巾Ｔぴの回路信号２ａを出力する。信号
発生回路３．４についても同様で、正常時には回路信号
２ａと同じ１ａ号を発生するので、排他的論理素子１．
８及び９は何れも出力せず、故障信号１０ａの発生はな
い。When the signal generating circuit 2 receives the input signal 1 during normal operation, it outputs a circuit signal 2a having a time width T as shown in FIG. The same applies to the signal generating circuit 3.4, which generates the same signal 1a as the circuit signal 2a during normal operation, so that the exclusive logic element 1.4 generates the same signal 1a as the circuit signal 2a.
Neither 8 nor 9 output, and no failure signal 10a is generated.

今１１ｇ号発生回Ｗ！？＋が故障して回ｗ！１１ｇ号４
ａが第２図に示す如き誤信号になったものと仮定する。Issue 11g is now occurring W! ? + broke down lol! 11g No. 4
Assume that a has become an erroneous signal as shown in FIG.

信号発生回路４が故障しても、他の２つの信号発生回路
２と３が正常に動作し、夫々発生タイミングと出力中が
同じである所定の回路信号２ａ、３ａを出力するので、
出力部５は正しい入力で制御された信号５ａを発生する
。ところが、故障検出装ｆｆｔ６側では、排他的論理和
菓子８と９に上記誤信号が入力される為、排他的論理ｙ
Ｆｕ累子８は回路信号２ａと上記誤信号の不一致出力期
間に信号８ａを出力し、排他的論理和素子９は回路信号
３ａと上記誤信号の不一致出力期間に信号９ａ’（ｒ出
力し、論理オ０累子１０から故障信号１０ａが発生する
。Even if the signal generation circuit 4 fails, the other two signal generation circuits 2 and 3 operate normally and output the predetermined circuit signals 2a and 3a, which have the same generation timing and output, respectively.
The output section 5 generates a signal 5a controlled by the correct input. However, on the fault detection device fft6 side, the above error signal is input to the exclusive logic Japanese sweets 8 and 9, so the exclusive logic y
The Fu resistor 8 outputs a signal 8a during the mismatch output period between the circuit signal 2a and the above error signal, and the exclusive OR element 9 outputs a signal 9a' (r) during the mismatch output period between the circuit signal 3a and the above error signal. A fault signal 10a is generated from the logic zero register 10.

この従来装置では、上記のようにして故障回路の有無が
検出されるが、回路信号の１が正常でなくなっても２つ
の排他的論理和素子が信号を発生するので、該信号から
だけではどの回路が故障回路でるるかを判別することが
できず、故障回路のユニット交換には手間と時間がか＼
るという欠点がめった。In this conventional device, the presence or absence of a faulty circuit is detected as described above, but since the two exclusive OR elements generate a signal even if 1 of the circuit signal is no longer normal, it is possible to detect the presence or absence of a faulty circuit from only the signal. It is not possible to determine whether a circuit is a faulty circuit, and it takes time and effort to replace the faulty circuit.
The disadvantage is that it is very rare.

この発明は、上記した従来の欠点を除去する為になされ
たもので、回路信号に基づいて基準信号を発生する基準
信号回路を設け、この基準信号と各回路信号との出力期
間を排他的論理和菓子で比較する構成とすることにより
、故障回路音直ちに判別することができる故障検出装ｒ
ｄｔ、ヲ提供することを目的とする。This invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology, and includes a reference signal circuit that generates a reference signal based on a circuit signal, and an exclusive logic that determines the output period of this reference signal and each circuit signal. A failure detection device that can immediately identify the sound of a faulty circuit by comparing it with Japanese sweets.
The purpose is to provide dt, wo.

以下、この発明の一実施例を図について説明する。An embodiment of the present invention will be described below with reference to the drawings.

第３図において、２０ｔｉ基準１ｇ号回路であって、第
４図に示す如き構成の２アウト・オブ・３回路で構成さ
れている。基準信号回路２ｏには回路信号２ａ、３ａ及
び４ａが導かれ、その出力は基準信号２０ａとして用い
られる。第３図において、２１．２２及び２３は論理積
素子、２４は論理和素子でめる。３１は排他的論理和素
子でろって、回路信号２ａと基準信号２０ａｔｌ−受は
両信号の不一致出力期間の間、不一致信号３１ａを発生
する。In FIG. 3, the 20ti standard No. 1g circuit is composed of a 2-out-of-3 circuit as shown in FIG. Circuit signals 2a, 3a, and 4a are led to the reference signal circuit 2o, and the output thereof is used as the reference signal 20a. In FIG. 3, 21, 22 and 23 are AND elements, and 24 is an OR element. 31 is an exclusive OR element which receives the circuit signal 2a and the reference signal 20atl and generates a mismatch signal 31a during a mismatch output period of both signals.

３２は排他的論理和素子であって、回路信号３ａと基準
信号ＺＵａを設け、両信号の不一致出力期間の間、不一
致信号３２ａｔ−出力する。３３は排他的論理和素子で
るって、回路信号４ａと基準信号２０３會受け、両信号
の不一致出力期間の間、不一致信号３３ａｔ出力する。Reference numeral 32 denotes an exclusive OR element, which is provided with the circuit signal 3a and the reference signal ZUa, and outputs a mismatch signal 32at- during a mismatch output period of both signals. 33 is an exclusive OR element which receives the circuit signal 4a and the reference signal 203 and outputs a mismatch signal 33at during a mismatch output period of both signals.

不一致信号３１ａ、３２ａ及び３３ａは論理和素子１０
に人力されると共に、夫々対応する故障表示回路４１．
４２及び４３に導かれる。The mismatch signals 31a, 32a and 33a are output from the OR element 10.
and the corresponding failure display circuits 41.
42 and 43.

次に、この装置の動作金弟５図を参照して説明する。Next, the operation of this device will be explained with reference to Figure 5.

信号発生回路２が正常に動作している場合には、入力信
号１に応答して第５図に示す回路信号２８を出力する。When the signal generating circuit 2 is operating normally, it outputs a circuit signal 28 shown in FIG. 5 in response to the input signal 1.

他の信号発生回路３と４も正常動作時には回路信号２ａ
と同じタイミングで同じ時間巾の信号を発生する。この
為、基準信号２Ｌｌａと回路信号２ａ、３ａ及び斗ａは
タイミング及び時間巾において一致し、不一致信号３１
ａ、３２ａ及び３３ａは発生せず、故障信号１０ａの発
生はない。しかし、信号発生回路４だけが故障して回路
信号４ａが第５ばに示す如き誤信号４ｂとなった場合は
、排他的論理和菓子３１．３２は不一致信号３１ａ＠３
２ａを発生しないが、排他的論理和菓子３３が不一致信
号３３ａを出力するので、故障信号１υａが発生すると
共に、故障した信号発生回路４に対応する故障表示回Ｎ
Ｚ＋３だけが点灯動作する。Other signal generating circuits 3 and 4 also generate circuit signal 2a during normal operation.
A signal with the same time width is generated at the same timing as . Therefore, the reference signal 2Lla and the circuit signals 2a, 3a, and dooa match in timing and time width, and the mismatch signal 31
a, 32a, and 33a are not generated, and the failure signal 10a is not generated. However, if only the signal generating circuit 4 fails and the circuit signal 4a becomes an error signal 4b as shown in the fifth example, the exclusive logic Japanese confectionery 31.32 becomes the mismatch signal 31a@3.
2a is not generated, but the exclusive logic Japanese confectionery 33 outputs the mismatch signal 33a, so the failure signal 1υa is generated and the failure indication time N corresponding to the failed signal generation circuit 4 is generated.
Only Z+3 lights up.

なお、この実施例でｅま、基１１！ｉｇ号回路２０を設
けているが、出力部５が２アウト・オン３回路で構成さ
れている場合には、出力部５の出力を基準信号として用
いることができる。In addition, in this example, e is the group 11! Although the ig circuit 20 is provided, if the output section 5 is composed of 2-out/on-3 circuits, the output of the output section 5 can be used as a reference signal.

以上の如く、この発明によれば、回路信号が人力され該
入力中に同じ信号がある礪曾にこれｔ−基＄１ｇ号とし
て出力する基準１ｄ号回路を設け、回路信号の各々を排
・池的論理オ０累子で上記基準信号と比較しその結果を
夫々対応する故障表示回路に導く構成としたことによシ
、回路信号の一つが正常信号でなくなった場合にこれ倉
出力した故障回路を正確に知ることができるので故障回
＠ヤニニット交侯や基板変換を故障回路検出後すみやか
に行うことができる。As described above, according to the present invention, a reference number 1d circuit is provided to output a circuit signal as a t-base $1g number for each circuit where a circuit signal is manually input and the same signal is present in the input, and each of the circuit signals is excluded and outputted. The structure is such that it compares with the above-mentioned reference signal using logical logic and directs the results to the corresponding fault display circuits, so that when one of the circuit signals is no longer a normal signal, this signal is output as a fault signal. Since the circuit can be known accurately, fault circuit crossing and board conversion can be performed promptly after detecting a faulty circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の故嘩慣出装置のブロック図、第２図は上
記故障検出装置のｇｒＪＪ作を説明する為の波形タイム
チャート、第３図はこのに明による故障検出装置の実Ｉ
Ｍ列のブロック図、第４図は上記実流例における基準１
６号回路の回路図、第５図は上記実ノ油列の動作を説明
゛ｒる為の波形タイムチャートでるる。 図において、２０・・・基準信号回路、３１．３２．３
３・・・ａ池的崗理叩素子、４１．４２．４３−・・故
＊表示回路。 なお、図中、同一符号は同−ｙ、は相当部分金示す。 代理人　　　葛　野　信　− 第１図 第２図 ０ ＩＯα 第３図 ２７１− 第４図 第す図 ００ 特許庁長官殿 １．事件の表示　　　特願昭　５７−９１＋’＋５３号
３、補正をする者 代表者片山仁へ部 明細書の発明の詳細な説明の欄 ６、　補正の内容 （１）明細書の第２頁第５行の「排他的論理和素子８」
を「排他的論理和素子９」と訂正する。 （２）同第２頁第６行の「排他的論理和素子９」を「排
他的論理和素子８」と訂正する。 （３）同第３頁第１４行の「回路信号の１が」を１回路
信号の１つが」と訂正する。 （４）同第５頁第４行の「論理和素子１０に」を「論理
和素子１６に」と訂正する。 以上Fig. 1 is a block diagram of a conventional fault detection device, Fig. 2 is a waveform time chart for explaining the failure detection device made by grJJ, and Fig. 3 is an actual failure detection device according to this invention.
The block diagram of the M column, Figure 4, is the standard 1 in the above actual flow example.
The circuit diagram of circuit No. 6, FIG. 5, is a waveform time chart for explaining the operation of the above-mentioned actual oil train. In the figure, 20... reference signal circuit, 31.32.3
3...a-like logic element, 41.42.43-...display circuit. In addition, in the figure, the same reference numerals are the same - y indicate corresponding amounts of gold. Agent Makoto Kuzuno - Figure 1 Figure 2 0 IOα Figure 3 271- Figure 4 Figure 00 Commissioner of the Japan Patent Office 1. Indication of the case: Japanese Patent Application No. 57-91+'+53 No. 3, Detailed explanation of the invention in the specification, column 6, Detailed explanation of the invention in the specification of the person making the amendment, Representative Hitoshi Katayama, Contents of the amendment (1) Page 2 of the specification, No. 5 "Exclusive OR element 8" in row
is corrected to "exclusive OR element 9". (2) Correct "Exclusive OR element 9" in the 6th line of the second page to "Exclusive OR element 8." (3) On page 3, line 14, ``1 of the circuit signals'' is corrected to ``one of the 1 circuit signals''. (4) In the fourth line of page 5, correct "to OR element 10" to "to OR element 16". that's all

Claims (1)

【特許請求の範囲】[Claims] 並列冗長回路の各回路信号を夫々１つの人力とし、基準
信号回路が出力する基準信号を他の１つの入力とする排
他的論理和素子、該排他的論理和素子の出力が夫々導か
れる故障表示回路を具え、上記基準信号回路が、上記各
回路信号を受は入力中に同じ信号がめる場合にこれを基
準信号として出力することを特徴とする故障検出装置。An exclusive OR element which uses each circuit signal of the parallel redundant circuit as one input and a reference signal output from the reference signal circuit as another input, and a failure indication from which the output of the exclusive OR element is respectively derived. A failure detection device comprising a circuit, wherein the reference signal circuit receives the respective circuit signals and outputs the same signal as a reference signal when the same signal is received during input.