JPS5968958A - Gate turn-off thyristor assembled body - Google Patents

Gate turn-off thyristor assembled body

Info

Publication number
JPS5968958A
JPS5968958A JP57180402A JP18040282A JPS5968958A JP S5968958 A JPS5968958 A JP S5968958A JP 57180402 A JP57180402 A JP 57180402A JP 18040282 A JP18040282 A JP 18040282A JP S5968958 A JPS5968958 A JP S5968958A
Authority
JP
Japan
Prior art keywords
gate turn
thyristor
gate
cathode
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57180402A
Other languages
Japanese (ja)
Inventor
Kozo Yamagami
山上　倖三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57180402A priority Critical patent/JPS5968958A/en
Priority to DE19833336979 priority patent/DE3336979A1/en
Publication of JPS5968958A publication Critical patent/JPS5968958A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To improve the assembly workability by reducing a wiring inductance component by containing a GTOSCR and a fly-wheel diode into the same outer container. CONSTITUTION:The GTOSCR10 and the fly-wheel diode 20 are soldered 32 on a copper plate 33 with metallized layers 11 and 12 of an anode and a cathode respectively. For the element 20, the one of a small reverse recovery current can be used. The copper plate 33 is soldered 34 on a metallized layer 35a of an alumina substrate 35, and further soldered 36 on a heat dissipating plate 37 by means of a metallized layer 35b. The anode external main terminal 38 of the SCR is provided in connection to the copper plate 33, a cathode plate 39b of a copper and a gate electrode plate 40b are soldered on the alumina substrate 35, and external main terminals 39 and 40 are provided in connection to the plates 39b and 40b respectively. The chips 10 and 20 are arranged in proximity, and metallized electrodes 12, 13, and 22 of each are connected 30 to the electrodes 39b and 40b as fixed. At this time, the connection length is shortened; therefore the leap voltage at the time of ''off'' of the SCR reduces, and there is no outer installation of the diode, and then the assembly workability improves.

Description

【発明の詳細な説明】 この発明は同一外装容器内に逆並列接続されたフライホ
イルダイオードを有するゲートターンオフサイリスタ組
立体に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate turn-off thyristor assembly having flywheel diodes connected in antiparallel in the same housing.

現在、省資源、省エネルギー化への対応は社会的使命と
なっている。これに対応するためパワーエレクト「」ニ
クスの分野では新機能素子の開発・実現により、その需
要が急増する傾向にある。最近とくに、インバータ、チ
ョッパ回路に用いられる素子としてゲートターンオフサ
イリスクが脚光をあびるようになってきている。この理
由としては、ゲートターンオフサイリスクが従来のトラ
ンジスタや高速スイッチングサイリスタのいずれにも優
り、スイッチング素子として理想的な特長をもっている
ことである。即ち、その大きな特長としては、■自己遮
断能力を持っている。　■僅かな制御電力で素子のオン
・オフ制御ができる。Currently, resource and energy conservation has become a social mission. In response to this, the demand for new functional devices in the field of power electronics is rapidly increasing due to the development and realization of new functional devices. Recently, gate turn-off circuits have been attracting attention especially as elements used in inverters and chopper circuits. The reason for this is that the gate turn-off thyristor is superior to both conventional transistors and high-speed switching thyristors, making it ideal as a switching element. That is, its major feature is ① self-shutoff ability. ■On/off control of elements is possible with a small amount of control power.

■高耐圧、大電流の素子が作り易い。　■ブージ電流耐
量がサイリスク並みの耐量を持っている。■Easy to create high voltage and large current devices. ■Booge current withstand capacity is comparable to Cyrisk.

■ターンオフ時間の短かいものが得られる。　などがあ
げられる。現在、ゲートターンオフサイリスタの主な応
用分野は、電動力応用を主体とした産業機器やインバー
タ等の電力変換機器および電源装置などである。■A short turn-off time can be obtained. etc. Currently, the main application fields for gate turn-off thyristors are industrial equipment mainly for electric power applications, power conversion equipment such as inverters, and power supplies.

ゲートターンオフサイリスタチップの構造は、基本的に
は一般のサイリスタの構造と同じである。The structure of the gate turn-off thyristor chip is basically the same as that of a general thyristor.

第１図はその構造を示す断面図で、同図のｏＱに示され
るように低不純物濃度のｎ形シリコン単結晶基板からな
るｎ形ベース層（１０１）　、ｎ形シリコン単結晶基板
の両面からガリウムやポロンなどのｐ形不純物を比較的
高濃度に拡散して形成てれたＰ形エミッタ層（１０２）
及びＰ形ベース層（１０３）　、並びに、ｐ形ベース層
（１０３）の部分的領域にリンなどのｎ形不純物をより
高澁度になるように選択的に拡散して形成されたｎ形エ
ミッタ層（１０４）のｐｎｐｎ四鳩構造からなる。（＋
１）、　（＋２）　ｒ　Ｏ萄ｔま夫々ｐ形エミンタ層（
１０２）　、　ｐ形ベースＮ　（１０３）、　ｎ形エミ
ッタ層（１０４）の各表面層にオーミック接触する陽極
メタライズ電極、ゲートメタライズ電極、陰極メタライ
ズ層極でオシ、その形成方法としては一般にＡＡを蒸着
して形成される。ゲートターンオフサイリスクの電圧（
ｖ）・電流（１）特性は第２図に示すように一般のサイ
リスタと全く同じ特性を示す。Figure 1 is a cross-sectional view showing its structure. As shown by oQ in the figure, an n-type base layer (101) made of an n-type silicon single crystal substrate with a low impurity concentration is formed from both sides of the n-type silicon single crystal substrate. P-type emitter layer (102) formed by diffusing p-type impurities such as gallium and poron at a relatively high concentration.
and a P-type base layer (103), and an n-type emitter formed by selectively diffusing n-type impurities such as phosphorus into a partial region of the p-type base layer (103) to a higher degree. The layer (104) consists of a pnpn four-dove structure. (+
1), (+2) p-type emitter layer (
102) An anode metallized electrode, a gate metallized electrode, and a cathode metallized layer that are in ohmic contact with the surface layers of the p-type base N (103) and the n-type emitter layer (104) are generally formed by vapor deposition of AA. It is formed by Gate turn-off voltage (
v)・Current (1) As shown in FIG. 2, the characteristics are exactly the same as those of a general thyristor.

順方向の特性、即ち陰極に対し陽極が正の電位になるよ
うに電圧を印加した場合、ある電圧まで電流が１１とん
ど流れない領域（順阻止領域）とある電圧を越えると導
通しダイオードの順方向特性と同様な特性を示す領域（
導通領域）と阻止状態から導通状態に移行する領域（遷
移領域）とが存在する。ここでいうめる電圧とは、第２
図でｖＢｏの記号で示される電圧でブレークオーバ電圧
と呼ばれる。“また、逆方向の特性、即ち陽極に対し陰
極が正の電位になるように電圧を印加した場合、ある電
圧ｖＢＩ）！ｌ：では電流がほとんど流れない領域（逆
阻止領域）とめる電圧ｖＢＤを越えると電流が増える領
域（なだれ降伏領域）とがある。この電圧ｖＢＤはブレ
ークダウン（降伏）電圧と呼ばれる。Forward characteristics, that is, when a voltage is applied so that the anode has a positive potential with respect to the cathode, there is a region (forward blocking region) where no current flows up to a certain voltage, and a diode that becomes conductive when the voltage exceeds a certain voltage. A region that exhibits characteristics similar to the forward characteristics of (
There are two regions: a conduction region) and a region transitioning from a blocked state to a conduction state (transition region). The voltage referred to here is the second
The voltage indicated by the symbol vBo in the figure is called the breakover voltage. "Also, if we apply a voltage so that the negative electrode has a positive potential with respect to the anode, we can calculate the voltage vBD that stops the region where almost no current flows (reverse blocking region). There is a region (avalanche breakdown region) where the current increases when exceeded.This voltage vBD is called the breakdown voltage.

このブレークオーバ電圧■Ｂｏとブレークダウン電圧ｖ
ＢＤとはゲートターンオフサイリスタの構造によって決
まるものである。次にゲートターンオフサイリスタの陽
極と陰極との間に順方向にブレークオーバ４圧ＶＢ。以
下の電圧ＶＤが印加された状態、いわゆるオフ状態から
オン状態へ移行させる一つの方法で最も一般的な方法と
してゲート・陰極間に順方向のゲート電流を流す方法が
とられる。This breakover voltage ■Bo and breakdown voltage v
BD is determined by the structure of the gate turn-off thyristor. Next, there is a forward breakover voltage of 4 VB between the anode and cathode of the gate turn-off thyristor. One of the most common methods for transitioning from a state where the following voltage VD is applied, a so-called off state, to an on state is to flow a forward gate current between the gate and the cathode.

第２図に示すように順方向のゲート電流を工。１く工。The forward gate current is adjusted as shown in Figure 2. 1 work.

２く工。３く工。４と増やしていくと、ブレークオーバ
電圧ｖＢｏは漸次低下し、陽極・陰極間への外部＃ｊ加
加力方向電圧Ｄより低くなるとオン状態に移行する。第
２図の場合、ゲート電流工。２を流すことによってオン
状態に移行させることができる。一般のサイリスタでは
オフ状態からオン状態忙いったん移行すると、ゲートは
制御機能を失ってしまい、陽極・陰極間への外部印加順
方向電圧ＶＤを零にするか、順方向（オン）電流の値を
保持電流値以下に下げてやる心安がある。これに対しゲ
ートターンオフサイリスタでは、ゲートと陰極との間に
陰極からゲートの方向に電流、即ちゲート逆電流を流す
ことによってオン状態からオフ状態に移行（遮断）でき
るものであり、一般のサイリスタに比し大きな特長を有
しているといえる。このように、ゲートターンオフサイ
リスクがゲート逆電流によシ遮断能力を有するようにす
るために、その構造上釉々な工夫がなされている。例え
ばゲート電極と陰極電極を互いに入シ組んだ櫛！目状構
造にしたり、ｐ形エミッタＮ（１０２）とｎ形ベース層
（１０１）とを表面の陽極メタライズ層（直りで短絡し
く図示せず）、ｐ形エミッタ層（１０２）がら・ｎ・形
さ一ス層（１０１）への正孔の注入を抑える構造にした
り、ｐ形成−ス層（１０３）の横方向抵抗を小さくする
工夫などが行われている。2 work. 3 work. When the voltage is increased to 4, the breakover voltage vBo gradually decreases, and when it becomes lower than the voltage D in the direction of external #j applied between the anode and the cathode, it shifts to the on state. In the case of Figure 2, it is the gate electric current. By flowing 2, it is possible to shift to the on state. In a general thyristor, once the gate transitions from the off state to the on state, the gate loses its control function, and the externally applied forward voltage VD between the anode and cathode must be reduced to zero, or the value of the forward (on) current must be reduced. It is safe to lower the current below the holding current value. On the other hand, gate turn-off thyristors can be switched from the on state to the off state (blocked) by flowing a current between the gate and the cathode in the direction from the cathode to the gate, that is, a gate reverse current. It can be said that it has great features compared to other models. As described above, in order to make the gate turn-off risk capable of blocking the gate reverse current, various improvements have been made to its structure. For example, a comb with a gate electrode and a cathode electrode intertwined with each other! The p-type emitter N (102) and the n-type base layer (101) can be formed into a mesh-like structure by forming an anode metallized layer on the surface (not shown because it is straightened and short-circuited), and a p-type emitter layer (102) with an n-type structure. Efforts have been made to create a structure that suppresses the injection of holes into the source layer (101) and to reduce the lateral resistance of the p-type layer (103).

ゲートターンオフサイリスクがインバータ回路やチョッ
パ回路等に用いられる場合、通常第３図に示すよう釦、
ゲートターンオフサイリスクＧＴＯＩＵりと逆並列にフ
ライホイルダイオードＤＦＩ（２０）が取付けられると
共に第２図の点線で示すようにダイオードＤ８と抵抗Ｒ
８とコンデンサｃ８とで構成されたスナバ−回路が陽極
Ａｌと陰極に１との間に接続される。スナバ−回路を用
いる目的は２つあシ、そのＪつはゲートターンオフサイ
リスクをターンオンさせるとき、今まで、ゲートターン
オフサイリスクを流れていた電流をスナバ−回路にバイ
パスさせゲートターンオフサイリスクを流れる電流を速
やかに減少させ、ゲートターンオフサイリスタ内の発生
損失を軽減させることであシ、また他の１つはゲートタ
ーンオフサイリスタのターンオフ時の再点弧防止の為に
ターンオフ時の電圧上昇率をある値以下に押えることで
ある。ゲートターンオフサイリスタのターンオフ時には
飛閂電圧が印加される。第２図に示すゲートターンオフ
サイリスタがインバータ回路に適用された場合を例にと
って説明する。第４図にインバータ１相分を示し、第５
図はターンオフ時の各部電圧波形を示す。When gate turn-off circuits are used in inverter circuits, chopper circuits, etc., there are usually buttons,
A flywheel diode DFI (20) is installed antiparallel to the gate turn-off switch GTOIU, and a diode D8 and a resistor R are connected as shown by the dotted line in Figure 2.
A snubber circuit consisting of a capacitor c8 and a capacitor c8 is connected between the anode Al and the cathode 1. There are two purposes for using a snubber circuit. When turning on the gate turn-off circuit, the current that previously flowed through the gate turn-off circuit is bypassed to the snubber circuit and flows through the gate turn-off circuit. This is to quickly reduce the current and reduce the loss generated in the gate turn-off thyristor.The other is to reduce the voltage rise rate at turn-off in order to prevent the gate turn-off thyristor from re-igniting when it is turned off. The goal is to keep it below that value. A jump voltage is applied when the gate turn-off thyristor is turned off. An example in which the gate turn-off thyristor shown in FIG. 2 is applied to an inverter circuit will be explained. Figure 4 shows one phase of the inverter.
The figure shows the voltage waveforms at various parts during turn-off.

ＶＡＫはゲートターンオフサイリスタに印加される電圧
、八はゲートターンオフサイリスクを流れる１−ｕ流、
１８．ｉ、、ｉＬはそれぞれスナバ−回路、フライホイ
ルダイオードおよび負荷に流れる電流である。第５図の
ｖＡＫの波形に示されたΔＶが飛躍電圧で、その値は次
式（１）で表わされる。VAK is the voltage applied to the gate turn-off thyristor, 8 is the 1-u current flowing through the gate turn-off thyristor,
18. i, , iL are currents flowing through the snubber circuit, flywheel diode, and load, respectively. ΔV shown in the waveform of vAK in FIG. 5 is a jump voltage, and its value is expressed by the following equation (1).

ここに、ＬＴ＝ｔ３＋ｔ４＋ｔ５＋ｔ６＋ｔ７＋ｔ８で
示され、ｔ３゜ｔ４はスナバ−回路、１５．１６は主回
路、Ｌ７．ｔ８はフライホイルダイオード回路の各配線
のインダクタンス成分である。ゲートターンオフサイリ
スタに印加される飛躍電圧ΔＶは素子の耐圧に関係し△
■を極力小さく押えることが重要である。この飛躍電圧
Δ■を小さく押え、るためには第４図の図中にｉ３．ｔ
４．ｔ５．ｔ６．ｔ７．ｔ８で示す上記各配線のインダ
クタンスを小さくすることが必要である。Here, LT=t3+t4+t5+t6+t7+t8, t3°t4 is the snubber circuit, 15.16 is the main circuit, L7. t8 is an inductance component of each wiring of the flywheel diode circuit. The jump voltage ΔV applied to the gate turn-off thyristor is related to the withstand voltage of the element.
It is important to keep ■as small as possible. In order to keep this jump voltage Δ■ small, i3. t
4. t5. t6. t7. It is necessary to reduce the inductance of each of the above wirings indicated by t8.

従来のゲートターンオフサイリスクではフライホイルダ
イオードが同一外装容器内に組込まれていないことから
フライホイルダイオードが外付となり必然的に配線が長
くなり、フライホイルダイオードの配線のインダクタン
ス成分ｔ７．ｔ８が大きくなり飛躍電圧ΔＶが大きくな
ること、また、フライホイルダイオードを外付けする必
要があり、取付けのだめのスペースを必要とすること、
さらに小畑なスペース内での外付は作業を要することか
ら作業性が愁くなるなどの欠点があった。In conventional gate turn-off circuits, the flywheel diode is not built into the same outer container, so the flywheel diode is attached externally, which inevitably results in longer wiring, and the inductance component t7 of the flywheel diode wiring. As t8 increases, the jump voltage ΔV increases, and it is necessary to attach a flywheel diode externally, which requires additional space for installation.
Furthermore, external installation within a small space requires work, which has the disadvantage of poor workability.

この発明はこれら従来の欠点に鑑みてなされたもので、
フライホイルダイオードを同一外装容器内に内蔵するこ
とにより、配線のインダクタンス成分１７．１８を小さ
く押え飛躍電圧を小さくできること、又、フライホイル
ダイオード内蔵することによって、外付けの場合のよう
にスペースを必要としないことや、外付作業が不要とな
シ作業性を良好ならしめることのできるゲートターンオ
フサイリスタ組立体を提供することを目的としている。This invention was made in view of these conventional drawbacks.
By incorporating the flywheel diode in the same outer container, the inductance component of the wiring (17.18) can be kept small and the jump voltage can be reduced. Also, by incorporating the flywheel diode, it does not require the same space as when installing it externally. It is an object of the present invention to provide a gate turn-off thyristor assembly that does not require any external work and has good workability.

第６図はこの発明の一実施例の半導体チップ部の構成を
示す断面図、第７図はこの実施例の組立て構造を理解し
易くするために外装容器の樹脂などの上部ケース部分及
びコーティング樹脂部分を除いて示す斜視図である。す
なわち、この実施例は第３図の一点鎖線で囲んだ部分（
１００）を１個の外装容器に組み込んだものである。ゲ
ートターンオフサイリスタチップαＱとフライホイルダ
イオードチップ（社）とが銅板を加工成形した共通電極
金属板に）の上にそれぞれ陽極メタライズ電極（１１）
および陰極メタライズ電極に）が半田などの低融点ろう
材で融着される。フライホイルダイオード四は低不純物
濃度のｎ形シリコン単結晶基板からなるｎ層（２０１）
と、これにガリウムやボロンなどのｐ形不純物を比較的
高不純物濃度になるように拡散して形成でれた９層（２
０２）、およびｎ層（２０１）の表面層にオーミック接
触形成のためにリンなどのｎ形不純物を比較的高濃度に
拡散形成されたｎ”７ｍ２０１ａ）を備えており、Ｑυ
はｎ　Ｍ！Ｊ　（ｚｏｌ）の表面ｎ層層（２０１１Ｌ）
にオーミンク接触する陰極メタライズ電極、に）は９層
（２０２）の表面にオーミック接触する陽極メタライズ
電極である。フライホイルダイオード四の電圧（ｖ）・
電流ＣＩ）特性は通常のダイオードと同じであるが、逆
回復電流の小さいもの、即ち／・イリカバリのものが有
効であり用いられる。FIG. 6 is a cross-sectional view showing the structure of a semiconductor chip section according to an embodiment of the present invention, and FIG. 7 is a cross-sectional view showing the upper case portion such as the resin of the outer container and the coating resin to make it easier to understand the assembled structure of this embodiment. FIG. 3 is a perspective view with some parts removed. That is, in this embodiment, the part (
100) is assembled into one outer container. The gate turn-off thyristor chip αQ and the flywheel diode chip (Co., Ltd.) are placed on a common electrode metal plate made from a copper plate), respectively, and an anode metallized electrode (11) is placed on top of the common electrode metal plate.
and the cathode metallized electrode) are fused with a low melting point brazing material such as solder. Flywheel diode 4 is an n-layer (201) made of an n-type silicon single crystal substrate with a low impurity concentration.
Then, nine layers (2
Qυ
Ha n M! J (zol) surface n layer (2011L)
(2) is a cathode metallized electrode that is in ohmic contact with the surface of the 9th layer (202), and is an anode metallized electrode that is in ohmic contact with the surface of the 9th layer (202). Flywheel diode voltage (v)・
Although the characteristics (current CI) are the same as those of ordinary diodes, those with a small reverse recovery current, that is, those with an irrecoverable current are effective and are used.

共通電極金属板（至）は半田などの低融点ろう材■によ
って、アルミナからなる絶縁基板曽の上面のメタライズ
形成部（３５ａ）に融着される。また、絶縁基板に）の
下面のメタライズ形成部（３５ｂ）は半田などの低融点
ろう材（７）によって金属板などからなる放熱板（ロ）
に融着される。The common electrode metal plate (1) is fused to the metallized portion (35a) on the upper surface of the insulating substrate made of alumina using a low melting point brazing material such as solder. In addition, the metallized portion (35b) on the lower surface of the insulating substrate is bonded to a heat dissipation plate (b) made of a metal plate or the like by using a low melting point brazing material (7) such as solder.
is fused to.

第７図において、に）は共通電極金属板に）と連なって
形成されたゲートターンオフサイリスタの陽極外部主端
子、（３８５Ｌ）はこれに設けられた外部配線接続孔で
ある。また、前記アルミナ絶縁基板に）の両端部の上面
のメタライズ部の上にはそれぞれ銅板を加工成形した陰
極電極板（ｓ９ｂ）およびゲート電極板（４ｏｂ）が半
田などの低融点ろう材で融着される。陰極電極板（ｚ９
ｂ）には陰極外部主端子四が連なって形成され、陰極外
部主端子ＩＪＩＫは外部配線接続孔（３９ａ）が設けら
れている。また、ゲート電極板（４０ｂ）にはゲート外
部端子−が連なって形成され、ゲート外部端子（６）に
は外部配線接続孔（４０ａ）が設けられている。In FIG. 7, (3) is an anode external main terminal of a gate turn-off thyristor formed in series with () on the common electrode metal plate, and (385L) is an external wiring connection hole provided therein. In addition, on the metallized portions on the top surface of both ends of the alumina insulating substrate, a cathode electrode plate (s9b) and a gate electrode plate (4ob), each made of a copper plate, are fused using a low melting point brazing material such as solder. be done. Cathode electrode plate (z9
In b), cathode external main terminals 4 are formed in a row, and the cathode external main terminal IJIK is provided with an external wiring connection hole (39a). Furthermore, gate external terminals are formed in a row on the gate electrode plate (40b), and external wiring connection holes (40a) are provided in the gate external terminals (6).

ゲートターンオフサイリスクチツブ叫とフライボイルダ
イオードチップ（２０）とは第６図及び第７図に示され
るよう傾、共通電極金属板に）の上に近接するように配
置式れ融着される。この目的はゲートターンオフツーイ
リスタテツブαＱの陰極メタライズ電極０３）とフライ
ホイルダイオードテンブレ０）の陽極メタライズ電極（
４）との間の内部配線（７）の長式及びゲートターンオ
アサイリスタテップ（Ｉｔ、）の陽極メタライズ電極（
０）とフライホイルダイオードチップ（２０）の陰極メ
タライズ電極■υとの間の共通電極金属板に）の長さを
極力短かくし配線部のインダクタンスを小さくするため
である。なお、内部配線に）はゲートターンオフブイリ
スタテツブα０の陰極Ａ４メタライズ電極（１３）とフ
ライホイルダイオ−トチツブシ０）の陽極Ａｔメタライ
ズ電極に）と陰極電極板（３９ｂ）との間をＡｔワイヤ
を用いて超音波溶接して電気的接続配線される。また、
ゲートＡｔメタライズ′１１ｉ極（１匂とゲート電極板
（４ｏｂ）との間も同様にＡ／−ワイヤＧ３］）を用い
て超音波溶接して電気的に接続される。A gate turn-off silicon chip and a flyboil diode chip (20) are positioned and fused in close proximity to the common electrode metal plate, tilted as shown in FIGS. 6 and 7. The purpose of this is the cathode metallized electrode (03) of the gate turn-off resistor block αQ and the anode metallized electrode (03) of the flywheel diode template (0).
4) of the internal wiring (7) and the anode metallized electrode of the gate turn-or-thyristor step (It,) (
This is to minimize the length of the common electrode metal plate between the metallized cathode electrode ■υ of the flywheel diode chip (20) and the cathode metallized electrode ■υ of the flywheel diode chip (20) to reduce the inductance of the wiring part. In addition, an At wire is connected between the internal wiring (to the cathode A4 metallized electrode (13) of the gate turn-off block α0 and the anode At metallized electrode of the flywheel diode (0)) and the cathode electrode plate (39b). Electrical connections are made using ultrasonic welding. Also,
Electrical connection is made by ultrasonic welding using the gate At metallized electrode (A/- wire G3 between the gate electrode plate (4ob) and the gate electrode plate (4ob)).

次にこの発明の他の実施例として２個のゲートターンオ
フサイリスタテツブが１つの外装容器に直列接続され組
込まれたゲートターンオフサイリスクモジュールの例に
ついて第８図、第９図について説明する。第８図にはこ
の実施例のゲートターンオフサイリスタモジュールの等
価回路を示す。Next, as another embodiment of the present invention, an example of a gate turn-off thyristor module in which two gate turn-off thyristor tubes are connected in series and built into one outer container will be described with reference to FIGS. 8 and 9. FIG. 8 shows an equivalent circuit of the gate turn-off thyristor module of this embodiment.

２個のゲートターンオフサイリスタＧＴＯＩ　ＧＴＯ２
が１Ｌ列接続され、各々のゲートターンオフサイリスク
に逆並列接続になるようにフライホイルダイオードＤＰ
Ｉ、ＤＦ２が接続される。第８図九一点鎖線で示す部分
（２００）が第９図の１つの外装に組込まれる部分を示
す。曽は２個のゲートターンオフサイリスタＧＴＯ１と
ＧＴＯ２との共通主電極外部端子で、ＧＴＯＩの陽極電
極とＧＴＯ２の陰極電極との共通電極として形成される
。陶は一方のゲートターンオフサイリスタ（ＧＴＯｌ）
の陰極主電極外部端子、（３８０）は他のゲートターン
オフサイリスタ（ＧＴＯ２）　ノ陽極主電極外部端子、
（３９ｃ　）　オＪ：　Ｕ　ＧｌＯはゲートターンオフ
′ｙ−イリスタ（Ｇ’［’０１）の制御用のそれぞれ陰
極外部端子およびゲート電極外部端子、丑だ、同様に（
３９ｏｃ）および（４ｏｏ）は他のゲートターンオフサ
イリスタ（’ＧＴＯ２）の制御用のそれぞれ陰極外部端
子およびゲート電極外部端子である。このゲートターン
オフサイリスタモジュールをインバータ回路やチェツバ
回路に用いられるときには第８図に点線で示すように２
個のゲートターンオフサイリスクの夫々にスナバ−回路
が接続をれる。ダイオード（Ｄｓｌ）と抵抗（Ｒ８Ｉ）
とコンデンサ（Ｃ８ｌ）とで構成される一方のゲートタ
ーンオフサイリスタＧＴＯＩ用のスナバ−回路が外部主
電極端子（２）と（イ）との間に接続される。また、他
のゲーｉ・ターンオンサイリスタＧＴＯ２川としてダイ
オード（ＤＳ２）と抵抗（Ｒｓｓａ）とコンデ／　？　
（Ｃ８２）とで構成されるスナバ−回路が外部主電極端
子（３８０）と（３りとの間に接続される。第８図の結
線で示でれるゲートターンオフサイリスクモジュールの
組立構造をわかり易くするために第９図にその構造を上
面から斜めにみた図を示す。第６図に示される構造は、
第７図に示される第１の実施例の１個のゲートターンオ
フサイリスクを用いた組立ユニットを２ユニット組合せ
ることによって得られるもので、１組立ユニットの詳細
な説Ｆｌ１１は第７図の実施例で説明したのでここでは
省く。絶縁基板に）及び（３５０）の上面に、第７図に
示される組立構造と同様な構造に形成せられ、絶縁基板
（７）及び（３５０）の下面のメタライズ面が金属板な
どよりなる放熱板（ロ）へ半田などの低融点ろう材で融
着される。２個のゲートターンオアサイリスタを直列接
続するために、銅板などからなる接続リード■を、一方
のユニットのゲートターンオフサイリスクの陽極電極板
０：１と他方のユニットのゲートターンオフサイリスタ
の陰極ｍ＝板（３９ｏｂ）とのそれぞれに半田などの低
融点ろう材で融着して電気的に短絡形成せられる。また
、各外部電極端子は第７図の回路図に示す端子記号と次
のように対応する。外部電極端子（ハ）は２個のゲート
ターンオフサイリスタＧＴＯユ及びＧＴＯ２の共通主電
極外部端子（Ｋｚ、Ａ１端子）に、（（９）はゲートタ
ーンオフサイリスタＧＴＯＩの陰極主電極外部端子（Ｋ
ｌ端子）に、（３８０）はゲートターンオフサイリスタ
ＧＴＯ２の陽極外部端子（Ａ２端子）に、（３９０）と
（匂はゲートターンオフサイリスクＧ’Ｊ’Ｏユの制御
用外部端子で、（３９０）が陰極外部端子（Ｋｌ端子）
に、輪がター）　’＋’ｌｊ極外部端子（Ｇｌ端子）に
、同じ＜　（３９０）と（４００）はゲートターンオフ
サイリスタの制御用外部端子で、（３９０）は陰極外部
端子（Ｋ２端子）に、（４００）はゲート電極外部端子
（Ｇ２端子）にそれぞれ相当する。2 gate turn-off thyristors GTOI GTO2
The flywheel diodes DP are connected in a 1L column, and the flywheel diodes DP are connected in anti-parallel to each gate turn-off switch.
I and DF2 are connected. The part (200) indicated by the one-dot chain line in FIG. 8 shows the part that is incorporated into one exterior case in FIG.检 is a common main electrode external terminal of the two gate turn-off thyristors GTO1 and GTO2, and is formed as a common electrode between the anode electrode of GTOI and the cathode electrode of GTO2. One gate turn-off thyristor (GTOl)
(380) is the anode main electrode external terminal of the other gate turn-off thyristor (GTO2),
(39c) OJ: U GlO are cathode external terminal and gate electrode external terminal respectively for control of gate turn-off'y-iristor (G'['01), oxda, similarly (
39oc) and (4oo) are a cathode external terminal and a gate electrode external terminal, respectively, for controlling another gate turn-off thyristor ('GTO2). When this gate turn-off thyristor module is used in an inverter circuit or a chetsuba circuit, two
A snubber circuit is connected to each of the gate turn-off risks. Diode (Dsl) and resistor (R8I)
A snubber circuit for one of the gate turn-off thyristors GTOI is connected between the external main electrode terminals (2) and (A). In addition, other gate I-turn-on thyristors GTO2 include a diode (DS2), a resistor (Rssa) and a capacitor/?
A snubber circuit consisting of (C82) is connected between the external main electrode terminal (380) and (3). In order to do this, Fig. 9 shows the structure viewed diagonally from above.The structure shown in Fig. 6 is as follows.
It is obtained by combining two assembled units using one gate turn-off sill in the first embodiment shown in FIG. I have explained this with an example, so I will omit it here. A heat sink is formed on the upper surfaces of the insulating substrates (7) and (350) in a structure similar to the assembled structure shown in FIG. It is fused to the plate (b) with a low melting point brazing material such as solder. In order to connect two gate turn-off thyristors in series, connect the connecting lead ■ made of a copper plate or the like with the anode electrode plate of the gate turn-off thyristor of one unit 0:1 and the cathode m of the gate turn-off thyristor of the other unit. An electrical short circuit is formed by fusion bonding to the plate (39ob) using a low melting point brazing material such as solder. Further, each external electrode terminal corresponds to the terminal symbol shown in the circuit diagram of FIG. 7 as follows. The external electrode terminal (c) is connected to the common main electrode external terminal (Kz, A1 terminal) of the two gate turn-off thyristors GTOY and GTO2, ((9) is the cathode main electrode external terminal (K
(380) is the anode external terminal (A2 terminal) of the gate turn-off thyristor GTO2, (390) is the external terminal for controlling the gate turn-off thyristor G'J'O is the cathode external terminal (Kl terminal)
(390) and (400) are the external terminals for controlling the gate turn-off thyristor, and (390) is the cathode external terminal (K2 terminal). , (400) corresponds to the gate electrode external terminal (G2 terminal), respectively.

以上、この発明の詳細な説明したが、この発明によれば
、フライホイルダイオードを同−外装容器内に内蔵する
ことにより、配線によるインダクタンス成分を小烙くす
ることができ、配線のインダクタンスにより発生する飛
開電圧を小さくできること、また、フライホイルダイオ
ードを外装容器内に内蔵させることによって、従来の外
付けの揚台に比較しそのだめのスペースを必要としない
こと、さらに小さなスペース内でフライホイルダイオー
ドの外付作業が不要となり作業性がよくなるなどの利点
を有するゲートターンオフブイリスク組立体の実現と提
供とが可能となる。The present invention has been described in detail above.According to the present invention, by incorporating a flywheel diode in the outer container, the inductance component caused by the wiring can be reduced, and the inductance component generated by the inductance of the wiring can be reduced. In addition, since the flywheel diode is built into the outer container, it requires less space than a conventional external lifting platform. It becomes possible to realize and provide a gate turn-off buoy risk assembly that has advantages such as no external installation of a diode and improved workability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はゲートターンオフサイリスクチツブの構造を示
す断面図、第２図はその電圧・電流特性図、第３図はタ
ートターンオフサイリスクの使用時の接続構成を示す回
路図、第４図はゲートターンオフサイリスクを用いて構
成したインバータ回路の回路図、第５図はそのターンオ
フ時の各部電圧、電流波形図、第６図はこの発明の一実
施例の半導体チップ部の構成を示す断面図、第７図はこ
の実施例の組立て構造を外装部分を除いて示す斜視図、
第８図はこの発明の他の実施例のゲートター７オ７”ｊ
イリスタモジュールの等価回路図、第９図は第８図の実
施例の組立て構造を外装部分を除いて示す斜視図である
。 図において、（１１、ＧＴＯＩ　、　ＧＴ０２はゲート
ターンオフサイリスタテツブ、ＰＪ　＊　”ユ、　ＤＦ
２は７ライホイルダイオードチツプ、（ハ）、　（３８
０）は陽極主電極外部端子、（ト）、　（３９ｏ）は陰
極主電極外部端子、（ト）。 （４ＯＯ）はゲート電極外部端子である。 なお、図中同一符号は同一または相当部分を示代理人　
葛野信−（外１名） 第１図 第２図 第３　Ｆｌ 第４図 第５図 暗部 第６図Figure 1 is a sectional view showing the structure of the gate turn-off silicon chip, Figure 2 is its voltage/current characteristics diagram, Figure 3 is a circuit diagram showing the connection configuration when using the gate turn-off silicon chip, and Figure 4 is A circuit diagram of an inverter circuit configured using a gate turn-off circuit, FIG. 5 is a voltage and current waveform diagram of each part at turn-off, and FIG. 6 is a cross-sectional view showing the configuration of a semiconductor chip part of an embodiment of the present invention. , FIG. 7 is a perspective view showing the assembled structure of this embodiment excluding the exterior part,
FIG. 8 shows a gater 7"j of another embodiment of the present invention.
FIG. 9 is a perspective view showing the assembled structure of the embodiment of FIG. 8, excluding the exterior part. In the figure, (11, GTOI, GT02 is the gate turn-off thyristor block, PJ * "U, DF
2 is a 7-leafoil diode chip, (c), (38
0) is the anode main electrode external terminal, (G), (39o) is the cathode main electrode external terminal, (G). (4OO) is a gate electrode external terminal. In addition, the same reference numerals in the figures indicate the same or corresponding parts.
Shin Kuzuno (1 other person) Figure 1 Figure 2 Figure 3 Fl Figure 4 Figure 5 Dark part Figure 6

Claims (1)

【特許請求の範囲】[Claims] （１）　　ゲートターンオフサイリスタチップとこれ釦
逆並列接続になるように接続されたフライホイルダイオ
ードチップとが同一外装容器内に組み込まれ、上記ゲー
トターンオフサイリスタテツブの陽極電極、陰極電極お
よびゲート電極が」二記外装容器に互いに絶縁されて固
定保持されたそれぞれの外部端子に接続されてなること
を特徴とするゲートターンオフサイリスタ組立体。(1) A gate turn-off thyristor chip and a flywheel diode chip connected in reverse parallel to each other are assembled in the same outer container, and the anode electrode, cathode electrode, and gate electrode of the gate turn-off thyristor chip are ``A gate turn-off thyristor assembly characterized in that it is connected to respective external terminals that are mutually insulated and fixedly held in an outer container.
JP57180402A 1982-10-12 1982-10-12 Gate turn-off thyristor assembled body Pending JPS5968958A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57180402A JPS5968958A (en) 1982-10-12 1982-10-12 Gate turn-off thyristor assembled body
DE19833336979 DE3336979A1 (en) 1982-10-12 1983-10-11 Turn-off thyristor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57180402A JPS5968958A (en) 1982-10-12 1982-10-12 Gate turn-off thyristor assembled body

Publications (1)

Publication Number Publication Date
JPS5968958A true JPS5968958A (en) 1984-04-19

Family

ID=16082610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57180402A Pending JPS5968958A (en) 1982-10-12 1982-10-12 Gate turn-off thyristor assembled body

Country Status (2)

Country Link
JP (1) JPS5968958A (en)
DE (1) DE3336979A1 (en)

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JPH03108749A (en) * 1989-06-23 1991-05-08 Fuji Electric Co Ltd Transistor module for power converter
JPH03132066A (en) * 1989-10-18 1991-06-05 Fuji Electric Co Ltd Transistor module for power conversion device
JPH03145755A (en) * 1989-10-31 1991-06-20 Fuji Electric Co Ltd Power conversion device transistor module
EP0650193A3 (en) * 1993-10-25 1996-07-31 Toshiba Kk Semiconductor device and method for manufacturing the same.

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CH668505A5 (en) * 1985-03-20 1988-12-30 Bbc Brown Boveri & Cie SEMICONDUCTOR COMPONENT.
JPS61218151A (en) * 1985-03-23 1986-09-27 Hitachi Ltd Semiconductor device
DE3538933A1 (en) * 1985-11-02 1987-05-14 Bbc Brown Boveri & Cie PERFORMANCE SEMICONDUCTOR MODULE
CH668667A5 (en) * 1985-11-15 1989-01-13 Bbc Brown Boveri & Cie PERFORMANCE SEMICONDUCTOR MODULE.
DE3609065A1 (en) * 1986-03-18 1987-09-24 Siemens Ag LOW-INDUCTIVE RAILING
DE3643288A1 (en) * 1986-12-18 1988-06-30 Semikron Elektronik Gmbh Semiconductor assembly
JPH0740790B2 (en) * 1987-02-23 1995-05-01 株式会社東芝 High power power module
IT1202657B (en) * 1987-03-09 1989-02-09 Sgs Microelettronica Spa MANUFACTURING PROCEDURE OF A SEMICONDUCTOR MODULAR POWER DEVICE AND DEVICE WITH IT OBTAINED
JP2973799B2 (en) * 1993-04-23 1999-11-08 富士電機株式会社 Power transistor module
US5408128A (en) * 1993-09-15 1995-04-18 International Rectifier Corporation High power semiconductor device module with low thermal resistance and simplified manufacturing
DE102006006175A1 (en) 2006-02-10 2007-08-23 Ecpe Engineering Center For Power Electronics Gmbh Power electronics assembly has surface of insulating substrate with a metal layer, which projects beyond substrate on all sides and projecting region of metal layer forms metal flange which borders insulating substrate
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JPS5746662A (en) * 1980-09-04 1982-03-17 Toshiba Corp Semiconductor rectifier

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JPS6139563A (en) * 1984-06-01 1986-02-25 アントン・ピラ−・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング・ウント・コンパニ−・コマンデイ−トゲゼルシヤフト Semiconductor module
JPH03108749A (en) * 1989-06-23 1991-05-08 Fuji Electric Co Ltd Transistor module for power converter
JPH03132066A (en) * 1989-10-18 1991-06-05 Fuji Electric Co Ltd Transistor module for power conversion device
JPH03145755A (en) * 1989-10-31 1991-06-20 Fuji Electric Co Ltd Power conversion device transistor module
EP0650193A3 (en) * 1993-10-25 1996-07-31 Toshiba Kk Semiconductor device and method for manufacturing the same.
US5783466A (en) * 1993-10-25 1998-07-21 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same

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