JPS5968394U - flushing equipment - Google Patents
flushing equipmentInfo
- Publication number
- JPS5968394U JPS5968394U JP16509682U JP16509682U JPS5968394U JP S5968394 U JPS5968394 U JP S5968394U JP 16509682 U JP16509682 U JP 16509682U JP 16509682 U JP16509682 U JP 16509682U JP S5968394 U JPS5968394 U JP S5968394U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- register
- output
- display
- brightness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Computer Display Output (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案の一実施例の構成図、第２図は、第１
図の実施例のタイムチャートである。
１・・・・・・信号発生器、２・・・・・・アンドゲー
ト、３Ｘ。
３Ａ、 ３Ｂ、 ３Ｇ、 ３Ｄ・・・・・・レジ
スタ、４・・・・・・セレクタ回路、５・・・・・・デ
ジタルアナログ変換器、６・・・・・・陰極線管、７・
・・・・・パターンメモリ。FIG. 1 is a configuration diagram of one embodiment of the present invention, and FIG. 2 is a diagram of the first embodiment of the present invention.
3 is a time chart of the embodiment shown in the figure. 1...signal generator, 2...and gate, 3X. 3A, 3B, 3G, 3D...Register, 4...Selector circuit, 5...Digital analog converter, 6...Cathode ray tube, 7.
...Pattern memory.
Claims (1)
の輝度と、フラッシング指定情報が出力される第１のレ
ジスタと、 第２の表示をする第２の輝度信号が出力される第２のレ
ジスタと、該第１のレジスタを順次選択し、該第１の輝
度信号とフラッシング指定情報が出力される該第１のレ
ジスタを選択するパターンメモリと、 所定周期のパルス信号を発生する信号発生器と、該信号
発生器と、該パターンメモリによって選択された第１の
レジスタのフラッシング指定信号が入力され、論理積信
号が出力されるアンドゲートと、該アンドゲートから入
力される信号が所定値のとき該第２の輝度信号が該ディ
スプレイ装置に出力されるように該第１と第２の輝度信
号を切換える手段とを備えたフラッシング装置。[Claims for Utility Model Registration] A first display that displays a first display on a display device of a computer
A first register to which the brightness of the display and flashing designation information are output, a second register to which a second brightness signal for displaying the second display is output, and the first register are sequentially selected, and the first register is sequentially selected. a pattern memory that selects the first register to which the brightness signal of No. 1 and flashing designation information are output; a signal generator that generates a pulse signal of a predetermined period; an AND gate into which the flushing designation signal of the first register is input and an AND signal is output; and when the signal input from the AND gate is a predetermined value, the second luminance signal is output to the display device. and means for switching between the first and second luminance signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16509682U JPS5968394U (en) | 1982-10-30 | 1982-10-30 | flushing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16509682U JPS5968394U (en) | 1982-10-30 | 1982-10-30 | flushing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5968394U true JPS5968394U (en) | 1984-05-09 |
Family
ID=30361781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16509682U Pending JPS5968394U (en) | 1982-10-30 | 1982-10-30 | flushing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5968394U (en) |
-
1982
- 1982-10-30 JP JP16509682U patent/JPS5968394U/en active Pending
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