JPS5951545A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5951545A JPS5951545A JP16251082A JP16251082A JPS5951545A JP S5951545 A JPS5951545 A JP S5951545A JP 16251082 A JP16251082 A JP 16251082A JP 16251082 A JP16251082 A JP 16251082A JP S5951545 A JPS5951545 A JP S5951545A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- island region
- junction
- semiconductor
- isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は絶縁膜により素子間分離された半導体装置に関
するもので、特に結晶欠陥による接合リーク電流の増加
を防ぎ、トランジスタの歩留りを向上した半導体装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device in which elements are isolated by an insulating film, and more particularly to a semiconductor device that prevents an increase in junction leakage current due to crystal defects and improves the yield of transistors. It is something.
従来例の構成とその問題点
絶縁膜による素子間分離は、半導体集積回路装置の高密
度化に非常に有効な方法として広く利用されている。第
1図は従来の選択酸化法により絶縁膜分離構造を形成す
る工程断面図である。第1図(、)はシリコン基板1の
表面に酸化膜2及び窒化膜3を形IJνした後、半導体
素子形成用の島領域とすべき部分の表面酸化膜2及び窒
化膜3を残してエツチングを行なったものである。第1
図(b)は窒化膜3をマスクとして選択酸化を行なって
分離酸化膜4を形成したもので、第1図(c)は、然る
後、表面酸化膜2及び窒化膜3を除去したものである。Conventional configuration and its problems Isolation between elements using an insulating film is widely used as a very effective method for increasing the density of semiconductor integrated circuit devices. FIG. 1 is a process cross-sectional view of forming an insulating film isolation structure by a conventional selective oxidation method. Figure 1 (,) shows that after forming an oxide film 2 and a nitride film 3 on the surface of a silicon substrate 1, etching is performed, leaving the surface oxide film 2 and nitride film 3 in the area that is to be an island region for forming a semiconductor element. This is what was done. 1st
Figure 1(b) shows the isolation oxide film 4 formed by selective oxidation using the nitride film 3 as a mask, and Figure 1(c) shows the result after the surface oxide film 2 and nitride film 3 have been removed. It is.
以後分離酸化膜4で囲まれた島領域5にトランジスタが
形成される。Thereafter, a transistor is formed in the island region 5 surrounded by the isolation oxide film 4.
」二記方法により形成された分離酸化膜4は横方向ノ酸
化(バーズ・ビーフ)による分離領域の広がりが生じる
という欠点があり、高密度化の防げになる。The isolation oxide film 4 formed by the second method has the disadvantage that the isolation region expands due to lateral oxidation (bird's beef), which prevents high density.
第2図t」1、上記したバーズ・ビーフの発生を抑制し
た他の実施例の工程を説明する断面図である。FIG. 2 is a sectional view illustrating the process of another embodiment in which the occurrence of bird's beef described above is suppressed.
第2図(a)は、前記第1の従来例の第1図(a)に示
した構造からさらに分離領域となるシリコン基板6を反
応性スパッタエッチにより垂直にエッチングした後、露
出した島領域側面に酸化膜7及び窒化膜8を形成したも
のである。第2図(b)は然る後選択酸化により分離酸
化膜9を形成し、表面酸化膜及び窒化膜を除去したもの
である。以後、島領域10にトランジスタが形成される
。FIG. 2(a) shows an exposed island region after vertically etching the silicon substrate 6, which will become a separation region, by reactive sputter etching in the structure shown in FIG. 1(a) of the first conventional example. An oxide film 7 and a nitride film 8 are formed on the side surfaces. In FIG. 2(b), an isolation oxide film 9 is then formed by selective oxidation, and the surface oxide film and nitride film are removed. Thereafter, a transistor is formed in the island region 10.
上記方法により形成された分離酸化膜9はバーズビーフ
の発生が抑制されるという長所を有するが、シリコン窒
化膜8のストレスによって選択酸化時に多数の結晶欠陥
が誘発されるという問題があり、以後島領域10に形成
される半導体素子の電気的特性に悪影響を与えることが
知られている。Although the isolation oxide film 9 formed by the above method has the advantage of suppressing the occurrence of bird's beef, it has the problem that stress in the silicon nitride film 8 induces a large number of crystal defects during selective oxidation. It is known that this adversely affects the electrical characteristics of semiconductor elements formed in region 10.
このような結晶欠陥は、下地酸化膜/窒化膜の膜厚比を
適当な値にし、プロセス熱処理条件を工夫することによ
り低減させることができるが、選択酸化前のシリコン開
口部の構造が第2図(d)のように垂直な角度をもつ形
状であると、選択酸化時におけるシリコン開口部の体積
膨張により、シリコン基板に余分なストレスが加わるた
め、どうしても結晶欠陥の発生を皆無にすることはでき
ない。Such crystal defects can be reduced by setting the base oxide film/nitride film thickness ratio to an appropriate value and devising process heat treatment conditions, but if the structure of the silicon opening before selective oxidation is If the shape has a vertical angle as shown in Figure (d), extra stress will be applied to the silicon substrate due to the volume expansion of the silicon opening during selective oxidation, so it is impossible to completely eliminate the occurrence of crystal defects. Can not.
第3図は、窒化膜による選択酸化時のストレスをなくし
だ分前酸化膜の形成方法を説明する他の従来例を示すも
のである。第3図(a)はシリコン基板11を島領域1
メを残して分離領域13を反応性スパンタエノチにより
垂直にエツチングしたものである。第3図(b)はシリ
コン基板110表面にCVD法により酸化膜13を堆積
させたものである。シリコン基板のシリコン開口部13
における断差は酸化膜13を堆積することによシ解消さ
ね、酸化JIG!人面1.[・1乙坦化される。第3図
(C)は酸化膜13をその膜厚外だけエツチング除去し
、分離領域13に酸化膜14を残したものである0以後
、島領域12にトランジスタを形成する0上記方法によ
り形成された分離酸化膜14は、島領域12を垂直に分
離するため高密度化に適し、かつ選択酸化法によらなく
窒化膜のストレスがシリコン基板に加わらないだめ結晶
欠陥の発生が少ないという長所を有するものの、分離領
域13に埋込まれた分離酸化膜14と7リコン基板11
との膜質の相違により半導体素子形成丑での種々、の熱
処理工程の途中で新たな結晶欠陥の発生は避けられず、
半導体素子の電気的特性の劣化をもたらす0
以上説明したように素子間を絶縁膜によって分離する場
合、特に高密度化に向けて垂直に素子間分離する場合に
おいては、その形成過程で誘発する結晶欠陥が不可避な
問題となり、島領域に形成される半導体素子の電気的特
性に著しい悪影響を与える。FIG. 3 shows another conventional example of a method for forming a pre-oxide film to eliminate stress during selective oxidation using a nitride film. FIG. 3(a) shows the island region 1 of the silicon substrate 11.
The separation region 13 is vertically etched using a reactive spanner etching method, leaving a hole. FIG. 3(b) shows an oxide film 13 deposited on the surface of a silicon substrate 110 by the CVD method. Silicon opening 13 in silicon substrate
The difference in oxide JIG! can be eliminated by depositing an oxide film 13. Human face 1. [・1 is flattened. In FIG. 3(C), the oxide film 13 is removed by etching only beyond its thickness, leaving the oxide film 14 in the isolation region 13. After that, a transistor is formed in the island region 12 by the above method. The isolation oxide film 14 vertically separates the island regions 12 and is therefore suitable for high density, and has the advantage that crystal defects are less likely to occur since the stress of the nitride film is not applied to the silicon substrate regardless of the selective oxidation method. However, the isolation oxide film 14 embedded in the isolation region 13 and the silicon substrate 11
Due to the difference in film quality between the two, it is inevitable that new crystal defects will occur during the various heat treatment processes used to form semiconductor devices.
As explained above, when elements are separated by an insulating film, especially when elements are separated vertically for higher density, crystals that are induced in the formation process Defects become an unavoidable problem and have a significant negative impact on the electrical characteristics of semiconductor devices formed in the island regions.
発明の目的
本発明は、上記した素子間分離絶縁膜を形成する際に誘
起する結晶欠陥が、分離酸化膜の側面によって囲まれた
半導体島領域を横断すること防止し、半導体島領域に形
成される半導体素子の接合リーフ電流の増加を防ぎ、半
導体素子の歩留りを向上した半導体装置を提供するもの
である、発明の構成
本発明は、半導体素子が形成されるべきシリコン半導体
基板の面指数を(110)面にして、素子間分離酸化膜
の形成時に誘起する結晶欠陥が島領域内を横断しないよ
うにしだものである。OBJECTS OF THE INVENTION The present invention prevents the crystal defects induced when forming the above-mentioned element isolation insulating film from crossing the semiconductor island region surrounded by the side surfaces of the isolation oxide film, and prevents crystal defects from being formed in the semiconductor island region. The present invention provides a semiconductor device which prevents an increase in the junction leaf current of a semiconductor element and improves the yield of the semiconductor element. 110) plane to prevent crystal defects induced during the formation of the element isolation oxide film from crossing within the island region.
実施例の説明
半導体素子が形成されるべきシリコン半導体基板の面指
数は、バイポーラトランジスタにおいては(111)、
MOS)ランジスタにおいては(100)が使われてき
ている。これは、前者においてはエピタキシャル成長に
おける結晶性の良さ、後者においては、シリコンとシリ
コン酸化膜との界面電荷の楯9によってそれぞれ選ばれ
ている。Description of Examples The plane index of a silicon semiconductor substrate on which a semiconductor element is to be formed is (111) in a bipolar transistor.
(100) has been used in MOS) transistors. This is selected based on the good crystallinity in epitaxial growth in the former case, and the shield 9 of interfacial charge between silicon and silicon oxide film in the latter case.
−力、シリコン単結晶の結晶構造はダイヤモンド構造を
とり、結晶にせん断応力が加わった時、〔111〕面を
すべり面とし、(110)方向をすべり方向とする転位
が誘起される。第4図(a)。-The crystal structure of a silicon single crystal is a diamond structure, and when shear stress is applied to the crystal, dislocations with the [111] plane as the slip plane and the (110) direction as the slip direction are induced. Figure 4(a).
(b)は従来のシリコン基板を使って垂直の絶縁膜外、
離構造を形成したときの結晶欠陥(転位)の発生する様
子を示している。転位の観察は化学的エツチングによる
エッチビットとして容易に行なえる。(b) is a vertical insulation film using a conventional silicon substrate.
This figure shows how crystal defects (dislocations) occur when a separated structure is formed. Dislocations can be easily observed as etched bits by chemical etching.
第4図(a)は表面の面指数が(111)のシリコン基
板15内に分離酸化膜16を形成したときに誘起した転
位のエッチピット17の様子を示している。(110)
面の断面内に表われるエッチビツトは(111)面の表
面に平行で(110)方向に連なっている。応力は分離
酸化膜16のエツジ付近に集中するだめ転位は分離酸化
膜16のエツジ付近から発生し、島領域18内を横断し
て走っている。それ故、島領域18内に半導体素子を形
成する場合、転位にそって不純物原子が異常拡散を起こ
し、接合のリーフ電流の増加の原因となる。FIG. 4(a) shows the appearance of dislocation etch pits 17 induced when an isolation oxide film 16 is formed in a silicon substrate 15 whose surface has a plane index of (111). (110)
The etch bits appearing in the cross section of the plane are parallel to the surface of the (111) plane and continue in the (110) direction. The stress is concentrated near the edges of the isolation oxide film 16, and the dislocations are generated near the edges of the isolation oxide film 16 and run across the island region 18. Therefore, when a semiconductor element is formed in the island region 18, impurity atoms undergo abnormal diffusion along the dislocations, causing an increase in the leaf current of the junction.
第4図(b)は、表面の面指数が(100)のシリコン
基板18に分離酸化膜19を形成したときに誘発した転
位のエッチピット20の様子を示している。(111)
面の断面内に表われるエッチピットは分離酸化膜19の
エッヂ伺近から表面に対し約60°の角度で下方の(1
10)方向へ走っている。転位は島領域21を斜めに横
断しており、島領域に形成される半導体素子の接合リー
フ電流の増加の原因となる、
本発明は上記点にかんがみてなされたもので、以下本発
明の構成を図面とともに説明する。FIG. 4(b) shows the appearance of dislocation etch pits 20 induced when an isolation oxide film 19 is formed on a silicon substrate 18 whose surface has a plane index of (100). (111)
Etch pits that appear in the cross section of the surface are located at an angle of about 60° from the edge of the isolation oxide film 19 downward (1
10) Running in the direction. Dislocations diagonally cross the island region 21 and cause an increase in the junction leaf current of semiconductor elements formed in the island region.The present invention has been made in view of the above points, and the structure of the present invention will be described below. will be explained with drawings.
第5図は、本発明の一実施例を示す断面図である。(1
10)面指数をもつP形シリコン基板101に従来より
知られた方法により分離酸化膜102を形成した後、分
離酸化膜の側面により囲まれた島領域内にnpn )ラ
ンジスタを形成したものである。素子間分離が垂直にさ
れていると分離酸化膜102のエツジから発生した転位
は、表面に対し垂直力向に走り、分離酸化膜の側面より
四重れた島領域は横断しない。それ故、接合付近の不純
物原子の異常拡散による接合リーフ電流の増加は生じな
い。尚、第6図において、103はP形チャンネルスト
ッパー、1o4はn+埋込層、105はn形コレクタ層
、1Q6はn+コレクタコンタクト、107はP形ベー
ス層、108はn+エミッタ層、1o9,11Qはそれ
ぞれ電極分離酸化膜、111〜113はそれぞれコレク
タ、エミッタ、ベース電極である。FIG. 5 is a sectional view showing an embodiment of the present invention. (1
10) After forming an isolation oxide film 102 on a P-type silicon substrate 101 with a planar index by a conventionally known method, an npn transistor is formed in an island region surrounded by the side surfaces of the isolation oxide film. . If the isolation between the elements is vertical, dislocations generated from the edges of the isolation oxide film 102 run in the direction perpendicular to the surface, and do not cross the quadruple island region from the side surface of the isolation oxide film. Therefore, the junction leaf current does not increase due to abnormal diffusion of impurity atoms near the junction. In FIG. 6, 103 is a P-type channel stopper, 1o4 is an n+ buried layer, 105 is an n-type collector layer, 1Q6 is an n+ collector contact, 107 is a P-type base layer, 108 is an n+ emitter layer, 1o9, 11Q are electrode isolation oxide films, and 111 to 113 are collector, emitter, and base electrodes, respectively.
以上の説明から明らかな様に、本発明は従来の選択酸化
υ、により形成されたバーズ・ビーフを有する素子間分
肉11構造においても接合リーフ電流の減少の効果を1
.1つが、特に垂直に分何1された素子量分#Ni造に
おいて前記効果は著しい。As is clear from the above explanation, the present invention can reduce the effect of reducing the junction leaf current by 1 even in the inter-element wall 11 structure having bird's beef formed by the conventional selective oxidation υ.
.. One is that the above effect is particularly remarkable in #Ni structures where the element amount is vertically divided.
発明の詳細
な説明したように、本発明によれば半導体素子が形成さ
れるべきシリコン半導体基板の面指数を(110)にす
ることにより、素子間分離絶縁膜特に垂直に分離された
素子間分離絶縁膜の形成時に誘起する結晶欠陥が、分離
酸化膜の側面により囲まれた半導体島領域内を横断する
ことを防ぎ、半導体島領域内に形成される半導体素子の
接合リーフ電流の増加をなくシ、半導体素子の歩留りを
向上した半導体装置を提供することができる。As described in detail, according to the present invention, by setting the plane index of a silicon semiconductor substrate on which a semiconductor element is to be formed to (110), an element isolation insulating film, especially vertical element isolation, can be formed. This system prevents crystal defects induced during the formation of an insulating film from crossing the semiconductor island region surrounded by the side surfaces of the isolation oxide film, and eliminates an increase in the junction leaf current of the semiconductor element formed within the semiconductor island region. , it is possible to provide a semiconductor device with improved yield of semiconductor elements.
第1図(、)〜(C)は従来の選択酸化法による分離酸
化膜の製造方法を示す工程断面図、第2図(、)〜(b
)は、垂直な分離酸化膜の製造方法を示す他の従来例の
工程断面図、第3図(a)〜(C)は従来の埋込み法に
よる分離酸化膜の製造方法を示す工程断面図、第4図(
a)、Φ)は、分離酸化膜形成時に誘起する転位の分布
を説明する断面図、第5図は本発明の一実施例にかかる
半導体装置を示す断面図であるっ101 ・・・・・シ
リコン半導体基板、102・・・・・分離酸化111.
’3 、.103・・・・・・転位のエッチピット。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
3
第2図
第 3 図
12 14
第4図Figures 1(,) to (C) are process cross-sectional views showing a method for manufacturing an isolation oxide film by the conventional selective oxidation method, and Figures 2(,) to (b)
) is a process cross-sectional view of another conventional example showing a method for manufacturing a vertical isolation oxide film, and FIGS. Figure 4 (
a) and Φ) are cross-sectional views illustrating the distribution of dislocations induced when forming an isolation oxide film, and FIG. 5 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. Silicon semiconductor substrate, 102...separation oxidation 111.
'3,. 103...Dislocation etch pit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 2 Figure 3 Figure 12 14 Figure 4
Claims (2)
と、前記シリコン半導体基板内に形成された分離絶縁膜
によシ素子間分離された分離領域とを備え、前記分離領
域中に機能素子が形成されていることを特徴とする半導
体装置。(1) A silicon semiconductor substrate having a (110) plane index, and an isolation region in which elements are separated by an isolation insulating film formed in the silicon semiconductor substrate, and functional elements are formed in the isolation region. A semiconductor device characterized by:
、す1体基板表面と垂直になっていることを特徴とする
’I’f ¥rijfj求の範囲第1項記載の半導体装
置。(2) The surface of the Sakai 1 insulating film is 7 silicon]',
, is perpendicular to the surface of the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16251082A JPS5951545A (en) | 1982-09-17 | 1982-09-17 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16251082A JPS5951545A (en) | 1982-09-17 | 1982-09-17 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5951545A true JPS5951545A (en) | 1984-03-26 |
Family
ID=15755989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16251082A Pending JPS5951545A (en) | 1982-09-17 | 1982-09-17 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5951545A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010036013A (en) * | 2008-08-07 | 2010-02-18 | Masae Okadochi | Protector for handle of pan |
JP2011245286A (en) * | 2010-04-30 | 2011-12-08 | Mitsuko Sato | Cooking gripper |
-
1982
- 1982-09-17 JP JP16251082A patent/JPS5951545A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010036013A (en) * | 2008-08-07 | 2010-02-18 | Masae Okadochi | Protector for handle of pan |
JP2011245286A (en) * | 2010-04-30 | 2011-12-08 | Mitsuko Sato | Cooking gripper |
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