JPS5951368A - Measurement of leak current for semiconductor element - Google Patents

Measurement of leak current for semiconductor element

Info

Publication number
JPS5951368A
JPS5951368A JP57161869A JP16186982A JPS5951368A JP S5951368 A JPS5951368 A JP S5951368A JP 57161869 A JP57161869 A JP 57161869A JP 16186982 A JP16186982 A JP 16186982A JP S5951368 A JPS5951368 A JP S5951368A
Authority
JP
Japan
Prior art keywords
input
output terminals
leak current
terminals
measuring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57161869A
Other languages
Japanese (ja)
Inventor
Shinichi Kunieda
国枝　伸一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57161869A priority Critical patent/JPS5951368A/en
Publication of JPS5951368A publication Critical patent/JPS5951368A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To reduce the leak current measuring time by measuring leak current with input/output terminals of a semiconductor element divided into two groups by odd and even sequence utilizing the fact that the leak current flows between adjacent input/outut terminals. CONSTITUTION:Input/output terminals of a semiconductor 19 excluding power source terminals 14 and 18 are divided into two groups by odd and even sequence and the input/output terminals 11, 13 and 16 in the first group are connected together with a wire 20 while the input/output terminals 12, 15 and 17 in the second group are connected together with a wire 21. When a reference voltage is applied to terminals 14 and 18 while diffrent leak measuring voltages are applied into the wires 20 and 21 respectively, leak current flows between adjacent input/output terminals. If this fact is utilized, the leak current flowing through the element 19 equivalent to the total of leak currents flowing between the input/output terminals in the first and second groups and the power source terminals can be measured once without measuring leak current for each of the input/output terminals by switching the connection. Thus, the leak current measing time can be reduced.

Description

【発明の詳細な説明】 本発明は半導体素子のリーク電流測定方法に関する。[Detailed description of the invention] The present invention relates to a method for measuring leakage current of a semiconductor device.

半導体素子の直流特性測定項目の一つに半導体素子の入
出力端子のリーク電流測定がある。この入出力端子のリ
ーク電流測定は、測定対象の入出力端子と他の入出力端
子及び電源端子との間で行なわれる。One of the DC characteristics measurement items for semiconductor devices is leakage current measurement at input/output terminals of semiconductor devices. This input/output terminal leakage current measurement is performed between the input/output terminal to be measured and other input/output terminals and power supply terminals.

第１図は従来の半導体素子の平面図である。FIG. 1 is a plan view of a conventional semiconductor device.

桑 従来の半導体素子入出力端子のリーク電流測定は、まず
、半導体素子９の電源端子４，８間にアース電位を基準
電位とし所定の電源電圧を加える。In the conventional measurement of leakage current at the input/output terminals of a semiconductor element, first, a predetermined power supply voltage is applied between the power supply terminals 4 and 8 of the semiconductor element 9 using the ground potential as a reference potential.

次に入出力端子１以外の全ての入出力端子２，３゜５．
６．７に所定の入出力電圧を加える。この状態で入出力
端子１にリークを測定する為の電圧（以下リーク測定電
圧と呼ぶ）を加えリーク電流を測定する。Next, all input/output terminals other than input/output terminal 1 2, 3゜5.
6. Add the specified input/output voltage to 7. In this state, a voltage for measuring leakage (hereinafter referred to as leakage measurement voltage) is applied to input/output terminal 1 to measure leakage current.

次に、電源端子４，８はそのままの状態にしておき、入
出力端子３以外の入出力端子金てに所定の入出力電圧を
加え、入出力端子２にはリーク測定電圧を加えてリーク
電流を測定する。以下同様に残りの入出力端子のリーク
電流測定操作を１端子ごとにくり返す。Next, leave power supply terminals 4 and 8 as they are, apply a predetermined input/output voltage to all input/output terminals other than input/output terminal 3, and apply a leakage measurement voltage to input/output terminal 2 to determine the leakage current. Measure. Thereafter, the leakage current measurement operation for the remaining input/output terminals is repeated for each terminal in the same manner.

この様にして測定されるリーク電流は、測定対象の入出
力端子と他の入出力端子及び電源端子間に流れるリーク
電流の総和となる。The leakage current measured in this manner is the sum of leakage currents flowing between the input/output terminal to be measured, other input/output terminals, and power supply terminals.

この様に、従来のリーク電流測定方法では、入出力端子
ごとにリーク電流を測定するために、入出力端子数に比
例した多くの測定時間を必要とする欠点がある。As described above, the conventional leakage current measuring method has the disadvantage that a large amount of measurement time is required in proportion to the number of input/output terminals in order to measure the leakage current for each input/output terminal.

本発明の目的は、上記欠点を除去し、測定時間を短縮し
た半導体素子のリーク電流測定方法を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for measuring leakage current of a semiconductor device that eliminates the above-mentioned drawbacks and shortens measurement time.

本発明の半導体素子のリーク電流測定方法は、半導体素
子の入出力端子を奇数番目のＡ群と偶数番目のＢ群とに
分け、それぞれの群内の入出力端子をすべて接続し、Ａ
群に属する入出力端子に第１の規定電圧を、Ｂ群に属す
る入出力端子に第２の規定電圧をそれぞれ印加して流れ
る電流の総和を測定することにより構成される。The method for measuring leakage current of a semiconductor device according to the present invention is to divide the input/output terminals of a semiconductor device into odd-numbered groups A and even-numbered groups B, connect all the input/output terminals in each group,
It is constructed by applying a first specified voltage to the input/output terminals belonging to the group and applying a second specified voltage to the input/output terminals belonging to the group B, and measuring the sum of the flowing currents.

次に、本発明を実施例を用いて詳細に説明する。Next, the present invention will be explained in detail using examples.

第２図は本発明による一実施例を説明するための配線を
施した半導体素子の平面図である。FIG. 2 is a plan view of a semiconductor element with wiring for explaining one embodiment of the present invention.

一般に、入出力端子間のリーク電流は、半導体素子の設
計上隣りあう２つの入出力端子間にのみ流れるのが普通
である。Generally, leakage current between input and output terminals normally flows only between two adjacent input and output terminals due to the design of a semiconductor device.

このことから本実施例では、第２図に示す様に半導体素
子１９の電源端子１４．１８を除く入出′刃端子を２つ
の群に分け、第１群の入出力端子１１゜１３．１６を配
線２０で、第２群の入出力端子１２゜１５．１７を配線
２１でそれぞれ接続する。For this reason, in this embodiment, as shown in FIG. Wiring 20 connects the input/output terminals 12, 15, and 17 of the second group to wiring 21, respectively.

次に、電源端子１４．１８にアース電位を基準電位とし
て、電源電圧として、例えば５ｖを加え、配線２０に入
出力電圧として３ｖを、配線２１にリーク測定電圧とし
て７ｖをそれぞれ加える。Next, for example, 5V is applied as a power supply voltage to the power supply terminals 14 and 18 using the ground potential as a reference potential, 3V is applied as an input/output voltage to the wiring 20, and 7V is applied as a leakage measurement voltage to the wiring 21.

この様にして測定されたリーク電流は、第２群の入出力
端子と第１群の入出力端子及び電源端子間に流れるリー
ク電流の総和となる。従って、この１回の測定値を規格
値と比較することにより半導体素子の良・否を判定する
ことができる。The leakage current measured in this manner is the sum of the leakage currents flowing between the second group of input/output terminals, the first group of input/output terminals, and the power supply terminals. Therefore, by comparing this one measurement value with the standard value, it is possible to determine whether the semiconductor element is good or not.

なお、上述の様にリーク電流を測定したのち、配線２０
と配線２１に加える電圧を逆にしてリーク電流を測定す
れば、半導体素子のリーク電流の測定は更に信頼度の高
いものとなる。In addition, after measuring the leakage current as described above, the wiring 20
If the leakage current is measured with the voltage applied to the wiring 21 reversed, the measurement of the leakage current of the semiconductor element becomes even more reliable.

以上詳細に説明した様に、本発明によれば、半導体素子
の入出力端子数に関係なく短時間で半導体素子のリーク
電流が測定できるのでその効果は大きい。As described in detail above, according to the present invention, the leakage current of a semiconductor element can be measured in a short time regardless of the number of input/output terminals of the semiconductor element, so the effect is great.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来の半導体素子の平面図、第２図は、本発
明による一実施例を説明するための配線を施した半導体
素子の平面図である。 ４．８，１４．１８・・・・・・電源端子、１，２，３
゜５．６，７，１１，１２，１３，１５，１６，１７１
０１９０．入出力端子、９．１９・・・・・・半導体素
子、２０゜２１・・・・・・配線。 ５− 竿ｌ　切 ８　７　　≦　　５ 第２　目 １ −　　　　　　　　　ノ ＼ Ｉｌｌ　　　　　／７　　　ｔ６　　１δ／２FIG. 1 is a plan view of a conventional semiconductor device, and FIG. 2 is a plan view of a semiconductor device with wiring for explaining an embodiment of the present invention. 4.8, 14.18... Power terminal, 1, 2, 3
゜5.6,7,11,12,13,15,16,171
0190. Input/output terminal, 9.19...Semiconductor element, 20°21...Wiring. 5- Rod cut 8 7 ≦ 5 2nd eye 1 - ＼ Ill /7 t6 1δ/2

Claims (1)

【特許請求の範囲】[Claims] 半導体素子の入出力端子を奇数番目のＡ群と偶数番目の
Ｂ群とに分け、それぞれの群内の入出力端子をすべて接
続し、Ａ群に属する入出力端子に第１の規定電圧を、Ｂ
群に属する入出力端子に第２の規定電圧をそれぞれ印加
して流れる電流の総和を測定することを特徴とする半導
体素子のリーク電流測定方法。Divide the input/output terminals of the semiconductor element into odd-numbered A groups and even-numbered B groups, connect all the input/output terminals in each group, and apply a first specified voltage to the input/output terminals belonging to the A group. B
1. A method for measuring leakage current of a semiconductor device, comprising: applying a second specified voltage to each input/output terminal belonging to a group and measuring the sum of flowing currents.
JP57161869A 1982-09-17 1982-09-17 Measurement of leak current for semiconductor element Pending JPS5951368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57161869A JPS5951368A (en) 1982-09-17 1982-09-17 Measurement of leak current for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57161869A JPS5951368A (en) 1982-09-17 1982-09-17 Measurement of leak current for semiconductor element

Publications (1)

Publication Number Publication Date
JPS5951368A true JPS5951368A (en) 1984-03-24

Family

ID=15743507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57161869A Pending JPS5951368A (en) 1982-09-17 1982-09-17 Measurement of leak current for semiconductor element

Country Status (1)

Country Link
JP (1) JPS5951368A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371669A (en) * 1986-09-16 1988-04-01 Matsushita Electronics Corp Inspecting method for electronic circuit device
WO2013077882A1 (en) * 2011-11-23 2013-05-30 Intel Corporation Current tests for i/o interface connectors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55113968A (en) * 1979-02-27 1980-09-02 Nec Corp Method of testing integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55113968A (en) * 1979-02-27 1980-09-02 Nec Corp Method of testing integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371669A (en) * 1986-09-16 1988-04-01 Matsushita Electronics Corp Inspecting method for electronic circuit device
WO2013077882A1 (en) * 2011-11-23 2013-05-30 Intel Corporation Current tests for i/o interface connectors
US9551741B2 (en) 2011-11-23 2017-01-24 Intel Corporation Current tests for I/O interface connectors

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