JPS5947842A - Current switching logical circuit - Google Patents

Current switching logical circuit

Info

Publication number
JPS5947842A
JPS5947842A JP15745982A JP15745982A JPS5947842A JP S5947842 A JPS5947842 A JP S5947842A JP 15745982 A JP15745982 A JP 15745982A JP 15745982 A JP15745982 A JP 15745982A JP S5947842 A JPS5947842 A JP S5947842A
Authority
JP
Japan
Prior art keywords
current
level
emitter follower
constant current
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15745982A
Other languages
Japanese (ja)
Inventor
Kazumi Yamada
和美 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15745982A priority Critical patent/JPS5947842A/en
Publication of JPS5947842A publication Critical patent/JPS5947842A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/001—Arrangements for reducing power consumption in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To suppress useless consumption of an emitter follower current, by providing a power supply switch connecting a constant current source alternately to two output terminals, and controlling the power supply switch by an input signal of the current switching logical circuit. CONSTITUTION:The current switch comprising transistors(TRs) Q9, Q10 supplies alternately a constant current I0 to emitter follower TRs Q7, Q8. For example, when an input terminal IN is at L level, a TRQ6 is turned on, then an output terminal OUT goes to L level, while a complementary output terminal -OUT goes to H level. Thus, the TRQ9 is turned on, the constant current I0 flows to the TRQ8 to quicken the discharge of a capacitor CL added to the output terminal OUT and a transition time of the output level from H to L.

Description

【発明の詳細な説明】 本発明は、エミッタフォロアを備えた電流切換型論理回
路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current switched logic circuit with an emitter follower.

第１図に、従来用いられているエミッタフォロア付電流
切換型論理回路を示す。ここで、第１図の回路において
エミッタフォロアに接続された定電流源Ｃ３（ＥＦ）の
電流値”ｘ’（３Ｂ　（Ｅ　Ｆ　）は以下のようにして
決定されるのが一般的である。FIG. 1 shows a conventionally used current switching type logic circuit with an emitter follower. Here, in the circuit of FIG. 1, the current value "x' (3B (EF)) of the constant current source C3 (EF) connected to the emitter follower is generally determined as follows.

エミッタフォロアの出力端子ＯＵＴにｊに続さノする負
荷容量値をＣＬ１出力電圧振ＩｌｌΔＶ１高レベル出力
電圧をＶ　Ｏｌｌとすると、エミソタフオｒｘ　−７の
入力が高レベルから低レベルに遷移した時刻からｔ上式
を用いて、Ｖｏ（ｔｌが出力振幅Δ■の９０％から、１
０％まで降下する時間所謂降下時間Ｌｔｆ求めると下式
になる。If the load capacitance value following j to the output terminal OUT of the emitter follower is CL1 output voltage swing IllΔV1 high level output voltage is V Oll, then t Using the above formula, Vo(tl is 90% of the output amplitude Δ■, then 1
The time required to drop to 0%, the so-called falling time Ltf, is determined by the following formula.

因ニ、エミッタフォロアの入力が低→高レベルに遷移し
た場合に、Ｖｏ（ｔｌが出力振幅２ΔＶの１０％→９０
チに至る時間、所謂上昇時間ｔｒは出力端子ＯＵＴと、
負荷容ｆ（（’Ｌとの間の直列抵抗ｆｒとすると、下式
で近似される。Incidentally, when the input of the emitter follower transitions from low to high level, Vo(tl changes from 10% of the output amplitude 2ΔV to 90
The time to reach the peak, the so-called rise time tr, is between the output terminal OUT and
Assuming that the series resistance between the load capacity f(('L) is fr, it is approximated by the following formula.

ｔｒ−＜２．２ＣＬ−ｒ　　　　　　　　−＜３＞上記
１式よυ、エミッタフォロアの電流ＩＣ８（Ｆ；Ｆ）に
よって決まるのは専ら下降時間１／　　である事がわか
る。従ってエミッタフォロアのｔ［ｉｌｔ　Ｉｃｓ（ｇ
ｐ）ｆｄ上記式（２）に所璧のｔｆ’に代入して必要な
値を決定する。tr-<2.2CL-r-<3> According to the above equation 1, it can be seen that what is determined by υ and the emitter follower current IC8 (F; F) is exclusively the falling time 1/. Therefore, t[ilt Ics(g
p) fd Determine the required value by substituting the desired tf' into the above equation (2).

以上の一般的なエミッタフォロア電流の決定方法から明
らかなように、エミッタフォロア電１ＩＣ８（Ｆ、Ｆ）
の大小が影響力を持つのは、出力電圧が高→低と遷移す
る場合のみで、逆に低→高への遷移時間には影響がない
。従って、出力電圧が低→高へ遷移している間のエミッ
タフォロア４１ｉＩｃｓ（ＥＦ）は無駄に消費されてい
ることになる。As is clear from the above general method for determining emitter follower current, emitter follower current 1IC8 (F, F)
The magnitude of is influential only when the output voltage transitions from high to low; conversely, it has no effect on the transition time from low to high. Therefore, the emitter follower 41iIcs (EF) is wasted while the output voltage is transitioning from low to high.

本発明は、上記の様なエミッタフォロア電流■Ｃ３（Ｅ
Ｆ）の無駄な消費を抑えた電流切換型論理回路を提供す
ること金目的とする。The present invention provides the emitter follower current ■C3(E
The objective is to provide a current switching type logic circuit that suppresses wasteful consumption of F).

上記目的を達成するため、本発明は、エミッタフォロア
による真値、補値の２つの出力端子を有する電流切換型
論理回路において、定電流源と、該定電流源を前記２つ
の出力端子に変互に切換えて接続し得る電源スィッチと
を有し、該電流切換型論理回路の入力信号によって、上
記電流スイッチを制御することを特徴とする。In order to achieve the above object, the present invention provides a current switching type logic circuit having two output terminals, a true value and a complement value, by an emitter follower. The present invention is characterized in that it has power switches that can be switched and connected to each other, and that the current switches are controlled by an input signal of the current switching type logic circuit.

第２図に本発明の一実施例を示す。FIG. 2 shows an embodiment of the present invention.

同図で、トランジスタＱ９とＱ＋ｏにょるＷｆ　ｐｌ　
スイッチによハ定電流１０全エミノクフ（１−ｊアトラ
ンジスタＱｖ、Ｑｓに変互に供給する１、例えば入力端
子ＩＮが’Ｌ”レベルの時、）・少ソジスタＱ６がＯＮ
Ｌ、したがッテ、出力端子ＯＵＴは°Ｌ”　　Ｉ／ヘル
、一方相補出力端子ＯＵＴは°’ｉｌ”　レベルに変化
する。この時相補入力端子「習は’１１”レベルである
から、トランジスタＱ９がＯＮＬ、定電流１ｏは、トラ
ンジスタＱ８に流れる。すなわち、出力レベルが′Ｈ″
となるトランジスタＱ７には■′１．ユＦの電流しか流
れないのに対し、出力レベルが”Ｌ”となるトランジス
タＱ８にはＩ　ＥＦ　＋Ｉ　ｇなる電流が流れ、出力端
子ＯＵＴに付加された容ぷｃＬの放電を速め出力レベル
のＨ→Ｌへの遷移時間を早める。In the same figure, transistor Q9 and Q+o are Wf pl
A constant current of 10 is supplied to the transistors Qv and Qs alternately by the switch. For example, when the input terminal IN is at the 'L' level, the low voltage transistor Q6 is turned on.
When the signal is low, the output terminal OUT changes to the °L" I/hell level, while the complementary output terminal OUT changes to the °'il" level. At this time, since the complementary input terminal "X" is at the '11' level, the transistor Q9 is ONL, and the constant current 1o flows to the transistor Q8. In other words, the output level is 'H''
The transistor Q7 has ■'1. In contrast, a current of IEF +Ig flows through the transistor Q8 whose output level becomes "L", which speeds up the discharge of the capacitor PcL added to the output terminal OUT, and increases the output level to H. → Speed up the transition time to L.

上記の様に電源スィッチによって、よりｌｉｔ流の必要
なエミッタフォロアの方に定電流を振り分けるため、第
１図の従来回路と比較した場合、同じ速度を得るために
は、Ｉ　ＥＦ　＝　１’＋＞ｒ　−１−ｉｏ　とすれば
よいから、エミッタフォロア全体で必要とする電流は、
従来回路で２ＩＦ、Ｆ％−力木発明によれば、２Ｉｉ＋
Ｆ−１−ｌｏ−ｌ１ｐ−ｔ−ＩＥＦ　（Ｉ’ＥＦ　＜　
ＩＥＦ）となり、電流削減が可能となる。逆に、従来回
路と同じ電３１ｆ、金木発明の回路に用いれば、出力レ
ベルのＨ→Ｉ７遷移時間はより短かくなり、より高速な
動作がイ！Ｊられる。As mentioned above, the power switch distributes the constant current to the emitter follower, which requires more lit current, so when compared with the conventional circuit shown in Figure 1, in order to obtain the same speed, I EF = 1'+ > r -1-io, the current required for the entire emitter follower is:
In the conventional circuit, 2IF, F%-According to Rikiki's invention, 2Ii+
F-1-lo-l1p-t-IEF (I'EF <
IEF), making it possible to reduce the current. On the other hand, if it is used in the circuit invented by Kaneki, which is the same as the conventional circuit, the output level H→I7 transition time will be shorter and faster operation will be possible! J is done.

以上のように、本発明によれば、従来のエミックフ、）
ロア付電流切換型論理回路と同じ速度を得るためにより
少ない電流消費で済み、一方同じ電流消費の場合はよシ
高速な動作が可能となる。以上の説明ではＮＰＮ　トラ
ンジスタを用いたが、ＰＮＰトランジスタを用いても同
様の効果が得られることは明らかである。As described above, according to the present invention, the conventional emic
It requires less current consumption to achieve the same speed as a current-switching logic circuit with a lower, but can operate much faster with the same current consumption. Although NPN transistors have been used in the above description, it is clear that similar effects can be obtained using PNP transistors.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のエミッタフォロア付電流切換型論理回路
を示す図、第２図は本発明によるエミッタフォロア付電
流切換型論理回路の一実施例を示す図である。 ＩＮ・・・・・・相補入力端子、■ζ・・・・・・基準
電圧、Ｑ５〜Ｑｌｏ・・・・・・トランジスタ、（−Ｓ
’（Ｆ、１．・）・・・・エミッタフォロア定電流源、
　Ｃ８’（Ｇ　）−−ｒｉｂ流スイッチ部定電流源。FIG. 1 is a diagram showing a conventional current switching type logic circuit with an emitter follower, and FIG. 2 is a diagram showing an embodiment of the current switching type logic circuit with an emitter follower according to the present invention. IN...Complementary input terminal, ■ζ...Reference voltage, Q5~Qlo...Transistor, (-S
'(F, 1....) Emitter follower constant current source,
C8'(G)--rib flow switch section constant current source.

Claims (1)

【特許請求の範囲】[Claims] エミッタフォロアを介した真値、補値の２つの出力端子
を有する電流切換型論理回路において、定電流源と、該
定電流源を前記２つの出力端子釦交互に切換えて接続し
得る電流スイッチとを有し、該電流切換型論理回路の入
力信号によって、上記電流スイッチを制御することを％
？＆とする電流切換型論理回路。In a current switching type logic circuit having two output terminals for a true value and a complement value via an emitter follower, a constant current source and a current switch capable of connecting the constant current source by alternately switching the two output terminal buttons. and controlling the current switch by the input signal of the current switching type logic circuit.
? Current switching type logic circuit with &.
JP15745982A 1982-09-10 1982-09-10 Current switching logical circuit Pending JPS5947842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15745982A JPS5947842A (en) 1982-09-10 1982-09-10 Current switching logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15745982A JPS5947842A (en) 1982-09-10 1982-09-10 Current switching logical circuit

Publications (1)

Publication Number Publication Date
JPS5947842A true JPS5947842A (en) 1984-03-17

Family

ID=15650119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15745982A Pending JPS5947842A (en) 1982-09-10 1982-09-10 Current switching logical circuit

Country Status (1)

Country Link
JP (1) JPS5947842A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0562881A2 (en) * 1992-03-26 1993-09-29 Nec Corporation Wired-or logic circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5125304A (en) * 1974-08-27 1976-03-01 Komatsu Mfg Co Ltd KUTSUSAKUTSUMIKOMIKIKAI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5125304A (en) * 1974-08-27 1976-03-01 Komatsu Mfg Co Ltd KUTSUSAKUTSUMIKOMIKIKAI

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0562881A2 (en) * 1992-03-26 1993-09-29 Nec Corporation Wired-or logic circuit
EP0562881A3 (en) * 1992-03-26 1994-02-23 Nec Corp
US5459411A (en) * 1992-03-26 1995-10-17 Nec Corporation Wired-OR logic circuits each having a constant current source

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