JPS5947605A - Back-up controller - Google Patents
Back-up controllerInfo
- Publication number
- JPS5947605A JPS5947605A JP57159158A JP15915882A JPS5947605A JP S5947605 A JPS5947605 A JP S5947605A JP 57159158 A JP57159158 A JP 57159158A JP 15915882 A JP15915882 A JP 15915882A JP S5947605 A JPS5947605 A JP S5947605A
- Authority
- JP
- Japan
- Prior art keywords
- stand
- circuit
- check
- working
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims description 7
- 230000006870 function Effects 0.000 claims description 5
- 238000012544 monitoring process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 230000015654 memory Effects 0.000 abstract description 6
- 238000012360 testing method Methods 0.000 abstract description 2
- 230000003252 repetitive effect Effects 0.000 abstract 1
- 238000012545 processing Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Testing And Monitoring For Control Systems (AREA)
- Safety Devices In Control Systems (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、相互に他の処理動作をバック・アップする
２重系のバック・アップ制御装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dual system backup control device that mutually backs up other processing operations.
従来、この種の装置として第１図に示すものがあった。Conventionally, there has been a device of this type as shown in FIG.
図において、１ａ＊ｉｂはコンピュータ、２ａ、２ｂは
メモリ、３はバス３ａ 、３ｂを介しテコンピュータ１
ａ、メモリ２ａ、コンピュータ１ｂ及びメモＩＪ ２
ｂ Ｋ接続され、またノ（ス６Ｃを介して図示なしのプ
ロセス装置へ接続され、プロセス処理の際はバス３Ｃを
バス３ａ又は６ｂへ切換える制御及びコンピュータｉａ
又は１ｂの動作を監視する機能をもつバック・アップ制
御装置である。′
次に動作について説明する８いま、）くス６ａ。In the figure, 1a*ib is a computer, 2a and 2b are memories, and 3 is a computer 1 via buses 3a and 3b.
a, memory 2a, computer 1b and memo IJ 2
b. A control and computer ia which is connected to a process device (not shown) via a bus 6C and which switches the bus 3C to the bus 3a or 6b during process processing.
Alternatively, it is a backup control device that has the function of monitoring the operation of 1b. 'Next, I will explain the operation.8) Kusu6a.
３ｃがバック・アップ制御装置６を介して接続され、コ
ンピュータ１ａ及びメモリ２１Ｌが動作状態（動作系）
にあり、コンピュータ１ｂ及びメモリ２ｂが待機状態（
待機系）にあるものとする。ノぐツク・アップ装置３は
バス６８．上の信号をチェックし、これに異常が検出さ
れたときは、ノ（ス６Ｃの接続を待機系のバス３ｂに切
換え、コンピュータ１ｂを起動させてこれを動作系にて
、コンピュータ１ａを待機系にして処理を継続する。3c is connected via the backup control device 6, and the computer 1a and memory 21L are in an operating state (operating system).
computer 1b and memory 2b are in standby state (
(standby system). The check-up device 3 is on bus 68. Check the above signal, and if an abnormality is detected, switch the connection of bus 6C to the standby bus 3b, start the computer 1b and make it the active system, and set the computer 1a to the standby system. and continue processing.
従来のバック・アップ装置は、以上のように栴成されて
いるので、待機系の機能がチェックされておラス、例え
バック・アップのための切換えがあっても待機系が正常
に動作するという保障がなされていない欠点があった。Conventional backup devices are constructed as described above, so the functions of the standby system are checked, and even if there is switching for backup, the standby system will operate normally. There was a drawback that there was no guarantee.
この発明は、上記のような従来のものの欠点之除去する
ためになされたもので、動作系のチェックと共に待機系
のチェックも反復的に適時行なうことにより、信頼性の
高い２重系が得られるバック・アップ制御装置を提供す
ることを目的とする。This invention was made to eliminate the above-mentioned drawbacks of the conventional system, and by repeatedly and timely checking the standby system as well as the operating system, a highly reliable dual system can be obtained. The purpose is to provide a backup control device.
以下、この発明の一実施例を図について説明する。Ｗ、
２図において、第１図と同一符号は同一部分を示し、４
はこの発明によるバック・アップ制御装置である。バッ
ク・アップ制御装置４において、５はバス３ａ及び３ｂ
の信号をチェックするチェック回路、６は第１図に示す
バック・アップ制御装置６と同一機能をもつ監視切換回
路、７はチェック回路５及び監視切換回路６の動作を制
御する制御回路、８はチェック回路５から出力されるエ
ラー信号圧よりエラー発生の表示をする表示回路である
。An embodiment of the present invention will be described below with reference to the drawings. W,
In Figure 2, the same symbols as in Figure 1 indicate the same parts, and 4
is a backup control device according to the present invention. In the backup control device 4, 5 is the bus 3a and 3b.
6 is a monitoring switching circuit that has the same function as the backup control device 6 shown in FIG. 1; 7 is a control circuit that controls the operation of the checking circuit 5 and the monitoring switching circuit 6; This is a display circuit that indicates the occurrence of an error based on the error signal pressure output from the check circuit 5.
次に動作圧ついて説明する。コンピュータ１ａが動作系
、コンピュータ１ｂが待機系にあるものとすると、チェ
ック回路５はバス３ａ 、３ｂを介して適時、例えば一
定の周期で試験信号を出力してコンピュータ１ａ、ｉｂ
、メモリ３ａ、３ｂが正常に機能するか否かのチェック
を行なう。これにより異常が検出されたときは表示回路
８にエラー信号を送り、表示回路８によりどの部分にど
のような異常があるかを、数字、符号又は各部分にそれ
ぞれ対応される複数のラングから当該部分に対応するも
のを点灯することにより、エラー発生の表示をする。ま
た、チェック回路５は表示回路８ヘ工ラー信号を上記の
ように出力すると共に、エラーの発生を図示なしの外部
装置にも接点信号５ａにより知らせる。Next, the operating pressure will be explained. Assuming that the computer 1a is in the active system and the computer 1b is in the standby system, the check circuit 5 outputs test signals via the buses 3a and 3b at appropriate times, for example, at regular intervals, to
, checks whether the memories 3a, 3b function normally. When an abnormality is detected, an error signal is sent to the display circuit 8, and the display circuit 8 indicates what kind of abnormality is present in which part using numbers, codes, or multiple rungs corresponding to each part. The occurrence of an error is indicated by lighting up the corresponding part. Further, the check circuit 5 outputs an error signal to the display circuit 8 as described above, and also notifies an external device (not shown) of the occurrence of an error using a contact signal 5a.
また処理の過程で動作系のコンピュータ１ａからコンピ
ュータ１ｂへデータを転送することがある。これには、
操作員のスイッチ操作に従ってプログラムやデータを転
送する場合、一定周期で動作系から待機系へ最新データ
を与え、待機系を動作系にフォローアツプさせる場合が
含まれる。このようなデータ転送に対してもチェック回
路５はバス３ａ、３ｂの信号をチェックすることにより
、それらにおける異常の有無をチェックする。これには
データにエラーが検出されたときにリトライを行なわせ
、回復不能のエラーを検出する処理が含まれる。Also, in the process of processing, data may be transferred from the operating system computer 1a to the computer 1b. This includes:
When transferring programs and data according to switch operations by an operator, this includes cases where the latest data is given from the active system to the standby system at regular intervals, and the standby system follows up with the active system. Even in such data transfer, the check circuit 5 checks the signals on the buses 3a and 3b to see if there is any abnormality therein. This includes processing to perform a retry when an error is detected in data and detect an irrecoverable error.
以上のように、この発明によれば、待機糸についても正
常に機能するか否かのチェックを適時行なうよ５にした
ので、待機系の異常を予め除去しておくことが可能とな
り、動作系から待機系へのバック・アップが確実に得ら
れ、システム全体のｃ３頼性を高めることができる効果
がある。As described above, according to the present invention, it is possible to timely check whether or not the standby yarn is functioning normally, so it is possible to eliminate abnormalities in the standby system in advance, and the operation system It is possible to reliably obtain backup from the system to the standby system, which has the effect of increasing the C3 reliability of the entire system.
第１Ｎは従来のバック・アップ制御装置を示すブロック
図、第２図はこの発明の一実施例によるバック・アップ
制御装置のブロック図である。
ｉａ、ｌｂ川用ンピュータ、２ ａ 、 ２ ｂ−・メ
モリ、３，４・・・バック・アップ制御装置、５・・・
チェック回路、６一監視切換回路、７・・・制御回路。
なお、図中、同一符号は同一部を示づ−。
代理人 葛野信−（ほか、１名）
第１図
フａｔで７装置へ1N is a block diagram showing a conventional backup control device, and FIG. 2 is a block diagram of a backup control device according to an embodiment of the present invention. ia, lb computer, 2a, 2b-memory, 3, 4...backup control device, 5...
Check circuit, 6-monitoring switching circuit, 7...control circuit. In addition, in the figures, the same reference numerals indicate the same parts. Agent Makoto Kuzuno (and 1 other person) Figure 1 Fat to 7 device
Claims (1)
プロセス装置に接続し、接続された一方の上記コンピュ
ータの動作を監視し、異常が検出されたときは他方の上
記コンピュータに接続を切換える監視切換回路と、上記
各コンピュータの機能を反復的にチェックし、異常を検
出したときはエラー信号を出力するチェック回路とを備
えたバック・アップ制御装置。A monitoring switch that selectively connects one of a pair of computers to a process device via a bus, monitors the operation of one of the connected computers, and switches the connection to the other computer when an abnormality is detected. A backup control device comprising a circuit and a check circuit that repeatedly checks the functions of each of the computers and outputs an error signal when an abnormality is detected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57159158A JPS5947605A (en) | 1982-09-10 | 1982-09-10 | Back-up controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57159158A JPS5947605A (en) | 1982-09-10 | 1982-09-10 | Back-up controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5947605A true JPS5947605A (en) | 1984-03-17 |
Family
ID=15687531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57159158A Pending JPS5947605A (en) | 1982-09-10 | 1982-09-10 | Back-up controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5947605A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19516595A1 (en) * | 1993-11-02 | 1996-11-14 | Sumitomo Metal Ind | Method and appts. for pierce rolling seamless steel pipes |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS512889A (en) * | 1974-06-26 | 1976-01-10 | Tokyo Shibaura Electric Co | Jidoseigyokeino kanshisochi |
| JPS51148172A (en) * | 1975-06-16 | 1976-12-20 | Hitachi Ltd | An atutomatic control apparatus |
| JPS5741704A (en) * | 1980-08-26 | 1982-03-09 | Toshiba Corp | Sequence controller |
-
1982
- 1982-09-10 JP JP57159158A patent/JPS5947605A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS512889A (en) * | 1974-06-26 | 1976-01-10 | Tokyo Shibaura Electric Co | Jidoseigyokeino kanshisochi |
| JPS51148172A (en) * | 1975-06-16 | 1976-12-20 | Hitachi Ltd | An atutomatic control apparatus |
| JPS5741704A (en) * | 1980-08-26 | 1982-03-09 | Toshiba Corp | Sequence controller |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19516595A1 (en) * | 1993-11-02 | 1996-11-14 | Sumitomo Metal Ind | Method and appts. for pierce rolling seamless steel pipes |
| US5636542A (en) * | 1993-11-02 | 1997-06-10 | Sumitomo Metal Industries, Ltd. | Piercing-rolling method and piercing/rolling apparatus for seamless steel tube |
| DE19516595C2 (en) * | 1993-11-02 | 1999-10-07 | Sumitomo Metal Ind | Hole rolling process and hole rolling device for seamless steel pipes |
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