JPS5946047A - Forming method for multilayer wiring of semiconductor device - Google Patents

Forming method for multilayer wiring of semiconductor device

Info

Publication number
JPS5946047A
JPS5946047A JP15591082A JP15591082A JPS5946047A JP S5946047 A JPS5946047 A JP S5946047A JP 15591082 A JP15591082 A JP 15591082A JP 15591082 A JP15591082 A JP 15591082A JP S5946047 A JPS5946047 A JP S5946047A
Authority
JP
Japan
Prior art keywords
al2o3
layer wiring
wiring
connection
lower layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15591082A
Other languages
Japanese (ja)
Inventor
Yoshitami Oka
岡 宜民
Shigeo Furuguchi
古口 栄男
Hiroshi Kinoshita
博 木下
Toshio Yonezawa
敏夫 米沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15591082A priority Critical patent/JPS5946047A/en
Publication of JPS5946047A publication Critical patent/JPS5946047A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the defective connection of the connecting section of upper and lower layer wirings by adding a metal M, which reduces Al2O3 while forming MO and M2O3 by itself, into Al of the upper layer wiring. CONSTITUTION:Al2O3 is chemically stable, but can be reduced. An Al alloy containing 0.1-0.3% of the metal Th, La, Be, Mg, Ca, Ba or the like of strong oxidizability capable of reducing Al2O3 is used as an upper layer wiring material. The dissociation energy of the oxides of these metals is larger than Al2O3, they are chemically stable, and they can reduce Al2O3 into Al. A sintering temperature of 400-500 deg.C used for forming the connection of the upper and lower wirings is sufficient for reduction. MO and M2O3 formed take several massive shapes, and the lower layer Al wiring with Al2O3 naturally formed on the surface and the upper layer Al alloy wiring are Al-Al connected. An effect is not displayed when the quantity of the metal being added is less than 0.01%, and MO and M2O3 obstruct connection when it is 0.3% or more.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置の多層配線形成方法に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming multilayer wiring in a semiconductor device.

〔発明の技術的背景〕[Technical background of the invention]

従来、半導体装置の配線材料としてはA1.(アルミニ
ウム)を用いるが、A1は非常に酸化し7やすいため、
LSIなどの多層配線構造を有する半導体装置に於ては
上層配線と下層配線との1λI:6’jl: jllり
分に於て接続不良を生じることが予力・った。
Conventionally, A1. (Aluminum) is used, but since A1 is very easy to oxidize,
In a semiconductor device having a multilayer wiring structure such as an LSI, it is expected that a connection failure will occur in a distance of 1λI:6'jl:jll between the upper layer wiring and the lower layer wiring.

〔背景技術の問題点〕[Problems with background technology]

Alは非常に酸化されやすいため、蒸着の貞空条注下の
ようなかなり冒度の真空中(で放iねシた場合でも、そ
の表面は少なくとも数十穴以上のjマさのアルミナ膜が
生じる。アルミナ(A1203)は絶縁性の高い物質で
あるため、これが配線中や配線の接続部に生じると、配
線が断線した状態となったり、あるいは配線抵抗が著し
く高くなって半導体装置を実質的に不能化してしまう。
Al is very easily oxidized, so even if it is left alone in a fairly extreme vacuum, such as during vapor deposition, its surface will be covered with an alumina film with at least several tens of holes. Since alumina (A1203) is a highly insulating substance, if it occurs in the wiring or at the connections of the wiring, the wiring will become disconnected or the wiring resistance will increase significantly, causing the semiconductor device to be damaged. It becomes physically impossible.

従りてA1を用いて多層配線を形成する場合には上層配
線を被着させる直前に稀フッ酸洗浄などの表面1処理を
することが行われているが、そitでも」二層配線全形
成前又は形成中に下層配線の表面には必ず微小厚さのア
ルミナ膜が生じており、」一層配線と下層配線との接続
部に於゛C接続不良もしく(1断線を11じ、その結果
、特にスルーポール接続点が数十万個もあるような半導
体装置の製造歩留りを低下させるという問題点が提起さ
れている。
Therefore, when forming multilayer wiring using A1, surface 1 treatment such as dilute hydrofluoric acid cleaning is carried out immediately before depositing the upper layer wiring, but even with that, the entire second layer wiring is Before or during formation, a microscopic alumina film is always formed on the surface of the lower-layer wiring, and the connection between the first-layer wiring and the lower-layer wiring is caused by poor connection or disconnection (11). As a result, a problem has been raised in that the manufacturing yield of semiconductor devices, especially those having hundreds of thousands of through-pole connection points, is reduced.

〔発明の目的〕[Purpose of the invention]

この発明の目的は、前記の如き問題点、すなわち上層配
線と下層配線との接続部によ、・ける接続不良の発生を
防止しつる新規な多層配線形成方法ン:提供することで
ある。
It is an object of the present invention to provide a novel method for forming multilayer interconnections that can prevent the above-mentioned problems, namely, the occurrence of connection failures caused by connections between upper layer interconnections and lower layer interconnections.

〔発明の棚、要〕[Shelf of inventions, essential]

この発明の方法は上層配線材としてAlよりも被酸化性
の強いTh 、 La 、 Be 、Mg 、 Ca 
、 Ea等の金属’io、01〜03%含有しブヒA1
合金を用いるとともに1層配線利としてAtを用いるこ
とケ特徴とjる。この発明では、Al2O3を還元して
AIにするため[Th 、 La、 、 Be + M
g 、 Ca 、 Ba等の金属を用い、上層配線と下
層配線との接続部に存在するAl2O3を分解さ−(−
iJl 従来の半導体装置製造工程ケ著I−2〈改変す
ること攻く、前記の問題点を解決できるという利点があ
る。
The method of the present invention uses Th, La, Be, Mg, and Ca, which are more oxidizable than Al, as upper layer wiring materials.
, containing 01-03% of metals such as Ea, Buhi A1
The characteristics are that an alloy is used and At is used for the first layer interconnection. In this invention, in order to reduce Al2O3 to AI, [Th, La, , Be + M
Using metals such as g, Ca, and Ba, Al2O3 existing at the connection between the upper layer wiring and the lower layer wiring is decomposed.
iJl Conventional Semiconductor Device Manufacturing Process Book I-2〈It has the advantage of being able to solve the above-mentioned problems without modification.

〔発明の実施例〕[Embodiments of the invention]

以下に本発明の実施例について説明するが、その前に従
来方法の間)唄点について図面を参照L7て簡単に説明
する。
Embodiments of the present invention will be described below, but before that, the conventional method) will be briefly described with reference to the drawings.

第1図(イ)乃至(−9は半導体装置の製造工1ljI
”(a於゛て−L層配線と下層配線との接続部Vcオ、
−ける接に不良の発生状況不・示したものである。
Figures 1 (a) to (-9 are semiconductor device manufacturing workers 1ljI
”(a) - Connection part Vc between L layer wiring and lower layer wiring,
- It shows the situation in which the defect occurred in the contact area.

第1図に於て2はSi基板1上に成長さぜたSiO3膜
、6は5IO2膜2」、−に被着された純又はSi含有
Alから成る下層配線である。下層配線6の形成後、そ
の表面には薄いAl2O3の)換4が生じるが、こyt
はもちろん意図して発生させたものではない。下層配線
の形成後に全面に層間絶縁膜5が被着されたイ〔、:、
下層配線乙の上方の層間杷わ!< llp、’、35が
フォトエツチングによって除去され、スルーポールすな
わち接続用開口部5aが形成される。次に層mJ絶縁1
摸5の上に上層配線6が被着され、該接続用開口部5a
に於て上層配線6と下層配線ろとが接続さシ]、るがA
l2O3の股4が右在才るため、電気的には接続不良と
なる、 この発明VC,l−′−いては、多層配線の工程でA1
203j摸の発生を防止することは外部環境の制御のみ
では不可能であること、Al2O3は化学的に安シ1で
はあるが還元することは可能であること等に渚目し、A
1よりも被酸化性が強い一金属、すなわち次式のように
AI。03を還元すると、−もに自身MO2M2o3を
形成する金属Mを上層配線材料のAl中に添加すること
りこより、前記問題点を解決したものである。
In FIG. 1, 2 is a SiO3 film grown on a Si substrate 1, and 6 is a lower layer wiring made of pure or Si-containing Al deposited on the 5IO2 film 2''. After forming the lower layer wiring 6, a thin layer of Al2O3) is generated on its surface.
Of course, this was not intentional. After forming the lower layer wiring, the interlayer insulating film 5 is deposited on the entire surface.
The layer between the layers above the lower layer wiring B! <llp,', 35 is removed by photoetching to form a through pole, that is, a connection opening 5a. Then layer mJ insulation 1
Upper layer wiring 6 is deposited on the pattern 5, and the connection opening 5a
The upper layer wiring 6 and the lower layer wiring are connected at
Since the crotch 4 of l2O3 is bent on the right side, electrical connection will be poor.
Considering that it is impossible to prevent the occurrence of 203j by controlling the external environment alone, and that although Al2O3 is chemically unstable, it is possible to reduce it,
A metal that is more oxidizable than 1, that is, AI as shown in the following formula. The above-mentioned problem was solved by adding the metal M, which itself forms MO2M2o3 when O3 is reduced, to the Al of the upper layer wiring material.

Al2O:(+3M(21’vf)→2Al+3MO(
1\/1203)下層配、線上に自然形成されたA12
o3ば」1式のようにAIに還元されるが、この還元条
件は上層及び下層配線の接続形成に通常行わオしている
400〜500℃のゾンタリング温度条件で十分である
Al2O: (+3M(21'vf) → 2Al+3MO(
1\/1203) Lower layer wiring, A12 naturally formed on the line
It is reduced to AI as shown in formula 1, and the zontering temperature condition of 400 to 500° C., which is normally used to form connections between upper and lower layer wiring, is sufficient for this reduction.

また形成した■〜10若しくはM2O3の酸化物は、」
二式反応によって自然酸化したA1゜03膜のように下
層配線の被覆膜として残存1−2ないでいくつ刀・の固
まりとして残存するから、下層上層配線の接続面はAl
−Alの接続が形DIできる。
In addition, the formed oxide of ■~10 or M2O3 is
Like the A1゜03 film that is naturally oxidized by a two-way reaction, it remains as a coating film for the lower layer wiring, but remains as a lump of 1-2, so the connection surface of the lower layer and upper layer wiring is covered with Al.
-Al connections can be made in DI form.

このようにA1□o、’を還元する被酸化性の強い金属
は1:と(−1てア、ルノノリ土’i’:’1.!金属
、土類金属に属するものが多く、例えはLa l Be
 、 Mg 、 Ca 、 13a及びThなどが前記
条件を満た]、ている、こパ1、らの金属の酸化物はA
l Oよりも解離エネルギーΔF0□982  :( が大きく、化学的に安定でAI。03を還元してA1に
することができる。第1表に上記の各金属酸化物の20
 ’C(298″K)における解離エネルギーンーAl
2O3のそれに比較して示す(詳卸1は誠文堂新丸社発
行「金属イオ料の加〃(と酸化」参照)、第1表 −L層配線月料としてAIに添加する」1記金属の添加
量はOO■〜03重量係である。0.01%未満である
と本発明の効果が現れず、また03%を超えては生成す
るMO(M2O3)が接続を阻害するふそれが生じるか
らである。
In this way, the highly oxidizable metals that reduce A1□o,' are 1: and (-1tea, lunonori earth 'i':'1.! Many of them belong to metals and earth metals, for example, La l Be
, Mg, Ca, 13a and Th satisfy the above conditions], oxides of metals such as Copa 1, etc. are A
The dissociation energy ΔF0□982:( is larger than that of lO, it is chemically stable, and AI.03 can be reduced to A1.
Dissociation energy at 'C (298''K) - Al
A comparison with that of 2O3 is shown below. The amount of metal added is in the range of OO■ to 03% by weight.If it is less than 0.01%, the effect of the present invention will not appear, and if it exceeds 0.03%, the generated MO (M2O3) will inhibit the connection. This is because

以下にその実施例の一つ全記載する。One of the examples will be fully described below.

第2図の如く下層配線6として純Al’Th用いて配線
を行った後、層間絶え、月摸5の形成とフォトエツチン
グとを行って層間絶縁膜5にスルーホール5aを設けた
。」L層配線材としてAlO中に01%のCaミラ加(
7たA1合金を蒸着発生源に用いて」二層配線7を行っ
た後、400〜500°CのN2ガス雰囲気中で熱処理
を行った。熱処理後、上層配線7と下層配線6との接続
部について調査したところ、が、導通試、’、IHT4
の結果、これらのCaOは全く電気的には障害となっ”
τいないことがわかった。
After wiring was performed using pure Al'Th as the lower layer wiring 6 as shown in FIG. 2, the layers were separated, a moon pattern 5 was formed, and a through hole 5a was formed in the interlayer insulating film 5 by photoetching. ”01% Ca mira added in AlO as L layer wiring material (
After the two-layer wiring 7 was formed using the A1 alloy 7 as a vapor deposition source, heat treatment was performed in an N2 gas atmosphere at 400 to 500°C. After the heat treatment, the connection between the upper layer wiring 7 and the lower layer wiring 6 was investigated, and a continuity test was performed.
As a result, these CaOs do not pose any electrical problem.
It turned out that there was no τ.

〔発明の効果〕〔Effect of the invention〕

以上のよう1へ、この発明によれば、従来、接続不良を
生じゃ才力・った多層配線が接続不良な生じることなく
形成−yit、従、って半導体装置の歩留り及びイを軸
性を改善することができる。
As described above, according to the present invention, multi-layer wiring, which conventionally requires a lot of effort to avoid connection failures, can be formed without connection failures, thereby increasing the yield of semiconductor devices. can be improved.

なお、実施例では、この発明を半導体素子の多層配線に
適用する場合のみを示したが、本発明が半導体素子ばか
りでなく、他の電子部品等にも適用しうろことは明らか
であイ)。
In addition, in the examples, only the case where the present invention is applied to multilayer wiring of semiconductor elements is shown, but it is clear that the present invention can be applied not only to semiconductor elements but also to other electronic parts etc.) .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(イ)乃至(ハ)は半導体装置の製造工程Vr、
丸・ける配線形成工程と該工程で生じる問題点とを説ツ
]するための図、第2図は本発明の方法により配線形成
を行った半導体装置の断面図である。 1・・・基板、2・・・SiO2膜、6・・下層配線、
4・・・Al2O3の膜、5・・・層間絶縁j良、6.
7・・・上層配線。 特許出願人 東京芝浦軍気株式会月 第1図 (ハ) 第2図
FIGS. 1(A) to 1(C) show the semiconductor device manufacturing process Vr,
FIG. 2 is a cross-sectional view of a semiconductor device in which wiring is formed by the method of the present invention. 1... Substrate, 2... SiO2 film, 6... Lower layer wiring,
4... Al2O3 film, 5... Good interlayer insulation, 6.
7... Upper layer wiring. Patent applicant: Tokyo Shibaura Gunki Co., Ltd. Figure 1 (c) Figure 2

Claims (1)

【特許請求の範囲】 1 下層配線を形成した後−F層配線全形成し、両配線
の一部を接触させて半導体装置の多層配線を形成するに
あたり、下層配線拐料としてAIヲ用いるとともに、上
層配線拐料としてAIよりも被酸化性の強いTh、La
、Be、、Mg。 Ca 、 J3a等の金属p 0.01〜0.3%含有
しrvA]合金を用いることを特徴とする半導体装置の
多層配線形成方法、
[Scope of Claims] 1. After forming the lower layer wiring, all the F layer wiring is formed, and a part of both wirings are brought into contact to form a multilayer wiring of a semiconductor device. In addition, AI is used as a lower layer wiring material, Th and La, which are more oxidizable than AI, are used as upper layer wiring materials.
, Be, , Mg. A method for forming a multilayer interconnection of a semiconductor device, characterized by using an alloy containing 0.01 to 0.3% of metal p such as Ca, J3a, etc.
JP15591082A 1982-09-09 1982-09-09 Forming method for multilayer wiring of semiconductor device Pending JPS5946047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15591082A JPS5946047A (en) 1982-09-09 1982-09-09 Forming method for multilayer wiring of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15591082A JPS5946047A (en) 1982-09-09 1982-09-09 Forming method for multilayer wiring of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5946047A true JPS5946047A (en) 1984-03-15

Family

ID=15616180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15591082A Pending JPS5946047A (en) 1982-09-09 1982-09-09 Forming method for multilayer wiring of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5946047A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62239381A (en) * 1986-04-08 1987-10-20 Sony Corp Noise reduction circuit for fm recording and reproducing system
JP2020031095A (en) * 2018-08-21 2020-02-27 株式会社東芝 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62239381A (en) * 1986-04-08 1987-10-20 Sony Corp Noise reduction circuit for fm recording and reproducing system
JP2020031095A (en) * 2018-08-21 2020-02-27 株式会社東芝 Semiconductor device
US10784109B2 (en) 2018-08-21 2020-09-22 Kabushiki Kaisha Toshiba Semiconductor device

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