JPS5941830A - Forming method for bump electrode - Google Patents
Forming method for bump electrodeInfo
- Publication number
- JPS5941830A JPS5941830A JP57151325A JP15132582A JPS5941830A JP S5941830 A JPS5941830 A JP S5941830A JP 57151325 A JP57151325 A JP 57151325A JP 15132582 A JP15132582 A JP 15132582A JP S5941830 A JPS5941830 A JP S5941830A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- semiconductor substrate
- electrode
- substrate
- cylindrical body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 27
- 238000007747 plating Methods 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000004065 semiconductor Substances 0.000 abstract description 52
- 239000007788 liquid Substances 0.000 abstract description 13
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 12
- 229910052709 silver Inorganic materials 0.000 description 12
- 239000004332 silver Substances 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 239000011521 glass Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000008188 pellet Substances 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005453 pelletization Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
この発明はメッキ方法に関し、より詳細には半導体装置
等におけるバンプ電極の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a plating method, and more particularly to a method for forming bump electrodes in semiconductor devices and the like.
背景技術
ダブルヒートシンクダ、ｆオードに用いられるベレット
１は、第１図に示すように、裏面に薄いカソード電極２
を有し、表面にバンプ状のアノード電極８を有する。な
お、図において、４はＮ＋型基板領域、５はＮ−型カソ
ード領域、６はＰ型カソード領域、７は酸化膜等の絶縁
膜である。そして、前記カソード電極２は金蒸着膜８と
銀メッキ膜１０によって形成され、アノード電極８は下
地に金蒸着膜９を有し、その上に銀のバンプ電極１１を
有している。このアノード電極８はペレット１と一対の
ヒートシンク（図示せず）にて挾持して、その外周にガ
ラスバルブを融着封止する場合の、ベレット１とヒート
シックとの膨張係数差に基づく応力を吸収し、かつペレ
ット１とヒートシンクとを電気的に低抵抗で接触状態に
保持するのに役立つもので、その高さ寸法Ｈは一般に５
０〜６０μｍ程度もある。BACKGROUND TECHNOLOGY A bullet 1 used in a double heat sink and an f-ode has a thin cathode electrode 2 on the back side, as shown in FIG.
It has a bump-shaped anode electrode 8 on its surface. In the figure, 4 is an N+ type substrate region, 5 is an N- type cathode region, 6 is a P type cathode region, and 7 is an insulating film such as an oxide film. The cathode electrode 2 is formed of a gold evaporation film 8 and a silver plating film 10, and the anode electrode 8 has a gold evaporation film 9 as a base and a silver bump electrode 11 thereon. This anode electrode 8 is sandwiched between the pellet 1 and a pair of heat sinks (not shown), and when a glass bulb is fused and sealed on the outer periphery of the pellet, stress due to the difference in expansion coefficient between the pellet 1 and the heat sink is absorbed. It absorbs heat and serves to maintain electrical contact between the pellet 1 and the heat sink with low electrical resistance, and its height dimension H is generally 5.
It also has a diameter of about 0 to 60 μm.
ところで、上記のアノード電ＦＭ３は、次のようにして
形成されている。まず、Ｎ＋型基板領域４゜Ｎ−型ベー
ス領域５．Ｐ型カソード領域６．絶縁膜７を有する半導
体基板１８を製作し、表面全面に金蒸着膜９を形成した
のち、周知のフォトエツチング法等によってその不要部
分を除去し、続いて裏面全面に金蒸着膜８を形成する（
第２図）。次に、この半導体基板１３をメッキ液中に浸
漬して、裏面の金蒸着膜８をメッキ電源の負極に接続し
、金蒸着膜８と所定間隙離して対向配置した銀電極板を
メッキ電源の正極に接続して、金蒸着膜８上に銀メッキ
膜１０を形成する。このとき表面の金蒸着膜９上にも銀
メッキ膜が形成されるが、何ら支障はない。さらに、前
記銀メッキ膜１０をメ・ンキ電源の負極に接続して表面
の銀メツキ膜上に銀のバンプ電ＦＭ１１を形成すること
により形成されている（第３図）。By the way, the above-mentioned anode electrode FM3 is formed as follows. First, N+ type substrate region 4°N- type base region 5. P-type cathode region6. After manufacturing a semiconductor substrate 18 having an insulating film 7 and forming a gold evaporation film 9 on the entire surface, unnecessary parts thereof are removed by a well-known photoetching method, etc., and then a gold evaporation film 8 is formed on the entire back surface. (
Figure 2). Next, this semiconductor substrate 13 is immersed in a plating solution, the gold vapor deposited film 8 on the back side is connected to the negative electrode of the plating power source, and a silver electrode plate placed facing the gold vapor deposited film 8 with a predetermined gap is connected to the plating power source. A silver plating film 10 is formed on the gold vapor deposited film 8 by connecting to the positive electrode. At this time, a silver plating film is also formed on the gold vapor deposited film 9 on the surface, but this does not cause any problem. Furthermore, the silver bump electrode FM11 is formed by connecting the silver plating film 10 to the negative electrode of a metal plate power source and forming a silver bump electrode FM11 on the silver plating film on the surface (FIG. 3).
」二記バンプ電極１１の形成方法には、従来浸漬メッキ
法といわれる方法が採用されていた。この方法は半導体
基板１８の裏面の銀メッキ膜１０にニッケル等の金属テ
ープを貼り付けたのち、アビニシンワックス等のワック
スによって半導体基板１８をその裏面をもってガラス板
等に固着し、これをメッキ液中に浸漬して半導体基板１
８と電極板とを所定間隔で対向配置して、金属テープを
利用してメッキする方法である。しかしながら、この方
法は金属テープやガラス板等の資材を必要とするのみな
らず、メッキ作業に先立って金属テープの貼り付けやガ
ラス基板への固着が必要であり、またメッキ作業終了後
は、半導体基板１３をガラス板から取り外すために、有
機溶剤によるワ、ソクスの溶解が必要になり、有機溶剤
が必要であるばかりでなく、公害防止のために廃液の処
理も必要で著しく煩雑となり、原価高になるという問題
点があった。A method called immersion plating has conventionally been adopted as a method for forming the bump electrodes 11. In this method, a metal tape such as nickel is attached to the silver plating film 10 on the back side of the semiconductor substrate 18, and then the back side of the semiconductor substrate 18 is fixed to a glass plate or the like using wax such as avinyl wax. Semiconductor substrate 1 is immersed in
In this method, the electrode plate 8 and the electrode plate are arranged facing each other at a predetermined interval and plated using a metal tape. However, this method not only requires materials such as metal tape and glass plates, but also requires pasting the metal tape and fixing it to the glass substrate before plating, and after the plating is completed, the semiconductor In order to remove the substrate 13 from the glass plate, it is necessary to dissolve the wax with an organic solvent, and not only is the organic solvent required, but also the treatment of waste liquid is required to prevent pollution, which is extremely complicated and increases the cost. There was a problem with becoming.
そこで、最近では、第４図および第５図に示すようなメ
ッキ装置を使用する。いわゆる噴流メ・ツギ法が採用さ
れている。第４図はメッキ装置の平面図を示し、第５図
は第４図のＶ−ｖ線に沿う断面図を示す。図において、
２０は合成樹脂等の絶縁物よりなる円筒体で、その上端
肩部は面取りされて傾斜面２１となっている。２２は円
筒体２・０の上部に所定寸法Ｇだけ突出して所定間隔で
複数個（図示例は４個）設けられた半導体基板１３の支
持ピン、２３は前記支持ピンの外側に、前記支持ピン２
２の突出寸法Ｇよりも大きい寸法りだけ突出して所定間
隔で複数個（図示例は４個）設けられた半導体基板１８
の位置決め用ピンである。Therefore, recently, a plating apparatus as shown in FIGS. 4 and 5 is used. The so-called jet flow method is adopted. FIG. 4 shows a plan view of the plating apparatus, and FIG. 5 shows a sectional view taken along line V--V in FIG. 4. In the figure,
Reference numeral 20 denotes a cylindrical body made of an insulating material such as synthetic resin, and its upper shoulder is chamfered to form an inclined surface 21. Reference numeral 22 indicates support pins for the semiconductor substrate 13, which are provided at a predetermined interval (four in the illustrated example) and protrude from the upper part of the cylindrical body 2.0 by a predetermined dimension G; 2
A plurality of semiconductor substrates 18 (four in the illustrated example) are provided at predetermined intervals to protrude by a dimension larger than the protrusion dimension G of No. 2.
This is a positioning pin.
２４は円筒体２０内に配置された電極、２５は半導体基
板１３の押え治具を兼ねる電極で、前記電極２４がメッ
キ電源２６の正極に、まだ電極２５がメッキ電源２６の
負極に接続される。24 is an electrode arranged inside the cylindrical body 20, and 25 is an electrode that also serves as a holding jig for the semiconductor substrate 13. The electrode 24 is connected to the positive electrode of the plating power source 26, and the electrode 25 is connected to the negative electrode of the plating power source 26. .
次に、このメッキ装置を用いた噴流メッキ方法について
説明する。まず、第５図に二点鎖線で示すように、第８
図においてバンプ電１ｉｉｉｔｉが未だ形成されていな
い状態の半導体基板１３を、その表面すなわち金蒸着膜
９側を下側に向けて支持ピン２２の上に載置する。そし
て、この半導体基板１３の裏面上に電極２５を載置して
、半導体基板１３を押圧して水平状態に保持するととも
に、半導体基板１３のカソード電極２と電ｆＭ２５との
電気的接続を良好にする。この状態で、円筒体２゜の下
方からメッキ液２７を噴き上げると、メッキ液２７は半
導体基板１３の下面すなわち表面に衝突し放射方向に流
れ広がって、円筒体２０の上端面と半導体基板１８の下
面との隙間を通って四方に溢流する。したがって、メッ
キ電源２６により電極２４．２５間に通電すると、電流
が電極２４からメッキ液２７および半導体基板１３を通
って電極２５に流れて、半導体基板１３の表面の銀メツ
キ膜上に銀のバンプ電極１１が形成される。Next, a jet plating method using this plating apparatus will be explained. First, as shown by the two-dot chain line in FIG.
In the figure, the semiconductor substrate 13 on which the bump electrodes 1iii are not yet formed is placed on the support pins 22 with its surface, that is, the gold vapor deposited film 9 side facing downward. Then, an electrode 25 is placed on the back surface of the semiconductor substrate 13 to press the semiconductor substrate 13 and hold it in a horizontal state, and to establish a good electrical connection between the cathode electrode 2 of the semiconductor substrate 13 and the electric fM25. do. In this state, when the plating liquid 27 is sprayed up from below the cylindrical body 2°, the plating liquid 27 collides with the lower surface of the semiconductor substrate 13, flows in the radial direction, and spreads between the upper end surface of the cylindrical body 20 and the semiconductor substrate 18. It overflows in all directions through the gap with the bottom surface. Therefore, when electricity is applied between the electrodes 24 and 25 by the plating power supply 26, the current flows from the electrode 24 through the plating solution 27 and the semiconductor substrate 13 to the electrode 25, and the silver bumps are formed on the silver plating film on the surface of the semiconductor substrate 13. Electrode 11 is formed.
上記の噴流メッキ法によれば、浸漬メッキ法に比較して
、金属テープ、ガラス板、ワックス、有機溶剤等の諸資
材が一切不要で、資材費を著しく節減できるのみならず
、それらを用いる処理も不要になるため加工費も著しく
節減できるという利点がある。According to the jet plating method described above, compared to the dip plating method, various materials such as metal tapes, glass plates, wax, organic solvents, etc. are not required at all, and not only can material costs be significantly reduced, but also the processing using them This has the advantage that the processing cost can be significantly reduced since it is no longer necessary.
しかしながら、上記の噴流メッキ法では、半導体基板１
８の位置決めピン２８の存在によって、次のような不都
合な点があった。すなわち、円筒体２０の上端面と半導
体基板１３の下面との隙間を通って溢流したメッキ液２
７が、前記位置決めピン２８に衝突し流れが乱れてメッ
キ液面が上下動しやすく、しかもメッキ液２７が位置決
めピン２３を伝って半導体基板１８の側面を濡らし、甚
しい場合は半導体基板１８の裏面にまで廻り込みやすい
。もしこのような状態になると、メッキ電流が半導体基
板１３の周縁部へ集中するようになり、第６図に示すよ
うに、半導体基板１８の周縁部のバンプ電ｔｉｌｌａが
非常に厚く大きくなり、これに伴って周縁部近傍のバン
プ電１ｉｔ１ｂが薄く小さくなる。このため、周縁部の
ベレットが不良になることはもちろん、周縁部近傍のバ
ンプ電％ １ ｔ ｂをはじめ他のバンプ電極の成長速
度が小さくなって、メッキ時間が長くなり、周縁部近傍
のバンプ電１ｉｔｔｂを正常な高さ寸法まで成長させよ
うとすると、周縁部のバンプ電１’Ｍ１１ａはますます
犬＾くなって、周縁部近傍のバンプ電１ｌｌｂと連絡し
てしまい、周縁部近傍のペレットをも不良にすることに
なる。さらには、半導体基板１３の裏面にまでバンプ電
極１１ａが廻り込んで形成されると、半導体基板１３を
ダイシングマシンで切断分離してペレノタイズする工程
で、半導体基板１３の中央部がダイシングステージから
浮き上を強くして無理に吸着すると、半導体基板１３が
湾曲して、ダイシング時に半導体基板１３に水平方向の
クラックが生じ、半導体基板１３が破損して飛び散ると
いった問題点があった。However, in the jet plating method described above, the semiconductor substrate 1
The presence of the positioning pins 28 of No. 8 has the following disadvantages. That is, the plating solution 2 overflowed through the gap between the upper end surface of the cylindrical body 20 and the lower surface of the semiconductor substrate 13.
7 collides with the positioning pin 28, the flow is disturbed, and the plating liquid level tends to move up and down.Moreover, the plating liquid 27 travels along the positioning pin 23 and wets the side surface of the semiconductor substrate 18, and in severe cases, the plating liquid 27 may wet the side surface of the semiconductor substrate 18. Easy to get around to the back side. If this happens, the plating current will concentrate on the peripheral edge of the semiconductor substrate 13, and as shown in FIG. 6, the bump electric charge on the peripheral edge of the semiconductor substrate 18 will become very thick and large. Accordingly, the bump electrode 1it1b near the peripheral edge becomes thinner and smaller. As a result, not only the pellets near the periphery become defective, but also the growth rate of other bump electrodes including the bump electrode near the periphery decreases, the plating time becomes longer, and the bumps near the periphery decrease. When trying to grow the electric field 1ittb to its normal height, the bump electric field 1'M11a at the periphery becomes more and more dog-like and connects with the bump electric field 1llb near the periphery, causing the pellets near the periphery to grow. It will also make it defective. Furthermore, when the bump electrodes 11a are formed around the back surface of the semiconductor substrate 13, the center part of the semiconductor substrate 13 is lifted off the dicing stage during the step of cutting and separating the semiconductor substrate 13 with a dicing machine and pelletizing it. If the semiconductor substrate 13 is forcibly attracted by increasing the strength, there is a problem that the semiconductor substrate 13 is curved, horizontal cracks are generated in the semiconductor substrate 13 during dicing, and the semiconductor substrate 13 is damaged and scattered.
発明の開示
この発明は上記の噴流メッキ法によるバンプ電極の形成
方法において、メッキ液が半導体基板等の側面および裏
面に廻り込まず、バンプ電極の高さおよび大きさを均斉
化できる形成方法を提供することを目的とする。DISCLOSURE OF THE INVENTION The present invention provides a method for forming bump electrodes using the above-mentioned jet plating method, which prevents the plating solution from going around the side and back surfaces of a semiconductor substrate, etc., and makes it possible to equalize the height and size of the bump electrodes. The purpose is to
この発明は上記目的達成のために、基板の上面を電極兼
用の吸着治具で吸着し、しかもこの基板の下面を少なく
とも位置決めピンを有しないメッキ装置の上面から所定
寸法だけ離隔させた状態でメッキすることを特徴とする
。In order to achieve the above-mentioned object, this invention attracts the top surface of a substrate with a suction jig that also serves as an electrode, and plating the bottom surface of the substrate at least a predetermined distance away from the top surface of a plating device that does not have positioning pins. It is characterized by
そして、上記のような位置決めピンを用いない構成によ
って、メッキ液が基板の側面および裏面に廻り込むこと
を防止し、もって前記の問題点のない均斉な高さおよび
大きさのバンプ電極を形成できるという作用効果を奏す
るものである。In addition, the above-mentioned configuration that does not use positioning pins prevents the plating solution from getting around to the side and back surfaces of the substrate, thereby making it possible to form bump electrodes with uniform height and size that do not have the above-mentioned problems. This has the following effects.
全面を実施するための最良の形態 以下、この発明の実施例を図面を参照して説明する。Best form for full implementation Embodiments of the present invention will be described below with reference to the drawings.
第７図はこの発明に係るバンプ電極の形成方法について
説明するためのメッキ装着の断面図である。図において
、３ｏは絶縁物よりなる円筒体で、」二端肩部は面取り
されて傾斜面３１となっている。FIG. 7 is a sectional view of plating installation for explaining the method of forming a bump electrode according to the present invention. In the figure, 3o is a cylindrical body made of an insulator, and the shoulders at the two ends are chamfered to form an inclined surface 31.
そして、この円筒体８ｏの上面には、第５図に示す従来
のメノギ装置と異なって、半導体基板１・８の位置決め
ピン２３はもちろん支持ピン２２も存在していないこと
に注目されたい。３２は前記円筒体３０の中心部に配置
されたメッキ電極、３８は下面に真空吸引孔３８ａを有
する電極兼用の吸着治具で、３４はメッキ電源である。It should be noted that, unlike the conventional agate device shown in FIG. 5, there are not only positioning pins 23 for the semiconductor substrates 1 and 8 but also support pins 22 on the upper surface of the cylindrical body 8o. 32 is a plating electrode arranged at the center of the cylindrical body 30, 38 is a suction jig that also serves as an electrode and has a vacuum suction hole 38a on the bottom surface, and 34 is a plating power source.
上記吸着治具３３はレバー（図示せず）等によって移動
可能 １゜に支持されている。
１次に、このメッキ装置を用いたバンプ電
極の形 ｊ成力法について説明する。まず、図示しな
いレノ〈−等を操作して、吸着治具８８を図示しない定
位 １置に移動させて半導体基板１８を吸着させた
のち、レバー等を操作して吸着治具３３を図示する位置
に移動させる。すなわち、半導体基板１３の下面（表面
）が円筒体８ｏの上端から寸法Ｇだけ離隔するように保
持する。この状態で、円筒体３ｏの下方からメッキ液３
５を噴き上げると、メッキ液３５は半導体基板１８の下
面に衝突しかつ案内されて放射方向に流れ広がって、円
筒体３ｏの上面と半導体基板１３との隙間を通って四方
から溢流する。このとき、第５図に示すような支持ピン
２２や位置決めピン２３が存在しないので、溢流したメ
ッキ液３５の乱れに′よる液面の」二下動かなくなり、
しかも位置決めピン２３を伝ってメッキ液３５が半導体
基板１３の側面および裏面まで廻り込むことがなくなる
。このため、半導体基板１３の周瞭部へのメッキ電流の
集中が起らなくなり、これで伴って周縁部のバンプ電極
の異常成長や周縁部１傍のバンプ電極の成長速度低下も
起らなくなり、ト導体基板１８の表面全面に均斉な高さ
および大賢さのバンプ電極１１が形成される。このため
、バンプ電ＦＭｌｌの形成に要するメッキ時間は短くて
すむし、メッキ液の疲労やむだも激減する。また、上記
実施例のように、位置決′めピン２８のみならず支持ピ
ン２２をも無くした場合は、従来この支持ピン２２０当
接部分におけるバンプ電極１１の高さが他の部分のバン
プ電極１１より１０μｍ程度低くなっていた現象をもな
くすことができるという利点がある。The suction jig 33 is movably supported at 1° by a lever (not shown) or the like.
First, a method for forming bump electrodes using this plating apparatus will be explained. First, by operating a lever (not shown) or the like, the suction jig 88 is moved to a fixed position (not shown) to suction the semiconductor substrate 18, and then a lever or the like is operated to move the suction jig 33 to the position shown in the figure. move it to That is, the semiconductor substrate 13 is held so that the lower surface (front surface) of the semiconductor substrate 13 is spaced apart from the upper end of the cylindrical body 8o by a distance G. In this state, the plating solution 3 is applied from below the cylindrical body 3o.
5, the plating liquid 35 collides with the lower surface of the semiconductor substrate 18 and is guided to flow and spread in the radial direction, overflowing from all sides through the gap between the upper surface of the cylindrical body 3o and the semiconductor substrate 13. At this time, since there are no support pins 22 or positioning pins 23 as shown in FIG.
Furthermore, the plating liquid 35 is prevented from flowing along the positioning pins 23 to the side and back surfaces of the semiconductor substrate 13. Therefore, concentration of plating current on the peripheral part of the semiconductor substrate 13 does not occur, and accordingly, abnormal growth of the bump electrodes on the peripheral part and a decrease in the growth rate of the bump electrodes near the peripheral part 1 do not occur. Bump electrodes 11 of uniform height and width are formed over the entire surface of the conductive substrate 18. Therefore, the plating time required to form the bump electrode FMll is short, and fatigue and waste of the plating solution are drastically reduced. Furthermore, as in the above embodiment, when not only the positioning pin 28 but also the support pin 22 is eliminated, the height of the bump electrode 11 at the part where this support pin 220 contacts is higher than that of the bump at other parts. There is an advantage in that the phenomenon that the height was lowered by about 10 μm compared to No. 11 can be eliminated.
なお、上記実施例はＤＨＤのバンプ電極を形成する場合
について説明したが、フェースダウンボンティング（Ｆ
ＤＢ ）半導体装置や、ビームリード（ＢＬ）半導体装
置のビームリード等を形成する場合にも実施できる。さ
らには半導体装置のバンプ電極のみならず、他の電子回
路基板等のバンプ電極を形成する場合にも実施できる。Note that although the above embodiment describes the case of forming bump electrodes for a DHD, face-down bonding (F
It can also be carried out when forming a beam lead of a DB) semiconductor device or a beam lead (BL) semiconductor device. Furthermore, it can be carried out not only when forming bump electrodes of semiconductor devices but also when forming bump electrodes of other electronic circuit boards and the like.
第１図はダブルヒートシンクダイオード用ノベレソトの
断面図、第２図および第３図はバンプ電極の形成工程に
ついて説明するだめの各段階の半導体基板の断面図、第
４図および第５図はこの発明の背景となる噴流メッキ法
によるバンプシ公の形成方法について説明するためのメ
ッキ装置を示し、第４図は平面図、第５図は第４図の■
−■線に沿う断面図、第６図は従来の噴流メッキ法によ
るバンプ電極の形成方法において生じる不良状態を示す
半導体基板の断面図、第７図はこの発明の噴流メッキ法
によるバンプ電極の形成方法について説明するためのメ
ッキ装置の断面図である。
１１・・・・・・バンプ電極、
１８・・・・・・半導体基板、
３０・・・・・・メッキ装置（円筒体）、３８・・・・
・・電極兼吸着治具。
第１図
第２図
３
第４図Figure 1 is a cross-sectional view of a novel battery for double heat sink diodes, Figures 2 and 3 are cross-sectional views of a semiconductor substrate at various stages for explaining the process of forming bump electrodes, and Figures 4 and 5 are cross-sectional views of a semiconductor substrate according to the present invention. Fig. 4 is a plan view, and Fig. 5 is a plating device for explaining the method of forming bumps using the jet plating method, which is the background of the process.
6 is a sectional view of a semiconductor substrate showing a defective state that occurs in the conventional jet plating method for forming bump electrodes, and FIG. 7 is a bump electrode formation method using the jet plating method of the present invention. FIG. 2 is a sectional view of a plating apparatus for explaining the method. 11...Bump electrode, 18...Semiconductor substrate, 30...Plating device (cylindrical body), 38...
...Electrode/suction jig. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
する際に、基板の他主面を電極兼用の吸着治具で吸着し
てこの基板の一生面を上端に少なくとも位置決めピンを
有しないメッキ装置の上面から所定寸法だけ離隔させた
状態でメッキすることを特徴とするバンプ電極の形成方
法。When forming bump electrodes on the entire surface of a substrate by jet plating, the other main surface of the substrate is adsorbed using a suction jig that also serves as an electrode, and the entire surface of the substrate is attached to the upper end using a plating device that does not have at least a positioning pin. A method for forming a bump electrode, characterized by plating at a predetermined distance from an upper surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57151325A JPS5941830A (en) | 1982-08-31 | 1982-08-31 | Forming method for bump electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57151325A JPS5941830A (en) | 1982-08-31 | 1982-08-31 | Forming method for bump electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5941830A true JPS5941830A (en) | 1984-03-08 |
Family
ID=15516141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57151325A Pending JPS5941830A (en) | 1982-08-31 | 1982-08-31 | Forming method for bump electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5941830A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61216345A (en) * | 1985-03-20 | 1986-09-26 | Nec Kansai Ltd | Manufacture of semiconductor element |
| JPS6439045A (en) * | 1987-08-04 | 1989-02-09 | Sanyo Electric Co | Formation of projecting electrode |
| DE10027931C1 (en) * | 2000-05-31 | 2002-01-10 | Infineon Technologies Ag | Method for rear-side electrical contacting of a semiconductor substrate during its processing |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5739438B2 (en) * | 1976-09-07 | 1982-08-21 |
-
1982
- 1982-08-31 JP JP57151325A patent/JPS5941830A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5739438B2 (en) * | 1976-09-07 | 1982-08-21 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61216345A (en) * | 1985-03-20 | 1986-09-26 | Nec Kansai Ltd | Manufacture of semiconductor element |
| JPS6439045A (en) * | 1987-08-04 | 1989-02-09 | Sanyo Electric Co | Formation of projecting electrode |
| DE10027931C1 (en) * | 2000-05-31 | 2002-01-10 | Infineon Technologies Ag | Method for rear-side electrical contacting of a semiconductor substrate during its processing |
| US6746880B2 (en) | 2000-05-31 | 2004-06-08 | Infineon Technologies Ag | Method for making electrical contact with a rear side of a semiconductor substrate during its processing |
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