JPS5941205B2 - electronic circuit - Google Patents
electronic circuitInfo
- Publication number
- JPS5941205B2 JPS5941205B2 JP55156713A JP15671380A JPS5941205B2 JP S5941205 B2 JPS5941205 B2 JP S5941205B2 JP 55156713 A JP55156713 A JP 55156713A JP 15671380 A JP15671380 A JP 15671380A JP S5941205 B2 JPS5941205 B2 JP S5941205B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- integrated circuit
- data retention
- circuit section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Direct Current Feeding And Distribution (AREA)
- Power Sources (AREA)
- Microcomputers (AREA)
Description
【発明の詳細な説明】
本発明はマイクロコンピュータ等に用いられ、乾電池等
によりバックアップされ内部データ保持等のみを行なう
データ保持動作時における低消費電力化を図るための電
子回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic circuit used in a microcomputer, etc., for reducing power consumption during a data retention operation backed up by a dry battery or the like and only retaining internal data.
一般にこの種の電子回路は、データ保持動作時に乾電池
等によりバックアップされる場合、データ保持動作時の
消費電力の低下を図るため、内部データ保持に必要な下
限まで電源電圧を下げるようにしている。Generally, when this type of electronic circuit is backed up by a dry battery or the like during data retention operation, the power supply voltage is lowered to the lower limit necessary for internal data retention in order to reduce power consumption during data retention operation.
これと同時に、内部データを保持するために書き込み禁
止信号等を内部で発生させるかあるいは外部から供給し
、この信号を内部で使用してデータ保持を実現している
。さらに消費電力を低下させるためには、データ保持の
必要のある集積回路Ａとデータ保持の必要のない集積回
路Ｂとに分け、それぞれ別々の電源系統Ａ、Ｂにより動
作させるものとし、データ保持動作時に電源系統Ａの電
源電圧を必要最低限まで下げ、電源系統Ｂへの電源供給
を遮断している。ここで、第１図を参照して従来の電子
回路の具体例を説明する。At the same time, in order to retain internal data, a write inhibit signal or the like is generated internally or supplied from the outside, and this signal is used internally to achieve data retention. In order to further reduce power consumption, integrated circuit A, which requires data retention, and integrated circuit B, which does not require data retention, are separated, and each is operated by separate power supply systems A and B. At times, the power supply voltage of power supply system A is lowered to the minimum necessary level, and the power supply to power supply system B is cut off. Here, a specific example of a conventional electronic circuit will be explained with reference to FIG.
１１は電源系統Ａの集積回路Ａの入力回路部であり、こ
の集積回路Ａはデータ保持動作時には乾電池等によりバ
ックアップされ、電源電圧が集積回路Ａの必要最低限ま
で下げられるものである。Reference numeral 11 denotes an input circuit section of the integrated circuit A of the power supply system A. This integrated circuit A is backed up by a dry battery or the like during data retention operation, and the power supply voltage is lowered to the minimum level necessary for the integrated circuit A.
この集積回路Ａは、たとえばＮチャンネルの絶縁ゲート
電界効果型トランジスタ（以下ＭＯＳ−ＦＥＴと云う。
）よりなり、入力線（集積回路Ａの入力端子）１２がＥ
／Ｄタイプのインバータ回路のＥ（エンハンスメント）
型トランジスタＴ４のゲートに接続されている。このＥ
型トランジスタＴ３のソースは接地され、ドレインはＤ
（デプレツシヨン）型トランジスタＴ。のソースに接続
されている。このＤ型トランジスタＴ。のドレインは電
源ライン１３に接続され、ソースは入力回路部１１の出
力を次段に伝えるための出力線１４に接続されている。
さらに、電源ライン１３と入力線１２との間にはプルア
ップ抵抗としてＤ型トランジスタＴ３のドレーン−ソー
ス間が接続され、このトランジスタＴ３はゲート・ソー
ス相互が接続されている。一方、１５は電源系統Ｂの集
積回路Ｂの出力回路部であり、保持動作時には電源系統
Ｂへの電源供給が遮断され．、この集積回路Ｂは動作し
ない。This integrated circuit A is, for example, an N-channel insulated gate field effect transistor (hereinafter referred to as MOS-FET).
), and the input line (input terminal of integrated circuit A) 12 is E
/E (enhancement) of D type inverter circuit
type transistor T4. This E
The source of type transistor T3 is grounded, and the drain is connected to D
(depression) type transistor T. connected to the source. This D type transistor T. Its drain is connected to a power supply line 13, and its source is connected to an output line 14 for transmitting the output of the input circuit section 11 to the next stage.
Furthermore, between the power supply line 13 and the input line 12, the drain and source of a D-type transistor T3 are connected as a pull-up resistor, and the gate and source of this transistor T3 are connected to each other. On the other hand, 15 is an output circuit section of integrated circuit B of power supply system B, and the power supply to power supply system B is cut off during the holding operation. , this integrated circuit B does not operate.
ここで１６は電源ライン、１７は集積回路Ｂの出力端子
となる出力線であり、前記入力線１２に接続されている
。第２図ＡないしＣはそれぞれ、第１図回路における一
方の集積回路Ｂの出力回路部１７を具体的に示す回路図
である。Here, 16 is a power supply line, and 17 is an output line serving as an output terminal of integrated circuit B, which is connected to the input line 12. 2A to 2C are circuit diagrams specifically showing the output circuit section 17 of one of the integrated circuits B in the circuit of FIG. 1, respectively.
第２図Ａのものは集積回路ＢがＣ−ＭＯＳのトランジス
タで構成されている場合であり、ＰチヤネルのＥ型トラ
ンジスタ５１とＮチヤネルのＥ型トランジスタ５２とを
備えている。第２図Ｂのものは集積回路Ｂが集積回路Ａ
と同様にＮチヤネルのＭＯＳ−ＦＥＴで構成されている
場合であり、Ｄ型トランジスタ５３とＥ型のトランジス
タ５４とを備えている。第２図Ｃのものは集積回路Ｂが
バイポーラトランジスタで構成されている場合であり、
負荷抵抗５５とＮＰＮトランジスタ５６とを備えている
。而して上記構成の電子回路によれば、集積回路Ａの電
源電圧がその必要最低限まで下げられかつ集積回路Ｂの
電源供給が遮断されるデータの保持動作時においても、
集積回路Ａの電源ライン１３からプルアツプ抵抗用のＤ
型トランジスタＴ３、入力線１２を通じて、集積回路Ｂ
の出力線１７、出力回路部１５へ第１図中に示すような
電流１が流出する。2A shows a case where the integrated circuit B is composed of C-MOS transistors, and includes a P-channel E-type transistor 51 and an N-channel E-type transistor 52. In the case of Figure 2B, integrated circuit B is integrated circuit A.
Similarly, this is a case in which the transistor is composed of N-channel MOS-FETs, and includes a D-type transistor 53 and an E-type transistor 54. Figure 2C shows the case where integrated circuit B is composed of bipolar transistors,
It includes a load resistor 55 and an NPN transistor 56. According to the electronic circuit having the above configuration, even during a data retention operation in which the power supply voltage of integrated circuit A is lowered to the minimum necessary level and the power supply to integrated circuit B is cut off,
D for pull-up resistor from power supply line 13 of integrated circuit A
type transistor T3, through input line 12, integrated circuit B
A current 1 as shown in FIG. 1 flows out to the output line 17 and the output circuit section 15.
たとえば、第２図Ａに示すような出力回路部の場合、ト
ランジスタ５１，５２の各ソース、ドレイン間には第２
図Ａに示すような極性でダイオードＤｌ，Ｄ２が等価的
に接続されている。そしてこの集積回路Ｂの電源供給が
遮断されて電源ライン１６が０Ｖになると、この電源ラ
イン１６よりも集積回路Ａの電源ライン１３の方が高電
位となるためにダイオードＤ１を通して上記電流１が流
れる。また、第２図Ｂに示すような出力回路部で電源供
給が遮断された場合には、負荷抵抗として用いられるＤ
型のトランジスタ５３を通して上記電流１が流れる。さ
らに第２図Ｃに示すような出力回路部でも、電源供給が
遮断された場合には負荷抵抗５５を通して上記電流１が
流れる。これら流出電流１の大きさは、集積回路Ａ，Ｂ
の電源ライン１３，１６間の電位差に比例し、プルアツ
プ抵抗（Ｄ型トランジスタＴ３）の抵抗値に反比例する
。しかし、このような流出電流１は、集積回路Ａの電源
電流の一部であり、集積回路Ａの消費電力の低減化を図
る上で問題になる。すなわち、集積回路Ａの真の電源電
流が上記流出電流１より充分に多い場合には流出電流１
を無視できるが、プルアツプ抵抗の抵抗値が小さい時や
集積回路Ａの真の電源電流が少ないときには流出電流１
を無視できなくなる。このような問題は、集積回路Ａの
入力回路部と集積回部Ｂの出力回路部とのインターフエ
ース部に限らず、集積回路Ａの出力回路部と集積回路Ｂ
の入力回路部とのインターフエース部においても、集積
回路Ａの電源ラインと集積回路Ｂとの間に電流経路（一
般にドライブ回路と称する）を有する場合にも同様に生
じる。For example, in the case of an output circuit section as shown in FIG. 2A, a second
Diodes Dl and D2 are equivalently connected with polarity as shown in Figure A. When the power supply to the integrated circuit B is cut off and the power line 16 becomes 0V, the power line 13 of the integrated circuit A has a higher potential than the power line 16, so the current 1 flows through the diode D1. . In addition, when the power supply is cut off in the output circuit section as shown in Figure 2B, D
The current 1 flows through the type transistor 53. Furthermore, even in the output circuit section as shown in FIG. 2C, the current 1 flows through the load resistor 55 when the power supply is cut off. The magnitude of these outflow currents 1 is
It is proportional to the potential difference between the power supply lines 13 and 16, and inversely proportional to the resistance value of the pull-up resistor (D-type transistor T3). However, such outflow current 1 is a part of the power supply current of integrated circuit A, and becomes a problem in reducing the power consumption of integrated circuit A. That is, if the true power supply current of integrated circuit A is sufficiently larger than the above-mentioned outflow current 1, the outflow current 1
can be ignored, but when the resistance value of the pull-up resistor is small or the true power supply current of integrated circuit A is small, the outflow current 1
can no longer be ignored. Such problems are not limited to the interface between the input circuit section of integrated circuit A and the output circuit section of integrated circuit section B, but also occur between the output circuit section of integrated circuit A and the output circuit section of integrated circuit B.
The same problem occurs when a current path (generally referred to as a drive circuit) is provided between the power supply line of the integrated circuit A and the integrated circuit B in the interface section with the input circuit section of the integrated circuit A.
本発明は上記の事情に鑑みてなされたものであり、集積
回路Ａの入力回路部あるいは出力回路部において集積回
路Ｂの出力回路部あるいは入力回路部との間に接続され
る電流経路に対して通常動作時にはオン状態、データ保
持動作時にはオフ状態に設定することによつて、データ
保持動作時における回路Ａの消費電力を低減し得る電子
回路を提供するものである。The present invention has been made in view of the above circumstances, and is directed to a current path connected between the input circuit section or the output circuit section of the integrated circuit A and the output circuit section or the input circuit section of the integrated circuit B. The present invention provides an electronic circuit that can reduce the power consumption of the circuit A during a data retention operation by setting the circuit A to an on state during normal operation and an off state during a data retention operation.
以下、図面を参照して本発明の一実施例を詳細に説明す
る。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第３図において、２１は電源系統Ａの集積回路Ａにおけ
る入力回路部であり、この集積回路Ａは通常動作時には
正規の電源電圧が供給され、データ保持等を行なうデー
タ保持動作時には乾電池等によりバツクアツプされ、電
源電圧が必要最低限まで下げられるものである。一方、
２２は電源系統Ｂの集積回路Ｂにおける前記第２図Ａな
いしＣのように構成された出力回路部であり、この集積
回路Ｂは通常動作時には正規の電源電圧が供給され、デ
ータ保持動作時には電源供給が遮断される。そして前記
集積回路Ａにおいて、２３は電源ライン２４と信号入力
ライン（入力端子）２５との間に挿入される電流経路で
あり、２６はこの電流経路２３に直列に挿入されたスイ
ツチ回路、たとえばリレー接点である。In FIG. 3, reference numeral 21 is an input circuit section in integrated circuit A of power supply system A. During normal operation, this integrated circuit A is supplied with a regular power supply voltage, and during data retention operation, it is backed up by a dry battery or the like. The power supply voltage can be lowered to the minimum required level. on the other hand,
Reference numeral 22 denotes an output circuit section configured as shown in FIGS. 2A to C in integrated circuit B of power supply system B. This integrated circuit B is supplied with a regular power supply voltage during normal operation, and is supplied with a power supply voltage during data retention operation. Supply is cut off. In the integrated circuit A, 23 is a current path inserted between a power supply line 24 and a signal input line (input terminal) 25, and 26 is a switch circuit inserted in series with this current path 23, such as a relay. It is a point of contact.
このリレー接点２６は、通常動作時にはオン状態になり
、データ保持動作時にはオフ状態となるように制御され
る。なお集積回路Ｂにおいて、２７は電源ライン、２８
は出力信号ライン（出力端子）である。而して上記構成
の電子回路において、通常動・作時には集積回路Ａ，Ｂ
においてそれぞれ所定の電力が消費され、かつ集積回路
Ａの電源ライン２４と集積回路Ｂの出力信号ライン２８
との間にも電流経路２３を経て駆動電流が流れている。This relay contact 26 is controlled so that it is in an on state during normal operation and is in an off state during a data retention operation. Note that in integrated circuit B, 27 is a power supply line, and 28 is a power supply line.
is the output signal line (output terminal). Therefore, in the electronic circuit with the above configuration, during normal operation, integrated circuits A and B
A predetermined amount of power is consumed in each of the power supply line 24 of integrated circuit A and the output signal line 28 of integrated circuit B.
A drive current also flows through the current path 23 between the two.
これに対してデータ保持動作時には、集積回路Ｂは動作
しなくなり、集積回ｊ路Ａは必要最低限の電源電圧でデ
ータ保持等の動作状態となり、リレー接点２６のオフに
より篭流経路２３には電流が流れなくなる。したがつて
、集積回路Ａのデータ保持動作時においては、従来に比
べて電流経路２３の電流に相当する分だけ消費電流が少
なくなり、消費電力が低減する。On the other hand, during data retention operation, integrated circuit B stops operating, integrated circuit path A enters an operating state such as data retention at the minimum necessary power supply voltage, and the relay contact 26 is turned off, so that the cage flow path 23 is not operated. Current stops flowing. Therefore, during the data retention operation of the integrated circuit A, the current consumption is reduced by an amount corresponding to the current of the current path 23 compared to the conventional case, and the power consumption is reduced.
この電力低減は、集積回路Ａの消費電力が少ない点を考
慮すれば、著しく効果がある。なお、一方の集積回路Ａ
を片チヤンネル（たとえばＮチヤンネル）のＭＯＳ−Ｆ
ＥＴで構成した例を第４図、相補型ＭＯＳ−ＦＥＴで構
成した例を第５図に示す。第４図においては、集積回路
Ａの入力回路部として、エンハンスメント型トランジス
タＴ，の負荷にデプレツシヨン型トランジスタＴ２を接
続したＥ／Ｄインバータ３０を用い、電流経路（第３図
２３）およびスイツチ回路（第３図２６）に相当するも
のとしてプルアツプ抵抗用のエンハンスメント型トラン
ジスタＴ４をデータ保持用書き込み禁止信号（集積回路
Ａのデータ保持動作制御信号である）により制御するよ
うにしている。また第５図においては、集積回路Ａの入
力回路部としてＮチヤンネルエンハンスメント型トラン
ジスタＴＮおよびＰチヤンネルエンハンスメント型トラ
ンジスタＴＰｌよりなるインバータ４０を用い、電流経
路およびスイツチ回路に相当するものとしてＰチヤンネ
ルエンハンスメント型トランジスタＴＰ２をデータ保持
用書き込み禁止信号により制御するようにしている。こ
の場合、禁止信号の極・ヰによつては上記トランジスタ
ＴＰ２に代えてＮチヤンネル型を使用してもよい。なお
、第４図および第５図において第３図と同一部分は同一
符号を付してその説明を省略する。本発明は上述したよ
うに、互いの電源系統が異なる集積回路Ａと集積回路Ｂ
とを接続し、集積回路Ａにおけるデータ保持動作時には
集積回路Ａの電源電圧を必要最低限まで下げると共に集
積回路Ｂを動作させないようにする電子回路において、
集積回路Ａのデータ保持動作時における消費電力を低減
させることができ、集積回路Ａの乾電池等によるバツク
アツプなどを行なう上で非常に好都合とし得るものであ
る。This power reduction is extremely effective when considering the fact that the integrated circuit A consumes less power. Note that one integrated circuit A
MOS-F of one channel (for example, N channel)
FIG. 4 shows an example constructed using ETs, and FIG. 5 shows an example constructed using complementary MOS-FETs. In FIG. 4, an E/D inverter 30 in which a depletion type transistor T2 is connected to the load of an enhancement type transistor T is used as an input circuit section of an integrated circuit A, and a current path (FIG. 3 23) and a switch circuit ( 26), the enhancement type transistor T4 for the pull-up resistor is controlled by a write inhibit signal for data retention (which is a data retention operation control signal of the integrated circuit A). Further, in FIG. 5, an inverter 40 consisting of an N-channel enhancement type transistor TN and a P-channel enhancement type transistor TPl is used as the input circuit section of the integrated circuit A, and a P-channel enhancement type transistor is used as a current path and a switch circuit. TP2 is controlled by a write inhibit signal for data retention. In this case, depending on the polarity of the inhibit signal, an N-channel type transistor may be used in place of the transistor TP2. In FIGS. 4 and 5, the same parts as those in FIG. 3 are designated by the same reference numerals, and the explanation thereof will be omitted. As described above, the present invention provides an integrated circuit A and an integrated circuit B having different power supply systems.
In an electronic circuit that connects the integrated circuit A to the integrated circuit A and lowers the power supply voltage of the integrated circuit A to the minimum necessary level and disables the operation of the integrated circuit B during a data retention operation in the integrated circuit A,
The power consumption during the data retention operation of the integrated circuit A can be reduced, and this can be very convenient when backing up the integrated circuit A using a dry battery or the like.
第１図は従来の電子回路を示す回路図、第２図は第１図
回路の一部分の具体図、第３図は本発明に係る電子回路
の一実施例を示す原理図、第４図および第５図はそれぞ
れ本発明の他の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a conventional electronic circuit, FIG. 2 is a concrete diagram of a part of the circuit in FIG. 1, FIG. 3 is a principle diagram showing an embodiment of the electronic circuit according to the present invention, and FIG. FIG. 5 is a circuit diagram showing other embodiments of the present invention.
Claims (1)
、電源系統Ａで動作する回路Ａと、出力回路部を有し、
上記とは異なる電源系統Ｂで動作する回路Ｂと、上記入
力回路部と出力回路部とを接続する信号伝達経路と、上
記回路Ａに設けられ、上記電源系統Ａと上記信号伝達経
路との間に接続されたプルアップ用素子とを備え、回路
Ａのデータ保持動作時には回路Ｂへの電源供給が遮断さ
れるとともに回路Ａの電源電圧が必要最低動作電圧まで
下げられ、電源系統Ａから上記プルアップ用素子および
上記信号伝達経路を介して出力回路部に電流が流れ出す
ような電子回路において、上記プルアップ用素子をＭＯ
ＳＦＥＴで構成し、回路Ａの通常動作時にはオン状態に
、データ保持動作時にはオフ状態に上記ＭＯＳＦＥＴを
それぞれ設定するような制御信号をそのゲートに与える
ようにしてなることを特徴とする電子回路。1 has an input circuit section configured using MOSFFT, has a circuit A that operates on power supply system A, and an output circuit section,
A circuit B that operates on a power supply system B different from the above, a signal transmission path connecting the input circuit section and the output circuit section, and a signal transmission path provided in the circuit A and between the power system A and the signal transmission path. When circuit A is in data retention operation, the power supply to circuit B is cut off, and the power supply voltage of circuit A is lowered to the required minimum operating voltage, and the pull-up element is connected to the pull-up element from power supply system A. In an electronic circuit in which a current flows into the output circuit section via the pull-up element and the signal transmission path, the pull-up element is
1. An electronic circuit comprising SFETs, wherein a control signal is applied to the gates of the MOSFETs to set the MOSFETs in an on state during normal operation of circuit A and an off state during data retention operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55156713A JPS5941205B2 (en) | 1980-11-07 | 1980-11-07 | electronic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55156713A JPS5941205B2 (en) | 1980-11-07 | 1980-11-07 | electronic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5781630A JPS5781630A (en) | 1982-05-21 |
| JPS5941205B2 true JPS5941205B2 (en) | 1984-10-05 |
Family
ID=15633704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55156713A Expired JPS5941205B2 (en) | 1980-11-07 | 1980-11-07 | electronic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5941205B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5923824U (en) * | 1982-07-31 | 1984-02-14 | 日本電気ホームエレクトロニクス株式会社 | Microcomputer interface circuit |
| JPS6214520U (en) * | 1985-07-04 | 1987-01-28 | ||
| JPH0449706Y2 (en) * | 1985-07-04 | 1992-11-24 | ||
| US5597200A (en) * | 1993-11-22 | 1997-01-28 | Amerigon, Inc. | Variable temperature seat |
| US6928559B1 (en) | 1997-06-27 | 2005-08-09 | Broadcom Corporation | Battery powered device with dynamic power and performance management |
| DE19755259A1 (en) * | 1997-12-12 | 1999-06-17 | Kostal Leopold Gmbh & Co Kg | Electronic circuit arrangement for supplying a microprocess with wake-up and action signals |
-
1980
- 1980-11-07 JP JP55156713A patent/JPS5941205B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5781630A (en) | 1982-05-21 |
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