JPS5941080A - Accessing method of common data - Google Patents

Accessing method of common data

Info

Publication number
JPS5941080A
JPS5941080A JP15084382A JP15084382A JPS5941080A JP S5941080 A JPS5941080 A JP S5941080A JP 15084382 A JP15084382 A JP 15084382A JP 15084382 A JP15084382 A JP 15084382A JP S5941080 A JPS5941080 A JP S5941080A
Authority
JP
Japan
Prior art keywords
common
processor
usable
data
shared data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15084382A
Other languages
Japanese (ja)
Inventor
Naohisa Oguchi
小口　尚久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15084382A priority Critical patent/JPS5941080A/en
Publication of JPS5941080A publication Critical patent/JPS5941080A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To prevent the deterioration of the processing performance of a processor, by making each processor execute common data processing and usable common data processing independently by a common memory accessing method using a common bus. CONSTITUTION:When processors P030-Pn3n access non-common data GD40 on a common memory CM4, a common bus 20 is used without using a common bus 21. When the processor P030 is to use a common data D0410-Dm41m, the processor P030 accesses common data usable display flags F0420-Fm42m through the bus 21, checks whether the data D0410 are usable or not, and when the data are usable, the data are made using state. If the processor P131 is in using, the data are in pin-way state. At that time, the processor P030 checks through the bus 21 with a fixed interval whether the flag F0420 is usable or not, and when recognising the usable state, read/write processing is executed. After completion of said processing, the usable state of the flag F0420 is displayed through the bus 21. When other processors access the common data, the same processing is executed.

Description

【発明の詳細な説明】 本発明は共有データアクセス方式に関し、特に各プロセ
ッサの共有データアクセス頻度が高いマルチプロセッサ
システムにおける共有データアクセス方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shared data access method, and particularly to a shared data access method in a multiprocessor system in which each processor accesses shared data frequently.

一般にマルチプロセッサシステムにおいて共通メモリ上
の共有デーｐ’ｔアクセスする際には核共有データにロ
ックフラグｒ設けて各プロセッサ間の共有データ同時ア
クセスケ禁止する。Ｔなわち既に使用中の共有データケ
アクセスＴる際には該共有データが使用可能になるまで
スピンウェイトし一定間隔で共通骨Ｈ’ｔロックして再
呼びする、従来この種の共有データアクセス方式では複
数のプロセッサが１本の共通母線を介して共通メモリと
接続されているため、スピンウェイトの頻度が高くなる
と該共通量１ｆＭ？ｆ−ロックする頻度も増加するので
共通母線使用率が増加し、各プロセッサの共通メモリア
クセス命令の実行時間が長くなりその処理能力に影響を
与えるという欠点があった。Generally, in a multiprocessor system, when accessing shared data on a common memory p't, a lock flag r is set in the core shared data to prohibit simultaneous access to the shared data between processors. In other words, when accessing shared data that is already in use, this type of shared data access is performed by spin-waiting until the shared data becomes available, locking the common bone at regular intervals, and calling it again. In this method, multiple processors are connected to a common memory via one common bus, so when the frequency of spin wait increases, the common amount 1fM? Since the f-lock frequency also increases, the common bus usage rate increases, and the execution time of the common memory access instruction of each processor becomes longer, which has a disadvantage in that it affects the processing capacity of each processor.

本発明の目的は、マルチプロセッサシステムにおいて各
プロセッサが共通メモリ上の共有データと共有データ使
用可能表示との処理ｔそれぞれ別個の共通母線ｒ使用し
た共通メモリアクセスで行うことにより上記の欠点を除
去し、プロセッサの処理能力の向上を図る共有データア
クセス方式ケ提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks in a multiprocessor system by allowing each processor to process shared data on a common memory and display shared data availability by common memory access using a separate common bus. The object of the present invention is to provide a shared data access method that improves the throughput of a processor.

本発明による共有データアクセス方式は、複数のプロセ
ッサがそれぞれ排他的に共通メモリ上の共有データケア
クセスするマルチプしセヅサシステムにおいて、前記共
Ｍデータおよび咳共有データ使用可能表示ケそれぞれ前
記プロセッサに接続する第１および第２の共通母線會備
えること荀特徴とする。A shared data access method according to the present invention is provided in a multiplexing system in which a plurality of processors each exclusively access shared data on a common memory, in which the shared data and shared data availability indicators are connected to the respective processors. It is characterized by having a first and a second common bus.

次に図面ケ参照して本発明について説明する。Next, the present invention will be explained with reference to the drawings.

図は本発明の共有データアクセス方式の一実施例ｒ示す
ブロック図である。同図において、アービタ（以下ＢＡ
）ＢＡｏＩ　Ｏ，ＢＡｌｌ　１はそれぞれ共通母線２０
．２１に介して複数のプロセッサ（以下Ｐ　）ｐ、ｓｏ
、Ｐ１３１１〜Ｐ、３ｎおよび共通メモリ（以下ＣＭ）
４と接続される。前記ＢＡ　　１０．ＢＡｌｌｌ　はそ
れぞれ前記共通母線２０．２１の各プロセッサＰ。３０
ｒ　”　１３　ＩＩ〜Ｐ　　３ｎのアクセス競合の整理
を行うための一般的アービタである。また前記０Ｍ４上
には各プロセッサＰ３０．Ｐ□３１．〜Ｐ　　３ｎが共
通に使用する共有データ（以下Ｄ）１）ｏ４１０．Ｄ□
４１１゜〜Ｄｎ１４１ｍと％該各ＩＪ。４１０．ｌ）□
４１１．〜Ｄｒｌ、４１ｍの共有データ使用可能表示フ
ラグ（以下Ｆ）Ｆ０４２０．Ｆ□４２１１〜Ｆｒｎ４２
ｍと、核り、Ｆ以外の非共有データ（以下Ｇｌ）、１４
０があり、該ＧＤ４０およびＤは前記共通母線２０を介
して前記プロセッサに読み書きされ、前記Ｆは前記共通
母線２１’に介して該プロセッサに読み出される。The figure is a block diagram showing an embodiment of the shared data access method of the present invention. In the same figure, the arbiter (hereinafter referred to as BA
) BAoI O, BAll 1 are each common bus line 20
．． A plurality of processors (hereinafter referred to as P) p, so through 21
, P1311-P, 3n and common memory (hereinafter referred to as CM)
Connected to 4. Said BA 10. BAll represents each processor P of the common bus 20 and 21, respectively. 30
This is a general arbiter for sorting out access conflicts among the processors P30. 1) o410.D□
411°~Dn141m and % each IJ. 410. l)□
411. ~Drl, 41m shared data usable display flag (hereinafter referred to as F) F0420. F□4211~Frn42
m, kernel, non-shared data other than F (hereinafter referred to as Gl), 14
0, the GDs 40 and D are read and written to the processor via the common bus 20, and the F is read to the processor via the common bus 21'.

続いて本実施例の動作について説明する。各プロセッサ
Ｐ。３０．Ｐ、３１．〜Ｐ　　３ｎが０Ｍ４上のＧＤ４
０にアクセスするときは共通器１２１ｉ−切使用せずに
共通母線２０？便用Ｔる。また。Next, the operation of this embodiment will be explained. Each processor P. 30. P, 31. ~P 3n is GD4 on 0M4
When accessing 0, the common bus 20? T for convenience. Also.

あるＰ（例えばＰ。３０　）が共有データＤ。４１Ｏ９
Ｄ１４１１．〜ＪＪｒｎ４１ｍｋ使用したいときには。A certain P (for example, P.30) is shared data D. 41O9
D1411. ~When you want to use JJrn41mk.

該Ｐ。３０は前記共通母線２１−介してＦ。４２０゜Ｆ
１４２１．〜Ｆ、Ｉ１４２ｍｋアクセスし、尚核共有デ
ータ（例えばＤ０４１０）が使用可能か否か？調べ、使
用可能ならは該り。４１（１−使用中状態とする。もし
他のＰ（例えばＰ□３１）が核り。４１０【使用中であ
れば前記Ｐ。３０　が使用可能になるまでスピンウェイ
ト状態になる。このとき該Ｐ。The P. 30 is F via the common bus bar 21-. 420°F
1421. ~F, I142mk is accessed, and is the shared nuclear data (for example, D0410) usable? Check it out, and if it's available, it's applicable. 41 (1 - In use. If another P (for example, P P.

３０は一定間隔で前記共通母線２１ｔ介してＦ。30 is F through the common bus bar 21t at regular intervals.

４２０が使用可能か否か紮チェックし、使用可能である
ことｔ認知すると前記共通母線２０を介してり。４１０
　に対する読み書きの処理を行う、この処理が終了する
と前記Ｐ。３０は前記共通母線２１勿介して前記Ｆ。４
２０　ケ使用可能表示とする。、Ｐｏ３０またはそれ以
外のプロセッサがり。420 is usable, and if it is recognized that it is usable, it is transmitted via the common bus 20. 410
When this process is completed, the above-mentioned P. 30 is the common bus line 21 and the F. 4
20 items will be marked as usable. , Po30 or other processors.

４１０以外まｔはり。４１０　　の共有データケアクセ
スするときも同様の動作ケ行う。Other than 410. A similar operation is performed when accessing the shared data of 410.

従って本実施例では共有データ使用中に遭遇したプロセ
ンサはそのスピンウェイト中、共通母線２１’に便用し
て該共有データが使用可能になるまで再呼びするので、
スピンウェイト頻度が高くなっても共有データケアクセ
スＴる共通器［２０の使用率が増加することはない。Therefore, in this embodiment, the processor encountered while using the shared data uses the common bus 21' during its spin wait and calls again until the shared data becomes usable.
Even if the spin wait frequency increases, the usage rate of the common device 20 for accessing shared data does not increase.

以上の説明により明らかなように本発明の共有データア
クセス方式によれば、マルチプロセンサシステムの各プ
ロセンサが共通メモリ上の共有データと共有データ使用
可能表示との処理ｔそれぞれ別個の共通母線２０？した
共通メモリアクセスで行うので、共有データアクセス頻
度が高く核データ用共通母線使用率が増加してもプロセ
ッサ処理能力が低下しないという大きな効果が生じる。As is clear from the above description, according to the shared data access method of the present invention, each processor in the multi-processor sensor system processes the shared data on the common memory and the shared data usability indication, respectively, on a separate common bus 20? Since the common memory access is performed using a common memory access, there is a great effect that the processor processing capacity does not decrease even if the shared data access frequency is high and the common bus utilization rate for core data increases.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の共有データアクセス方式の一実施例ｒ示す
ブロック図である。 図において、１０．１１・・・・・・アービタ、２０゜
２１・・・・・・共通母線、３０．３１．〜３ｎ・・・
・・・プロセッサ、４・・・・・・共通メモリ、４０・
・・・・・非共有データ、４１０，４１１．〜４１ｍ・
・・・・・共有データ。 ４２０．４２１．〜４２ｍ・・・・・・共有データ使用
可能表示フラグ。 代理人　弁理士　　内　原　　　晋、　　。The figure is a block diagram showing an embodiment of the shared data access method of the present invention. In the figure, 10.11...arbiter, 20°21...common bus, 30.31. ~3n...
... Processor, 4... Common memory, 40.
...Unshared data, 410,411. ~41m・
...Shared data. 420.421. ~42m...Shared data usable display flag. Agent: Susumu Uchihara, patent attorney.

Claims (1)

【特許請求の範囲】[Claims] 複数のプロセッサがそれぞれ排他的に共通メモリ上の共
有データケアクセスするマルチプロセッサシステムにお
いて、前記共有データおよび核共有データ使用可能衣示
ｒそれぞれ前記プロセッサに接続する第１および第２の
共通母線？備えることｒ特徴とする共有データアクセス
方式。In a multiprocessor system in which a plurality of processors each exclusively access shared data on a common memory, first and second common buses connected to the processors respectively indicate whether the shared data and the core shared data can be used. A shared data access method characterized by:
JP15084382A 1982-08-31 1982-08-31 Accessing method of common data Pending JPS5941080A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15084382A JPS5941080A (en) 1982-08-31 1982-08-31 Accessing method of common data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15084382A JPS5941080A (en) 1982-08-31 1982-08-31 Accessing method of common data

Publications (1)

Publication Number Publication Date
JPS5941080A true JPS5941080A (en) 1984-03-07

Family

ID=15505585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15084382A Pending JPS5941080A (en) 1982-08-31 1982-08-31 Accessing method of common data

Country Status (1)

Country Link
JP (1) JPS5941080A (en)

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