JPS594042U - Watchdog timer circuit - Google Patents

Watchdog timer circuit

Info

Publication number
JPS594042U
JPS594042U JP6779583U JP6779583U JPS594042U JP S594042 U JPS594042 U JP S594042U JP 6779583 U JP6779583 U JP 6779583U JP 6779583 U JP6779583 U JP 6779583U JP S594042 U JPS594042 U JP S594042U
Authority
JP
Japan
Prior art keywords
circuit
electronic circuit
oscillator
pulse
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6779583U
Other languages
Japanese (ja)
Inventor
功雄 一色
慎一郎 高橋
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Priority to JP6779583U priority Critical patent/JPS594042U/en
Publication of JPS594042U publication Critical patent/JPS594042U/en
Pending legal-status Critical Current

Links

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  • Electronic Switches (AREA)
  • Debugging And Monitoring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案の一実施例を示す回路図である。 図面中、■は発振器、■はリセット回路、1はマイクロ
プロセッサ、2はシュミットトリガゲート、3はインバ
ータ、4はRC積分回路、5は2人力ナンドゲート、6
は微分回路、8はトランジスタ、R1は帰環抵抗、C工
はコンデンサ、Rはリセット端子、PRはプログラムに
より発生したパルスの出力端子である。
The figure is a circuit diagram showing an embodiment of the present invention. In the drawing, ■ is an oscillator, ■ is a reset circuit, 1 is a microprocessor, 2 is a Schmitt trigger gate, 3 is an inverter, 4 is an RC integration circuit, 5 is a two-man NAND gate, 6
8 is a differential circuit, 8 is a transistor, R1 is a return resistor, C is a capacitor, R is a reset terminal, and PR is an output terminal for pulses generated by the program.

Claims (1)

【実用新案登録請求の範囲】 プログラムによって動作する電子回路に接続され、当該
プログラムによりこの電子回路から予め定めた時間内の
間隔で発信されるパルスを入力とし、このパルスが前記
予め定めた時間内に発信されないことを検出して前記電
子回路の動作を初期状態にリセットさせる信号を該電子
回路へ送出するウオッチドックタイマ回路において、と
もに前記電子回路のパルスを入力するRC積分回路及び
インバータ並びにこれらの出力を入力する2人力ナンド
ゲートで構成した微分回路と、シュミットトリガゲート
、その帰環抵抗及びコンデンサで構成し前記電子回路へ
のリセット用信号を発振する発振器と、 トランジスタ及び抵抗で構成し前記微分回路の出力信号
により駆動されて前記発振器のコンデンサを放電させる
リセット回路と、 からなることを特徴とするウォッチドッグタイマ回路。
[Claims for Utility Model Registration] The input is a pulse that is connected to an electronic circuit that operates according to a program and is emitted from this electronic circuit at predetermined time intervals according to the program, and that this pulse is transmitted within the predetermined time interval. In a watchdog timer circuit that detects that the electronic circuit is not being transmitted and sends a signal to the electronic circuit to reset the operation of the electronic circuit to the initial state, an RC integrating circuit and an inverter that both input the pulse of the electronic circuit, and an inverter thereof. A differentiating circuit made up of a two-man NAND gate inputting an output, an oscillator made up of a Schmitt trigger gate, its return resistor, and a capacitor and oscillating a reset signal to the electronic circuit, and a differentiating circuit made up of a transistor and a resistor. a reset circuit that is driven by an output signal of the oscillator to discharge a capacitor of the oscillator;
JP6779583U 1983-05-09 1983-05-09 Watchdog timer circuit Pending JPS594042U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6779583U JPS594042U (en) 1983-05-09 1983-05-09 Watchdog timer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6779583U JPS594042U (en) 1983-05-09 1983-05-09 Watchdog timer circuit

Publications (1)

Publication Number Publication Date
JPS594042U true JPS594042U (en) 1984-01-11

Family

ID=30197984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6779583U Pending JPS594042U (en) 1983-05-09 1983-05-09 Watchdog timer circuit

Country Status (1)

Country Link
JP (1) JPS594042U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0468422A (en) * 1990-07-09 1992-03-04 Matsushita Electron Corp Microcomputer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5557956A (en) * 1978-10-25 1980-04-30 Nissan Motor Co Ltd Malfunction prevention unit of microcomputer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5557956A (en) * 1978-10-25 1980-04-30 Nissan Motor Co Ltd Malfunction prevention unit of microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0468422A (en) * 1990-07-09 1992-03-04 Matsushita Electron Corp Microcomputer

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