JPS5939145A - Data discriminating circuit - Google Patents

Data discriminating circuit

Info

Publication number
JPS5939145A
JPS5939145A JP14931082A JP14931082A JPS5939145A JP S5939145 A JPS5939145 A JP S5939145A JP 14931082 A JP14931082 A JP 14931082A JP 14931082 A JP14931082 A JP 14931082A JP S5939145 A JPS5939145 A JP S5939145A
Authority
JP
Japan
Prior art keywords
circuit
input signal
input
signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14931082A
Other languages
Japanese (ja)
Inventor
Tsutomu Noda
勉 野田
Hiromichi Tanaka
田中 弘道
Hiroyuki Kimura
寛之 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14931082A priority Critical patent/JPS5939145A/en
Publication of JPS5939145A publication Critical patent/JPS5939145A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/20Arrangements for detecting or preventing errors in the information received using signal quality detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To obtain a data discriminating circuit with less malfunction by controlling a switching circuit provided at an output of a comparator by an output signal of an input signal detecting circuit discrminating the presence of an input digital signal. CONSTITUTION:An input signal detecting circuit 4 detects the presence of the digital input signal of a comparator 1, and when the input signal exists, a detecting signal of the circuit 4 closes a switch 5, applies a data to a digital signal processing circuit 3, and when no input signal exists, the switch 5 is opened so as not to apply data to the circuit 3. Thus, when no input signal exists, since the abnormal data due to input noise is not applied to the circuit 3, the malfunction of the system using the signal in the data as a control signal is prevented.

Description

【発明の詳細な説明】 本発明はディジタル信号伝送におけるアナログ入力信号
を波形整形してディジタル信号処理回路に出力するデー
タ識別回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data identification circuit that shapes the waveform of an analog input signal in digital signal transmission and outputs the waveform to a digital signal processing circuit.

従来のデータ識別回路は特開昭55−150644号公
報あるいは55−150645号公報の「データ抜きと
9回路」に示されているように、2値の入力信号の中間
点でレベル比較することでデータを識別していた。
Conventional data identification circuits compare levels at the midpoint of binary input signals, as shown in ``Data extraction and 9 circuits'' in Japanese Patent Laid-Open No. 55-150644 or 55-150645. The data was identified.

ディジタル・オーディオ・ディスク・プレーヤなどのよ
うにデータ内の信号をディスク・モータ・ザーボなどの
制御信号とするシステムにおいて、このようなデータ識
別回路を用いると入力信号のない場合にはデータ識別回
路出力は入力雑音によりあたかもデータかの」、うなで
たらめな信号がディジタル信号処理回路に加えられ誤動
作をまねく。
In a system such as a digital audio disc player where the signal in the data is used as a control signal for the disc motor, servo, etc., if such a data identification circuit is used, the data identification circuit outputs when there is no input signal. Due to input noise, a random signal that appears to be data is applied to the digital signal processing circuit, leading to malfunction.

本発明の目的は従来技術の欠点をなくし、データ内の信
号を開側1信号とするシステムにおいて誤動作の少ない
データ識別回路を提供する。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and provide a data identification circuit with fewer malfunctions in a system in which a signal in data is an open signal.

このため本発明は入力信号がない時に出力を出さないデ
ータ識別回路にすることにある・以下、本発明の一実施
例を第1図により説明する。1は比較器、2は入力端子
、2はディジタル信号処理回路、4は入力信号検出回路
、5はスイッチである。入力信号検出回路4で比較器1
の入力信号の有無を検出し、入力信号の有る場合にはス
イッチ5を閉じてデータをディジタル信号処理回路3に
加え、入力信号の無い場合にはスイッチ5を開いてデー
タをディジタル信号処理回路3に加えないようにする。
Therefore, the present invention is to provide a data identification circuit which does not output an output when there is no input signal.Hereinafter, one embodiment of the present invention will be described with reference to FIG. 1 is a comparator, 2 is an input terminal, 2 is a digital signal processing circuit, 4 is an input signal detection circuit, and 5 is a switch. Comparator 1 with input signal detection circuit 4
If there is an input signal, the switch 5 is closed and the data is added to the digital signal processing circuit 3. If there is no input signal, the switch 5 is opened and the data is sent to the digital signal processing circuit 3. Do not add it to

本実施例によれば入力信号の無い場合には入力雑音によ
るでたらめなデータがディジタル信号処理回路3に加え
られないため、データ内の信号を制御信号とするシステ
ムにおいても誤動作をしない。
According to this embodiment, when there is no input signal, random data due to input noise is not applied to the digital signal processing circuit 3, so that malfunctions will not occur even in a system in which a signal within the data is used as a control signal.

第1図のスイッチ5を具体的回路で記述した本発明の他
の実施例を第2図に示す。
Another embodiment of the present invention is shown in FIG. 2, in which the switch 5 of FIG. 1 is described as a concrete circuit.

第1図と同一符号のものは同一機能を示す。Components with the same symbols as in FIG. 1 indicate the same functions.

6は出力型式がオープンコレクタの比較器、7は負荷抵
抗、8は電源、9はトランジスタである。入力信号の有
る場合には入力信号検出回路4の出力をトランジスタ9
がオフするようにし、比較器6の出力はディジタル信号
処理回路3に加えられる。入力信号が無い場合には入力
信号検出回路4の出力でトランジスタ9がオンし、比較
器6の状態にかかわらずディジクル信号処理回路60入
力はローレベルに固定される。
6 is a comparator whose output type is an open collector, 7 is a load resistor, 8 is a power supply, and 9 is a transistor. When there is an input signal, the output of the input signal detection circuit 4 is connected to the transistor 9.
is turned off, and the output of the comparator 6 is applied to the digital signal processing circuit 3. When there is no input signal, the transistor 9 is turned on by the output of the input signal detection circuit 4, and the input of the digital signal processing circuit 60 is fixed at a low level regardless of the state of the comparator 6.

その結果第1図の場合と同等の効牙−を得る◇本発明の
さらに他の実施例を第3図に示す。
As a result, the same effect as in the case of FIG. 1 is obtained. Still another embodiment of the present invention is shown in FIG.

本実施例fは入力48号検出回路4の出力で比較器1の
比較レベルを制御するもので、人力信号が有る壕合には
比較レベルは本来の値であシデータ識別した出力はディ
ジタル信号処理回路に加えられる。
In this embodiment f, the comparison level of the comparator 1 is controlled by the output of the input No. 48 detection circuit 4, and when there is a human input signal, the comparison level is the original value, and the output after data identification is processed by digital signal processing. added to the circuit.

入力信号が無い場合には比較レベルを本来の値よυ高い
あるいは低いレベルに変化させて比較器1の出力を固定
する、 その結果第1図あるいは第2因と同等の効果を得る。
When there is no input signal, the comparison level is changed to a level υ higher or lower than the original value, and the output of comparator 1 is fixed. As a result, an effect similar to that of FIG. 1 or the second factor is obtained.

本実施例では入力信号検出回路4の出力で比較器1の比
較レベルを変化させて出力を固定したが、入力信号検出
回路4の出力で入力信号にオフセットを加えることでも
、同等の効果を得ることは周知である。
In this embodiment, the output of the comparator 1 is fixed by changing the comparison level of the comparator 1 using the output of the input signal detection circuit 4, but the same effect can be obtained by adding an offset to the input signal using the output of the input signal detection circuit 4. This is well known.

以上入力信号の有無を検出する入力信号検出回路4は検
波と比較で容易に栴成できるか、マイコンなどのシステ
ムを制御する回路が信号の無い状態の時にはデータ識別
回路の出力を切るように、出力して、入力信号検出回路
40代りをすることも可能であり、同等の効果を得る。
The input signal detection circuit 4 that detects the presence or absence of an input signal can be easily constructed by detection and comparison, or is it possible to create a circuit that controls a system such as a microcomputer by cutting off the output of the data identification circuit when there is no signal? It is also possible to output it and use it as the input signal detection circuit 40, and obtain the same effect.

このように本発明によれば入力信号のない時にでたらめ
なデータをディジタル信号処理回路に加えないためデー
タ内の信号を制御4rj号とするシステムでも誤動作を
まねかない。
As described above, according to the present invention, since random data is not added to the digital signal processing circuit when there is no input signal, malfunctions will not occur even in a system in which the signal in the data is the control number 4rj.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例図を示す1v、1、第2゜図
は本発明の他の実施例を示す図、第6図は本発明のさら
に他の実施flJを示す図である。 1.6・・・・・・比較器 6・・・・・・ディジタル信号処理回路4・・・・・・
入力信号検出回路 5・・・・・・スイッチ 7・・・・・・負荷抵抗 9・・・・・・トランジスタ 代理人弁理士 薄 83 利 才 1 図 才 2 図
FIG. 1 is a diagram showing one embodiment of the present invention; FIGS. 1v, 1, and 2 are diagrams showing another embodiment of the present invention; FIG. . 1.6...Comparator 6...Digital signal processing circuit 4...
Input signal detection circuit 5...Switch 7...Load resistor 9...Transistor agent Patent attorney Susuki 83 Risai 1 Diagram 2 Diagram

Claims (1)

【特許請求の範囲】 1、 入力ディジタル信号を基準レベルと比較する比較
器で構成され、前記該比較器出力信号をディジタル信号
処理回路に供給するデータ識別回路において、前記比較
器の人力または出力に切換回路を接続し、前記切換回路
を入力ディジタル信号の有無を判別する入力信号検出回
路で駆動するようになり、入力ディジタル信号がないと
きに前記ディジタル信号処理回路入力をオフとすること
を特徴とするデータ識別回路。 2、 前記切換回路が前記比較器出力をノ・イレベルi
 L < ldコロ−ベルのいずれか一方に固定する回
路である特許請求の範囲第1項記載のデータ識別回路。
[Claims] 1. A data identification circuit comprising a comparator for comparing an input digital signal with a reference level and supplying the output signal of the comparator to a digital signal processing circuit, wherein A switching circuit is connected, the switching circuit is driven by an input signal detection circuit that determines the presence or absence of an input digital signal, and the input to the digital signal processing circuit is turned off when there is no input digital signal. data identification circuit. 2. The switching circuit changes the comparator output to a level i.
2. The data identification circuit according to claim 1, which is a circuit that fixes L<ld to either one of the corrobels.
JP14931082A 1982-08-30 1982-08-30 Data discriminating circuit Pending JPS5939145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14931082A JPS5939145A (en) 1982-08-30 1982-08-30 Data discriminating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14931082A JPS5939145A (en) 1982-08-30 1982-08-30 Data discriminating circuit

Publications (1)

Publication Number Publication Date
JPS5939145A true JPS5939145A (en) 1984-03-03

Family

ID=15472327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14931082A Pending JPS5939145A (en) 1982-08-30 1982-08-30 Data discriminating circuit

Country Status (1)

Country Link
JP (1) JPS5939145A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6236477U (en) * 1985-08-21 1987-03-04
JPS6283217U (en) * 1985-11-15 1987-05-27

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS555586A (en) * 1978-06-29 1980-01-16 Mitsubishi Electric Corp Demodulation circuit for digital signal
JPS55118255A (en) * 1979-03-06 1980-09-11 Nec Corp Output control circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS555586A (en) * 1978-06-29 1980-01-16 Mitsubishi Electric Corp Demodulation circuit for digital signal
JPS55118255A (en) * 1979-03-06 1980-09-11 Nec Corp Output control circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6236477U (en) * 1985-08-21 1987-03-04
JPS6283217U (en) * 1985-11-15 1987-05-27

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