JPS5936394A - Information processor - Google Patents

Abstract

PURPOSE:To avoid a fixed fault of a control storage with a simple constitution, by providing an address line replacing circuit for mutual replacement of address lines. CONSTITUTION:A write address is supplied from a write control circuit 4 via a switch circuit 7 and an address replacing circuit 6. The read information which is read out by the circuit 4 and given from an external storage 17 is written to a control storage 1 for each bit. This bit information is read simultaneously out of the storage 1 and then compared with the write bit information through a comparator 3 after passing through a control storage register 2. If no coincidence is obtained from this comparison, a fault is discriminated for a memory cell corresponding to the storage 1. Then the circuit 6 is controlled by the circuit 4, an address line replacement mode register 5, etc. The address lines of the storage 1 are replaced with each other to perform the similar writing and the discrimination of a fault. In such a way, a fixed fault can be avoided for a control storage with a simple constitution excluding an error check code generating part, an error detecting/correcting part, etc.

Description

【発明の詳細な説明】 （発明の属する技術〕 本発明は情報処理装置、特に制御記憶の障害回避手段を
もつ情報処理装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Technology to which the invention pertains) The present invention relates to an information processing apparatus, and particularly to an information processing apparatus having control memory failure avoidance means.

〔従来技術〕[Prior art]

従来、−芽き換え可能な制御記憶分有する情報処理装置
において、制御記憶障害時に書込後１祈出を行い、書込
データと読出データとの比較により１・！′ｒ。Conventionally, in an information processing device having a control memory that can be replaced, when a control memory failure occurs, one readout is performed after writing, and the written data is compared with the read data to determine 1.! 'r.

出データの凧りが検出されると、制御記憶障害として装
置が使用出来なかった。If a kite in the output data was detected, the device could not be used due to a control memory failure.

従来にあっては、これを解決するために制御記憶に誤り
検出訂正回路を付加することが行なわれているが、制御
記憶障害の増加及び複雑な誤り検出訂正回路を設けるこ
とにより、設計敏の増大。Conventionally, an error detection and correction circuit has been added to the control memory in order to solve this problem. Increase.

金物量の増加、製作費の高騰等の欠点がある。さらに誤
り検出訂正回路に於ける遅延時間の為にマシンサイクル
が伸延し情報処理装置の性能低下を招来する欠点がある
。There are disadvantages such as an increase in the amount of metal materials and a rise in production costs. Furthermore, there is a drawback that the machine cycle is extended due to the delay time in the error detection and correction circuit, resulting in a decrease in the performance of the information processing device.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、制御記憶書込時に検出されるｆｉｉ制
御記憶の固定障害を１鍼く僅かな回路の追加で回避ＤＪ
能とする情報処理装置全提供することにある。An object of the present invention is to provide a DJ system that avoids fixation failures of fii control memory detected when writing control memory by adding a small number of circuits.
The aim is to provide all information processing equipment that can be used.

〔発明の構成〕[Structure of the invention]

本発明によると書き換え可能な制御記憶と、通′帛モー
ドと１つまたは複数の制御記憶アドレス線入替モードか
ら１）り択されたモードを保持するモードレジスタと、
該モードレジスタに設定されたモードに従って少なくと
も２本の制御記憶アドレス線全相互に入・、ヤえる手段
と、制？ｉ′ｌｉｌ紀憶Ｉ：込後坑出しを行う手段と、
前記誠出値と宵込値との比較検査を行う手段と　、；ｉ
、記倹査において誤りを検出した時に５１つの制御記憶
アドレス線入替モードをびギ＾出値と斗込１１■との比
較検査をイ１い、該検査により誤り？検出すると、モー
ドレジスタに１つのアドレス線入替モード金設定して再
度ｉｔｉ制御記憶書込全最初から行うこと全特徴とする
情報夕ノ（理装置が得られる。According to the present invention, a rewritable control memory and a mode register holding a mode selected from 1) a regular mode and one or more control memory address line swap modes;
means for inputting and switching all at least two control memory address lines to each other according to the mode set in the mode register; i'lil Memories I: Means for digging out the mine after entering,
means for carrying out a comparative test between the evening value and the evening value;
, When an error is detected in the memory check, the 51 control memory address line exchange mode is activated and a comparison test is performed between the output value and the input value 11■. When detected, one address line replacement mode is set in the mode register and the entire control memory write is performed from the beginning again.

〔実施例の説Ｉｌｌり 次に本発明に一ういて図面全参ＩＩ＠　して：Ｊ’　ｉ
？Ｉｌｌに涜、明する。[Description of the embodiments] Next, referring to the present invention, please refer to all the drawings.
? I'll confess to you.

第１図は不発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the invention.

制御記憶１は書込ｉｉ制御回路４Ｑてより書込データ１
０と、１４＝込１ぎ号とが与えられる。制御記憶１のｒ
？ｉ’Ｍ出データは制御記憶レジスタ２に取込まれ、そ
の出力８は比較回路３によって書込データ１０と比較さ
れる。比較結果は信号線９により書込側（１］ｊ回路４
に伝えられる。Control memory 1 receives write data 1 from write ii control circuit 4Q.
0 and 14=inclusive number 1 are given. control memory 1 r
? The i'M output data is taken into the control storage register 2, and its output 8 is compared with the write data 10 by the comparison circuit 3. The comparison result is sent to the write side (1] j circuit 4 via signal line 9.
can be conveyed to.

アドレス線入・青モードレジスタ５は湯送制御回路４か
ら１６分通じてモードがセットされる。モードレジスタ
５の出力１５はアドレス線入替回路６を制御し、処理饗
買動作時の制御記憶流量アドレス１２とｌ物理アドレス
１４、または・１″込時に与えられる斗込アドレス１１
と物理アドレス１４との対応（蓼１係の変更全アドレス
線の入替によって実現する。切替回路７は処理装＃動作
時の読出アドレス１２と初期設定時の制御記憶訃込／Ｗ
ｚ出アドレス１１との切替全行う。The mode of the address line-on/blue mode register 5 is set by the hot water transfer control circuit 4 for 16 minutes. The output 15 of the mode register 5 controls the address line switching circuit 6, and the control storage flow rate address 12 and l physical address 14 during processing operation, or the input address 11 given when 1'' is included.
and the physical address 14 (this is realized by replacing all the address lines).The switching circuit 7 corresponds to the read address 12 at the time of processing unit # operation and the control memory address /W at the time of initial setting.
Complete switching with z output address 11 is performed.

次にその動作を説、明する。Next, its operation will be explained and explained.

最初に初期設定の為に制御記憶湯送が起動されると、制
御、紀憶聾込制伺１回路４はアドレス陀４入替モードレ
ジスタ５に初期値と［７て通常モードを設定すると共に
、憚込制′ｉｉ’ｌｔ１回路４の内部に１１有する、１
込アドレス計斂器に初期値を設定する。When the control memory transfer is started for the first time for initial setting, the control memory transfer control 1 circuit 4 sets the initial value and the normal mode in the address 4 exchange mode register 5 and sets the normal mode. There are 11 inside circuit 4, 1
Set the initial value to the included address meter.

次に制御記憶への書込データを晒納している外部記憶１
７から制御配憶非込データｋｉ’ｆｒみ出して書込デー
タ線１０金通じてｔｉ制御’、＋４．゛臣１へ書込金イ
１う。ｆｌｉｌＪ御記憶１の１語の攬込毎に湯送制御１
ｑ１路４はＴ−込アドｌ／ス１１及び湯送データ１０を
更新する。書込後１元出しは制御記憶の１語膚き込みＦ
ｆｖｃ行ってもよいし、全語、りき込み全行ってから１
ｈハずつ全語数にわたって１１児み出しでもよいが、後
者の、用台、比較回前のために再度外部記憶１７の読出
が必要である。Next, external memory 1 that stores the data written to the control memory
Control storage non-input data ki'fr is extracted from 7 and is passed through the write data line 10 to ti control', +4.゛Write 1 payment to minister 1. Bottle feeding control 1 every time one word of flilJ memory 1 is imported.
The q1 path 4 updates the T-included address 11 and the water transfer data 10. One word output after writing is one word in control memory F
You can go to fvc, or you can go to all the words and rekikomi and then go to 1.
Although it is possible to retrieve 11 words for each word of h, it is necessary to read out the external memory 17 again for the latter use and before the comparison.

イ込後読出余行って硯み出されたデータと計込データと
全比較器３によって比較し、不一致が検出されると、書
込制御回路４はアドレス線入詐モードレジスタ５の初期
値である賄濱モード全１つのアドレス線入替モードに変
更し、これ以外の一１’Ｊ込制御を初期状態にもどして
再び制御記憶書込を最初のアドレスから行う。The data read out after writing and the calculated data are compared by the full comparator 3, and if a mismatch is detected, the write control circuit 4 sets the initial value of the address line input fraud mode register 5. A certain supply mode is changed to an all-one address line replacement mode, the other 1'J control is returned to the initial state, and control memory writing is performed again from the first address.

この２回目の斗込において前記更ｕＪ＋され、たアドレ
ス線入替モードにおいては、アドレス線入替回路６が入
力アドレス線１３のうち少なくとも２木のアドレス線ヲ
相互に人替えて出力アドレス線１４とする為、前回書込
後絖出時に誤りとｋつだ記憶ピットセルは前回と（ｌ−
ｊ異なるアドレスに割当てられる。In the address line switching mode in which the address line switching circuit 6 is in the address line switching mode in which the address lines are changed in the second input, the address line switching circuit 6 mutually switches at least two address lines among the input address lines 13 and uses them as the output address lines 14. Therefore, after the previous write, there was an error during printing and the memory pit cells were different from the previous time (l-
j are assigned to different addresses.

この沼「１〜く割当てられたアドレスにおける該ビット
の斗込データ１直か前記記憶ビットセルの固定故障値と
一致すれば、第２回目の制御記憶り込において、書込後
胱出倹査が合格とな、り障害が回避されたこととなり、
この時の制御記憶アドレス線入替モードを保存して処理
装置前の動作へ移る。If the input data of the bit in the address assigned from 1 to 1 matches the fixed failure value of the storage bit cell, the post-write output check will be performed in the second control memory write. If the test is passed, the obstacle has been avoided, and
The control memory address line exchange mode at this time is saved and the process moves on to the operation before the processing device.

第２回目の制御記憶丼込においても屏込後１訳出し・ｆ
・朽査が不合格であれば、さらに１ｍのアドレス線入替
モードに変更して制御記憶湯送ケやり直すことになる。In the second control memory bowl, there is also one translation after the folding.
- If the inspection fails, the mode will be changed to 1m address line replacement mode and the control memorized hot water transfer will be performed again.

制御ｄ１；憶アドレスがＯ〜２°−１！であるとすれば
最小アドレスＯと最大アドレス２”−１’ｅ除いた残り
全てのアドレスに対してｎ回までのアドレス線入済モー
ド変更が可能であり、制御記憶１内データの２進論理値
分布を０と１が均等であると仮定すると、ｎ通りのアド
レス線入行で１−１／２゜の確率で１つのビットセルの
障害回避が可能となる。１ビット誤りがＩｎ岡のアドレ
スＶこ存在する場合は同様に（１，−１，／２　”　）
”の確率で全ての誤りが回避される。Control d1; Memory address is O~2°-1! If so, it is possible to change the address line entry mode up to n times for all remaining addresses except for the minimum address O and maximum address 2"-1'e, and the binary logic of the data in control memory 1 Assuming that the value distribution is equal for 0 and 1, it is possible to avoid a fault in one bit cell with a probability of 1-1/2° by entering the address line in n ways. If this exists, similarly (1, -1, /2 ”)
” all errors are avoided with probability.

さらに本角明において６−１１．　１つのアドレスＶこ
複数ビットの誤りが存在する場合においても、′吻理ア
ドレスを異なる論理アドレスに対１．シをＶ更すること
により障害回避が町１化であり、通常使用される１ビツ
トエラー訂ｉＥ２ビツトエラー検出のＥ（づＣよりも優
れた待機となっている。Furthermore, in Akira Honkaku 6-11. Even if there are multiple bit errors in one address, it is possible to pair a logical address to a different logical address. By changing the number of bits to V, failure avoidance is reduced to one, and the standby is superior to the commonly used 1-bit error correction, iE, and 2-bit error detection, E(dzc).

第２図は３木のアドレス線を相互に入替えて６通シのア
ドレス入替モード全有する実施例におけるアドレス線入
替モードレジスタ及びアドレス入替回路の詳細？示す。FIG. 2 shows details of an address line switching mode register and an address switching circuit in an embodiment in which three address lines are mutually switched to provide all six address switching modes. show.

ＮＯからＮ１棟での人力アドレス線群１３のうちＮｏ、
Ａｔ、Ａ２の３本カニ相互に：入Ｗｔ　ラレテＡＯ’　
、　Ａｔ’　、　Ａ２’　トナ５　ｆｉｌアドレス線群
１４の一部となる。６は３ピツトの６−ＷＡＹセレクタ
で、アドレス線入替モードレジスタ５の出力１５により
選択位置が足まる。！＜１は５−ＷＡＹセレクタ６にお
ける１攬択１占号゛と入Ｉｔｓ　’７７の対応を示す。No. of the human address line group 13 in the N1 building from NO.
At, A2 three crabs mutually: Enter Wt Larete AO'
, At', A2' Toner 5 fil becomes part of the address line group 14. 6 is a 3-pit 6-WAY selector, and the selected position is determined by the output 15 of the address line exchange mode register 5. ! <1 indicates the correspondence between 1 selection 1 digit in the 5-WAY selector 6 and input Its '77.

表　　１ 〔発明の効果〕 本発明は以−上説明し／こように、制御へ己憶アドレス
線上にアドレスイリを相互に入替えるアドレス線入替回
路を挿入することによって、制御記憶容置を１太させる
ことなく、才たＥ　ＣＣのような複雑か誤り検出訂正回
路を設けることな（、ｆｊ制御記憶の固？障害笈同避し
、安価で寅１−性（′）商い情報列１１１Ｊｊ装鮪全提
供する効果がある。Table 1 [Effects of the Invention] As described above, the present invention can reduce the number of control storage units to one by inserting an address line switching circuit for mutually switching address lines on the control storage address lines. It is possible to avoid the problems of fj control memory without having to install a complicated error detection and correction circuit such as an efficient ECC, and to implement an inexpensive and efficient (') commercial information string 111Jj system. It is effective to provide whole tuna.

４、図面”　’ｌ’ｌｔｌ　％−す説１ｇｊ第１図は本
発明の一実施例を示すフロック図、第２１ン１は第１図
（り：示り、　ｙ’＋−アドレス１１人若回路部分の１
１１１路図である。4.Drawings"'l'ltl %-1gj Figure 1 is a block diagram showing an embodiment of the present invention, 21-1 is a block diagram showing an embodiment of the present invention, y'+-Address 11 circuit part 1
111 route map.

Claims (1)

【特許請求の範囲】[Claims] 逓き換え可能な制御記憶と、通常モードと１つモードレ
ジスタに設定されたモードに従って少なくとも２木の制
御記憶アドレス線全相互に入替える手段と、制御Ｍｉ’
、ｔ、を書込後読出し全行う手段と、前記仇出値と書込
値との比較検査を行う手段と、ｒ７ｉＪ記検査において
１呉りを検出した時に、１つの制御記憶アドレス１゛ノ
人替モードを前記モードレジスとの比較検査を行い、該
検査により誤り全検出すると、モードレジスタに１つの
アドレス紳入替モードを設定して再度制御記憶書込を最
初から行うことを特徴とする情報処理装置。a switchable control memory; means for switching all of at least two control memory address lines according to a normal mode and a mode set in a mode register; and a control Mi'.
, t, after writing, means for performing a comparison test between the output value and the written value, and a means for performing a comparison test between the output value and the written value, and a means for performing a comparison test between the output value and the written value; Information characterized in that the replacement mode is compared with the mode register, and if all errors are detected by the test, one address replacement mode is set in the mode register and control memory writing is performed again from the beginning. Processing equipment.