JPS5935452A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the variation of reference potential by forming a reference potential wiring at ground potential in two layer wirings, connecting a first wiring between them to a diffusion layer, using a second wiring as a wiring coating the whole surface of a chip-surface insulation and electrically connecting at least one point or more of these two wirings. CONSTITUTION:A source region 2 and a drain region 3 are diffused and formed to the surface layer section of a semiconductor substrate 1, the peripheries of these regions are surrounded by a field oxide film 6, and a gate electrode 5 buried in a gate insulating film 4 is set up to the surface of the substrate 1 between the regions 2 and 3. The whole surface is coated with the laminated film of insulating films 7 and 8, an opening is bored to these films, and a drain electrode 9 reaching the region 3 is formed surrounded by the film 7. A source electrode 10 reaching the region 2 is also set up, but the films 7 and 8 are penetrated by the electrode 10 at that time, and the whole surface containing an end section exposed is coated with a second wiring layer 11. Accordingly, a margin for input voltage is widened, and the generation of the malfunction of an internal circuit is avoided.

Description

【発明の詳細な説明】 本発明は半導体集積回路装置にかかシ、特に基準電位（
ＧＮＤ）の変動を防止する構成を有する半導体集積回路
装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, particularly a reference potential (
The present invention relates to a semiconductor integrated circuit device having a configuration that prevents fluctuations in ground (GND).

第１図に従来の金属−酸化膜半導体装置（ＭＯＳトラン
ジスタ）の要部模式平面図を示し、第２図に第１図の一
点鎖線部の断面図を示し几。両図において１は半導体基
板、２および３は半導体基板に不純物を拡散して形成し
几ソースおよびドレイン領域である。また４はゲート酸
化膜でその上にはゲート電極５が形成されている。６．
　７．　８は基板上に形成された絶縁膜である。９はド
レイ面１２で接し形成されたソース電極である。このよ
うなＭＯＳ）ランジスタにおいては基準電位（ＧＮＤ）
はソース端子で拡散層２と金属配線１０でコンタクトが
取られた一層のみの金属配線で構成されてい几。従って
インピーダンスが高くなシ交流電流が大きな半導体集積
回路では交流電流の大きさに比例して基準電位が変動す
るため、入力電圧のマージンを狭くしたシ、トランジス
タのインバータ回路レシオを変動させ、内部回路の誤動
、作？起し易くさせるという問題点があった。FIG. 1 shows a schematic plan view of a main part of a conventional metal-oxide film semiconductor device (MOS transistor), and FIG. 2 shows a cross-sectional view taken along a dashed-dotted line in FIG. 1. In both figures, 1 is a semiconductor substrate, and 2 and 3 are source and drain regions formed by diffusing impurities into the semiconductor substrate. Further, 4 is a gate oxide film, and a gate electrode 5 is formed on the gate oxide film. 6.
7. 8 is an insulating film formed on the substrate. Reference numeral 9 denotes a source electrode formed in contact with the drain surface 12. In such a transistor (MOS), the reference potential (GND)
The source terminal is made up of only one layer of metal wiring, which is in contact with the diffusion layer 2 and the metal wiring 10. Therefore, in semiconductor integrated circuits with high impedance and large alternating current, the reference potential fluctuates in proportion to the magnitude of the alternating current. Malfunction, operation? There was a problem in that it made it easier to wake up.

本発明は以上の問題に対処してなされ几もので、その目
的は基準電位の変動を極力少なくすることによＪ入力電
圧のマージンを広くシ、トランジスタのインバータ回路
レシオの変動を防止して内部回路の誤動作金なくした半
導体集積回路装置を提供するにある、 すなわち本発明の要旨は、基準電位（ＧＮＤ）配置ｔ−
金属配線による二重配線とし、前記配線の第１の配線は
拡散層とコンタクトラとシ第２の配線はチップの表面絶
縁膜を全面的に覆う金属配線とし、第１の金属配線と第
２の金属配線は少なくとも一点以上で電気的に接続され
ていることｔ−特徴とする半導体集積回路装置にある。The present invention has been devised to solve the above problems, and its purpose is to widen the margin of the J input voltage by minimizing fluctuations in the reference potential, and to prevent fluctuations in the inverter circuit ratio of the transistors. The gist of the present invention is to provide a semiconductor integrated circuit device that eliminates circuit malfunction costs.
The first wiring is a diffusion layer and a contact layer, and the second wiring is a metal wiring that completely covers the surface insulating film of the chip, and the first metal wiring and the second wiring are double wiring. The semiconductor integrated circuit device is characterized in that the metal wirings are electrically connected at at least one point.

以下本発明の実施例につき図面を参照して詳細に説明す
る。第３図は本発明の一実施例による半導体集積回路装
置の断面図を示す。第３図において、ＷＪ２図と同じ部
分については第２図と同一番号を付しであるので大部分
の説明を省略する。トランジスタのドレイン端子は拡散
層３と金属配線９でコンタクトがとられている。それに
対し基準電位であるソース端子は拡散層２と第１の金属
配線１０および第２金属配Ｒ１１でコンタクトがとられ
金属配線１０および金属配線１１は接点部１４で接続さ
れている。またゲート端子５は低抵抗配線で構成されて
いる。なお第２の金属配線はチップ表面絶縁物８等を覆
って形成されている。Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 3 shows a cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention. In FIG. 3, the same parts as in FIG. WJ2 are given the same numbers as in FIG. 2, so the explanation of most of them will be omitted. The drain terminal of the transistor is in contact with the diffusion layer 3 and the metal wiring 9. On the other hand, the source terminal having a reference potential is in contact with the diffusion layer 2 through the first metal wiring 10 and the second metal wiring R11, and the metal wiring 10 and the metal wiring 11 are connected through the contact portion 14. Further, the gate terminal 5 is formed of a low resistance wiring. Note that the second metal wiring is formed to cover the chip surface insulator 8 and the like.

以上のような構成によれば基準電位接続息から拡散層に
至る直流抵抗はすくなくなシ交流インピーダンスも小さ
くなる、特に絶縁膜上には全面的に第２の金属配線がさ
れているので交流インピーダンスの低下はよシ大きくな
る。According to the above configuration, the DC resistance from the reference potential connection to the diffusion layer is reduced, and the AC impedance is also reduced.In particular, since the second metal wiring is completely covered on the insulating film, the AC impedance is reduced. The decline will be even greater.

すなわち本構成金とることによシ基準電位のインピーダ
ンスが小さくなシ、交流動作時にも直流動作時にも基準
電位の変動を小さく保つことができ本発明の目的を達成
することができる。That is, by using this metal, the impedance of the reference potential is small, and fluctuations in the reference potential can be kept small both during AC operation and during DC operation, and the object of the present invention can be achieved.

以上説明したとおシ本発明によれば、基準電位の変動を
極力少なくすることが可能になシ、入力電圧のマージン
を広くシ、トランジスタのインバータ回路レシオの変動
を防止して、内部回路の誤動作をなくした半導体集積回
路装置を容易に得ることができる。As explained above, according to the present invention, it is possible to reduce fluctuations in the reference potential as much as possible, widen the input voltage margin, prevent fluctuations in the inverter circuit ratio of transistors, and malfunction internal circuits. It is possible to easily obtain a semiconductor integrated circuit device that eliminates this.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のＭＯＳ　）ランジスタの要部模式平面図
、第２図は第１図の一点鎖線部の断面図、第３図は本発
明の一実施例による半導体集積回路装置の断面図である
。 １・・・・・・半導体基板、２・・・・・・拡散層（ソ
ース）、３・・・・・・拡散層（ドレイン）、４・・・
・・・ゲート酸化膜、５・・・・・・ゲート電極、６，
７．８・・・・・・絶縁膜、９・・・・・・ドレイン電
極、１０・・・・・・ソース電極（第１の配線）１１・
・・・・・第２の配線、１２．１３・・・・・・接触面
、１４・・・・・・第１及び第２配線の接点。 穿３図FIG. 1 is a schematic plan view of the main part of a conventional MOS transistor, FIG. 2 is a sectional view taken along the dashed-dotted line in FIG. 1, and FIG. 3 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention. be. 1... Semiconductor substrate, 2... Diffusion layer (source), 3... Diffusion layer (drain), 4...
...Gate oxide film, 5...Gate electrode, 6,
7.8... Insulating film, 9... Drain electrode, 10... Source electrode (first wiring) 11.
...Second wiring, 12.13...Contact surface, 14...Contact point of first and second wiring. Diagram 3

Claims (1)

【特許請求の範囲】[Claims] 基準電位（ＧＮＤ）配線を金属配線による二層配線とし
、前記配線の第１の配線は拡散層とコンタクトラとシ第
２の配線はチップの表面絶縁膜を全面的に覆う金属配線
とし、第１の金属配線と第２の金属配線は少なくとも一
点以上で電気的に接続されていることを特徴とする半導
体集積回路装置。The reference potential (GND) wiring is a two-layer wiring made of metal wiring, the first wiring is a diffusion layer and a contact layer, the second wiring is a metal wiring that completely covers the surface insulating film of the chip, and the second wiring is a metal wiring that completely covers the surface insulating film of the chip. 1. A semiconductor integrated circuit device, wherein a first metal wiring and a second metal wiring are electrically connected at at least one point.