JPS5932901B2 - Integrated photodetector circuit device - Google Patents
Integrated photodetector circuit deviceInfo
- Publication number
- JPS5932901B2 JPS5932901B2 JP55169678A JP16967880A JPS5932901B2 JP S5932901 B2 JPS5932901 B2 JP S5932901B2 JP 55169678 A JP55169678 A JP 55169678A JP 16967880 A JP16967880 A JP 16967880A JP S5932901 B2 JPS5932901 B2 JP S5932901B2
- Authority
- JP
- Japan
- Prior art keywords
- type semiconductor
- region
- semiconductor region
- layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 96
- 239000000758 substrate Substances 0.000 claims description 25
- 238000002955 isolation Methods 0.000 claims description 13
- 238000000926 separation method Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】
この発明は、ＰＮ接合を有する受光素子と受光電流増幅
器とを同一半導体基板上に形成した集積化受光回路装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated light receiving circuit device in which a light receiving element having a PN junction and a light receiving current amplifier are formed on the same semiconductor substrate.
この種の装置の従来例を第１図に示す。A conventional example of this type of device is shown in FIG.
第２図は第１図に示した装置の等価回路である。第１図
の装置は、Ｐ型半導体基板１上にＮ型エピタキシャル層
２を形成し、このエピタキシャル層２を拡散Ｐ型半導体
層３で複数の領域に分離し、領域２１にはＰ型半導体領
域４を拡散形成して受光ダイオード５を形成し、領域２
２にはＰ型半導体領域６とＮ型半導体領域Ｔを順次拡散
形成してＮＰＮトランジスタ８を形成し、領域２３には
Ｐ型半導体領域９を形成して抵抗１０を形成したもので
ある。このような装置において、光が、Ｎ型半導体領域
２１とその外側のＰ型領域（基板１とＰ型半導体層３か
らなる）で形成されるＰＮ接合を介して入射されると、
このＰＮ接合部で光のエネルギが消費されるので、Ｐ型
半導体領域４からＮ型半導体領域２１に流れる光電流と
して有効に利用されない。したがつて、有効に光電流に
変換される光は、Ｐ型半導体領域４の真上（第１図符号
１１参照）から入射される光に限定される欠点があつた
。また、Ｎ型半導体領域２１はＰ型領域に包囲されてい
るため、充分な深さを持つことができない。したがつて
、Ｎ型半導体領域２１は充分な時間、光エネルギを吸収
できないため、入射光を効率よく光電流に変換できない
欠点を有していた。第３図は従来の他の装置を示し、第
４図は第３図の装置の等価回路である。FIG. 2 is an equivalent circuit of the device shown in FIG. In the device shown in FIG. 1, an N-type epitaxial layer 2 is formed on a P-type semiconductor substrate 1, and this epitaxial layer 2 is separated into a plurality of regions by a diffused P-type semiconductor layer 3. 4 is diffused to form a light receiving diode 5.
2, a P-type semiconductor region 6 and an N-type semiconductor region T are sequentially diffused to form an NPN transistor 8, and a P-type semiconductor region 9 is formed in region 23 to form a resistor 10. In such a device, when light is incident through the PN junction formed by the N-type semiconductor region 21 and the P-type region outside it (consisting of the substrate 1 and the P-type semiconductor layer 3),
Since the energy of the light is consumed at this PN junction, it is not effectively used as a photocurrent flowing from the P-type semiconductor region 4 to the N-type semiconductor region 21. Therefore, there is a drawback that the light that is effectively converted into photocurrent is limited to the light that is incident from directly above the P-type semiconductor region 4 (see reference numeral 11 in FIG. 1). Furthermore, since the N-type semiconductor region 21 is surrounded by the P-type region, it cannot have a sufficient depth. Therefore, since the N-type semiconductor region 21 cannot absorb optical energy for a sufficient period of time, it has the disadvantage that it cannot efficiently convert incident light into photocurrent. FIG. 3 shows another conventional device, and FIG. 4 is an equivalent circuit of the device shown in FIG.
第３図の装置は、Ｐ型半導体基板２１を用い、これに、
Ｎ型半導体領域２２を、たとえば拡散などの力法で形成
することによりＰＮ接合型受光ダイオード２３を形成し
たものである。また、第３図の装置では、Ｐ型半導体基
板２１に形成したｎ型半導体領域２４で抵抗２５が形成
されており、さらにＰ型半導体基板２１に形成したＮ型
半導体領域２６内にｒ型半導体領域２７ｊ６よびｖ型半
導体領域２８を順次形成することによりトランジスタ２
９が形成されている。なお、３０は受光ダイオード２３
のカソード取出しのためにＮ型半導体領域２２内に形成
されたＮ＋型半導体領域、３１はＮＰＮトランジスタ２
９のコレクタ取出しのためにＮ型半導体領域２６内に形
成されたＮ＋型半導体領域である。しかし、第３図の装
置は、ｒ型半導体領域２７の拡散形成時に、Ｎ型半導体
領域２２，２４，２６が深く追拡散されるため、受光ダ
イオード２３の接合容量が増大する製造上の欠点を有し
ていた。Ｎ型半導体領域２２，２４，２６が深く追拡散
される理由は、そのＮ型半導体領域２２，２４，２６を
形成するためのＮ型不純物の拡散係数が大きいためであ
る。また、Ｐ型半導体基板は表面にＮ型反転層が発生し
やすいので、第３図の装置は、ＰＮ接合部の耐電圧特姓
の劣化を招く欠点も有していた。The device shown in FIG. 3 uses a P-type semiconductor substrate 21, in which:
A PN junction type light receiving diode 23 is formed by forming an N type semiconductor region 22 by a force method such as diffusion. Further, in the device shown in FIG. 3, a resistor 25 is formed in an n-type semiconductor region 24 formed on a P-type semiconductor substrate 21, and an r-type semiconductor is further formed in an N-type semiconductor region 26 formed on the P-type semiconductor substrate 21. By sequentially forming the region 27j6 and the v-type semiconductor region 28, the transistor 2
9 is formed. In addition, 30 is a light receiving diode 23
An N+ type semiconductor region 31 is formed in the N type semiconductor region 22 for taking out the cathode of the NPN transistor 2.
This is an N+ type semiconductor region formed within the N type semiconductor region 26 for taking out the collector of No. 9. However, the device shown in FIG. 3 has a manufacturing disadvantage in that the junction capacitance of the light receiving diode 23 increases because the N-type semiconductor regions 22, 24, and 26 are deeply additionally diffused when the R-type semiconductor region 27 is diffused. had. The reason why the N-type semiconductor regions 22, 24, and 26 are additionally diffused deeply is because the diffusion coefficient of the N-type impurity for forming the N-type semiconductor regions 22, 24, and 26 is large. Furthermore, since an N-type inversion layer is likely to occur on the surface of a P-type semiconductor substrate, the device shown in FIG. 3 also has the drawback of deteriorating the withstand voltage characteristics of the PN junction.
この発明は上記の点に鑑みなされたもので、光電変換効
率を向士させることができるとともに、光の入射方向の
制限を解くことができ、さらには受光ダイオードの接合
容量の増大、ＰＮ接合部の耐電圧特性の劣化を防止でき
る集積化受光回路装置を提供することを目的とする。以
下この発明の実施例を図面を参照して説明する。This invention was made in view of the above points, and it is possible to improve the photoelectric conversion efficiency, remove the restriction on the incident direction of light, and further increase the junction capacitance of the photodetector diode, and reduce the PN junction. An object of the present invention is to provide an integrated light-receiving circuit device that can prevent deterioration of withstand voltage characteristics. Embodiments of the present invention will be described below with reference to the drawings.
第５図ＡないしＤはこの発明の実施例の装置を製造工程
順に示す断面図である。したがつて、実施例は、製造工
程に従つて説明することにする。第５図Ａにおいて、４
１はシリコンＮ型半導体基板であり、まず、このＮ型半
導体基板４１の所望の表面領域にＰ型半導体領域４２を
形成する。このＰ型半導体領域４２は、イオン注入法で
シート抵抗２ＫΩ／口程度に形成する。しかる後、この
Ｐ型半導体領域４２の所望の表面領域内にＮ＋フローテ
イング層４３，，４３２を所定距離離間して形成する。
このＮ＋フローテイング層４３１，４３２は、Ｐ型半導
体領域４２内にＳｂなどを拡散することにより形成する
。また、ｖフローテイング層４３１，４３２はシート抵
抗２０Ω／口程度に形成する。次に、Ｎ型半導体基板４
１の全体の上にＮ型半導体層４４をエピタキシヤル成長
法により形成する（第５図Ｂ参照）。FIGS. 5A to 5D are cross-sectional views showing the apparatus according to the embodiment of the present invention in the order of manufacturing steps. Therefore, the examples will be described according to the manufacturing process. In Figure 5A, 4
1 is a silicon N-type semiconductor substrate, and first, a P-type semiconductor region 42 is formed in a desired surface area of this N-type semiconductor substrate 41. This P-type semiconductor region 42 is formed by ion implantation to have a sheet resistance of about 2 KΩ/hole. Thereafter, N+ floating layers 43, 432 are formed in a desired surface area of this P-type semiconductor region 42 at a predetermined distance apart.
The N+ floating layers 431 and 432 are formed by diffusing Sb or the like into the P-type semiconductor region 42. Further, the v-floating layers 431 and 432 are formed to have a sheet resistance of about 20Ω/hole. Next, the N-type semiconductor substrate 4
An N-type semiconductor layer 44 is formed on the entire substrate 1 by epitaxial growth (see FIG. 5B).
続いて、拡散によりＰ型アイソレーシヨン領域４５を形
成する。Subsequently, a P-type isolation region 45 is formed by diffusion.
このＰ型アイソレーシヨン領域４５は、Ｎ型半導体層４
４の表面部分からＰ型半導体領域４２に到達するように
、かつフローテイング層４３１，４３２の各々を包囲す
るごとくＮ型半導体層４４に形成する（第５図Ｃ参照）
。次に、第１の分離領域４４１、すなわち、Ｐ型アイソ
レーシヨン領域４５とＰ型半導体領域４２で分離された
Ｎ＋フローテイング層４３１（第１のＸフローテイング
層）上のＮ型半導体層領域に、ベース領域としてのＰ型
半導体領域４６を形成する。このＰ型半導体領域４６は
、シート抵抗２００Ω／口程度のボロン拡散により形成
する。この時、同時に、第２の分離領域４４２、すなわ
ち、上記と同様にして分離されたｖフローテイング層４
３２（第２のフローテイング層）上のＮ型半導体層領域
に、抵抗４７としてＰ型半導体領域４８を形成する。ま
た、受光ダイオード４９を形成するためのＰ型半導体領
域５０を、分離されていないＮ型半導体層領域４４３に
形成する（第５図Ｄ参胸。しかる後に、第５図Ｄの同図
に示すように、Ｐ型半導体領域４６にＮ型半導体領域５
１を形成する。このＮ型半導体領域５１はエミツタ領域
としてであり、リン拡散により形成する。したがつて、
第１の分離領域４４１には、この領域４４１をコレクタ
領域として、Ｐ型半導体領域４６およびＮ型半導体領域
５１とによりＮＰＮトランジスタ５２が形成される。エ
ミツタ領域としてのＮ型半導体領域５１を形成する際、
同時に、第１の分離領域４４１にＮ＋型半導体領域５３
を形成する。This P-type isolation region 45 corresponds to the N-type semiconductor layer 4.
The N-type semiconductor layer 44 is formed so as to reach the P-type semiconductor region 42 from the surface portion of 4 and to surround each of the floating layers 431 and 432 (see FIG. 5C).
. Next, the first isolation region 441, that is, the N-type semiconductor layer region on the N+ floating layer 431 (first X floating layer) separated by the P-type isolation region 45 and the P-type semiconductor region 42. Then, a P-type semiconductor region 46 as a base region is formed. This P-type semiconductor region 46 is formed by boron diffusion with a sheet resistance of about 200 Ω/hole. At this time, at the same time, the second separation region 442, that is, the v floating layer 4 separated in the same manner as above.
A P-type semiconductor region 48 is formed as a resistor 47 in the N-type semiconductor layer region on 32 (second floating layer). Further, a P-type semiconductor region 50 for forming a light-receiving diode 49 is formed in the unseparated N-type semiconductor layer region 443 (see FIG. 5D). As shown in FIG.
form 1. This N-type semiconductor region 51 serves as an emitter region and is formed by phosphorus diffusion. Therefore,
An NPN transistor 52 is formed in the first isolation region 441 by the P-type semiconductor region 46 and the N-type semiconductor region 51, with this region 441 serving as a collector region. When forming the N-type semiconductor region 51 as an emitter region,
At the same time, an N+ type semiconductor region 53 is formed in the first isolation region 441.
form.
このｙ型半導体領域５３は、コレクタを取出すための領
域である。続いて、受光ダイオード４９、ＮＰＮトラン
ジスタ５２および抵抗４７を結線するためのＡｔ配線５
４を表面に形成し、以上で集積化受光回路装置の製造を
終了する。なお、５５は表面に形成された絶縁膜である
。以上のようにして製造された装置においては、第５図
Ｄの矢印５６で示す方向から、Ｎ型半導体層４４上の表
面に向つて光を入射させる方法が、効率の面から考えて
最もよい。This y-type semiconductor region 53 is a region for taking out the collector. Subsequently, an At wiring 5 for connecting the light receiving diode 49, the NPN transistor 52, and the resistor 47 is connected.
4 is formed on the surface, and the manufacturing of the integrated light receiving circuit device is thus completed. Note that 55 is an insulating film formed on the surface. In the device manufactured as described above, the best method in terms of efficiency is to make the light enter the surface of the N-type semiconductor layer 44 from the direction shown by the arrow 56 in FIG. 5D. .
また、光結合力法との関係でＮ型半導体基板４１の裏面
から光の入射を行わせる必要がある場合には、第６図Ａ
およびＢの他の実施例に示すようにすることにより、裏
面からの光の入射を行わすことができる。In addition, if it is necessary to make light incident from the back surface of the N-type semiconductor substrate 41 in relation to the optical coupling force method, FIG.
By doing as shown in the other embodiments B and B, light can be incident from the back surface.
すなわち、この実施例では、Ｐ型半導体領域５０に対応
するＮ型半導体基板４１の裏面部５７をエツチングなど
の方法により薄くし、ウエル５８として形成するもので
ある。第６図Ｂにおいて、５９は光の入射ビームを示す
。なお、Ｎ型半導体基板４１として（１００）方向の結
晶軸をもつものを用い、ウエル５８形成用としてＫＯＨ
系エツチヤントを用いることで、上記所望のＮ型半導体
基板裏面光入射構造を容易に形成することができた。第
７図は、以上のような、この発明の実施例の装置の等価
回路図を示す。That is, in this embodiment, the back surface portion 57 of the N-type semiconductor substrate 41 corresponding to the P-type semiconductor region 50 is thinned by a method such as etching to form a well 58. In FIG. 6B, 59 indicates an incident beam of light. Note that the N-type semiconductor substrate 41 has a crystal axis in the (100) direction, and KOH is used for forming the well 58.
By using the etchant, it was possible to easily form the desired backside light incident structure of the N-type semiconductor substrate. FIG. 7 shows an equivalent circuit diagram of the device according to the embodiment of the present invention as described above.
以上実施例で詳述したように、この発明の集積化受光回
路装置では、Ｎ型半導体基板上にＮ型半導体層をエピタ
キシヤル成長により形成して、このＮ型半導体層にＰＮ
接合分離により分離してトランジスタと抵抗を形成する
とともに、分離領域以外のＮ型半導体層領域にＰ型半導
体領域を形成して受光素子を形成するものである。As described in detail in the embodiments above, in the integrated light receiving circuit device of the present invention, an N-type semiconductor layer is formed on an N-type semiconductor substrate by epitaxial growth, and a PN layer is formed on this N-type semiconductor layer.
A transistor and a resistor are formed by separating by junction isolation, and a P-type semiconductor region is formed in an N-type semiconductor layer region other than the isolation region to form a light-receiving element.
したがつて入射光によりＰＮ接合で発生するキヤリアの
拡散長が長いＮ型半導体領域を、分離領域以外のＮ型半
導体層領域およびＮ型半導体基板で充分大きくとること
が可能になり、光電変換効率を向上させることができる
とともに、受光素子のＰＮ接合部を包囲するＰＮ接合領
域がなく、たとえ斜方向からの入射光であつても、その
入射光が途中で吸収されることがないので、その場合も
光電変換効率を向上させることができる。実際、従来の
装置と比較実験を行つたところ、この発明の装置では、
従来に比較して約１．５倍、光電変換効率を向上させる
ことができた。また、受光素子のＰＮ接合部を包囲する
ＰＮ接合領域がないので、光の入射方向は、表面側に限
らず裏面側からも行うことができるようになり、光の入
射方向の制限を解くことができる。さらに、この装置に
おいては、エピタキシヤル成長のＮ型半導体層に、拡散
係数の小さいＰ型不純物を用いてＰ型半導体領域を形成
することにより受光素子を形成しているので、そのＰ型
半導体領域の形成後に他の拡散形成工程があつても、そ
の半導体領域が追拡散されることはなく、受光素子の接
合容量が増大することはない。さらに、この装置におい
ては、Ｎ型半導体基板上にＮ型半導体層をエピタキシヤ
ル成長して基板部を構成しているので、この基板部の表
面に反転層が形成されてＰＮ接合部の耐電圧特性が劣化
することは防止される。Therefore, the N-type semiconductor region where the diffusion length of carriers generated at the PN junction by incident light is long can be made sufficiently large in the N-type semiconductor layer region other than the separation region and the N-type semiconductor substrate, and the photoelectric conversion efficiency can be increased. In addition, there is no PN junction area surrounding the PN junction of the light receiving element, and even if the incident light is incident from an oblique direction, the incident light will not be absorbed on the way. In this case, the photoelectric conversion efficiency can also be improved. In fact, when we conducted a comparative experiment with a conventional device, we found that the device of this invention:
The photoelectric conversion efficiency was improved by approximately 1.5 times compared to conventional methods. In addition, since there is no PN junction region surrounding the PN junction of the light receiving element, the direction of light incidence can be done not only from the front side but also from the back side, eliminating restrictions on the direction of light incidence. Can be done. Furthermore, in this device, the light-receiving element is formed by forming a P-type semiconductor region in the epitaxially grown N-type semiconductor layer using a P-type impurity with a small diffusion coefficient. Even if another diffusion formation step is performed after the formation of the semiconductor region, the semiconductor region will not be further diffused, and the junction capacitance of the light receiving element will not increase. Furthermore, in this device, since the substrate portion is formed by epitaxially growing an N-type semiconductor layer on the N-type semiconductor substrate, an inversion layer is formed on the surface of the substrate portion, which increases the withstand voltage of the PN junction. Deterioration of characteristics is prevented.
第１図は従来の集積化受光回路装置を示す断面図、第２
図は第１図装置の等価回路図、第３図は従来の装置の他
の例を示す断面図、第４図は第３図装置の等価回路図、
第５図ＡないしＤはこの発明の集積化受光回路装置の実
施例を製造工程順に示す断面図、第６図ＡおよびＢはこ
の発明の他の実施例を示す断面図、第７図はこの発明の
実施例の装置の等価回路図である。
４１・・・・・・シリコンＮ型半導体基板、４２・・・
・・・Ｐ型半導体領域、４３１，４３２・・・・・・Ｎ
＋フローテイング層、４４・・・・・・Ｎ型半導体層、
４４１・・・・・・第１の分離領域、４４２・・・・・
・第２の分離領域、４４３・・・・・・分離領域以外の
Ｎ型半導体層領域、４５・・・・・・Ｐ型アイソレーシ
ヨン領域、４７・・・・・・抵抗、４９・・・・・・受
光ダイオード、５０・・・・・・Ｐ型半導体領域、５２
・・・・・・ＮＰＮトランジスタ。Figure 1 is a sectional view showing a conventional integrated light receiving circuit device;
The figure is an equivalent circuit diagram of the device shown in FIG. 1, FIG. 3 is a sectional view showing another example of the conventional device, and FIG. 4 is an equivalent circuit diagram of the device shown in FIG.
5A to 5D are cross-sectional views showing an embodiment of the integrated light-receiving circuit device of the present invention in the order of manufacturing steps; FIGS. 6A and B are sectional views showing other embodiments of the present invention; and FIG. FIG. 2 is an equivalent circuit diagram of a device according to an embodiment of the invention. 41...Silicon N-type semiconductor substrate, 42...
...P-type semiconductor region, 431,432...N
+ floating layer, 44...N-type semiconductor layer,
441...First separation area, 442...
- Second isolation region, 443... N-type semiconductor layer region other than the isolation region, 45... P-type isolation region, 47... Resistor, 49... . . . Photodetector diode, 50 . . . P-type semiconductor region, 52
...NPN transistor.
Claims (1)
所望の表面領域に形成されたＰ型半導体領域と、このＰ
型半導体領域の所望の表面領域内に所定距離離間して形
成された第１および第２のＮ＾＋フローティング層と、
上記Ｎ型半導体基板全体の上にエピタキシャル成長によ
り形成されたＮ型半導体層と、上記Ｐ型半導体領域に到
達し、かつ上記第１および第２のＮ＾＋フローティング
層を各々包囲するごとく上記Ｎ型半導体層に形成された
Ｐ型アイソレーシヨン領域と、このＰ型アイソレーシヨ
ン領域と上記Ｐ型半導体領域により分離された上記第１
のＮ＾＋フローティング層上のＮ型半導体層領域に形成
されたトランジスタと、同様にして分離された上記第２
のＮ＾＋フローティング層上のＮ型半導体層領域に形成
された抵抗と、上記分離領域以外のＮ型半導体層領域に
形成され、受光素子を構成するためのＰ型半導体領域と
を具備してなる集積化受光回路装置。1 A silicon N-type semiconductor substrate, a P-type semiconductor region formed in a desired surface region of this N-type semiconductor substrate, and a P-type semiconductor region formed in a desired surface region of this N-type semiconductor substrate;
first and second N^+ floating layers formed at a predetermined distance apart within a desired surface region of the type semiconductor region;
The N-type semiconductor layer is formed by epitaxial growth on the entire N-type semiconductor substrate, and the N-type semiconductor layer reaches the P-type semiconductor region and surrounds the first and second N^+ floating layers. a P-type isolation region formed in the semiconductor layer; and the first P-type isolation region separated by the P-type semiconductor region.
The transistor formed in the N-type semiconductor layer region on the N^+ floating layer and the second transistor separated in the same way.
a resistor formed in an N-type semiconductor layer region on the N^+ floating layer, and a P-type semiconductor region formed in an N-type semiconductor layer region other than the separation region to constitute a light receiving element. An integrated light receiving circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55169678A JPS5932901B2 (en) | 1980-12-03 | 1980-12-03 | Integrated photodetector circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55169678A JPS5932901B2 (en) | 1980-12-03 | 1980-12-03 | Integrated photodetector circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5793567A JPS5793567A (en) | 1982-06-10 |
| JPS5932901B2 true JPS5932901B2 (en) | 1984-08-11 |
Family
ID=15890871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55169678A Expired JPS5932901B2 (en) | 1980-12-03 | 1980-12-03 | Integrated photodetector circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5932901B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6043857A (en) * | 1983-08-20 | 1985-03-08 | Mitsubishi Electric Corp | Solid-state image pickup device and manufacture thereof |
| JPH0620158B2 (en) * | 1984-03-08 | 1994-03-16 | 新技術事業団 | Semiconductor radiation distribution detector |
| JPH01123480A (en) * | 1987-11-07 | 1989-05-16 | Fuji Electric Co Ltd | Photo detector |
-
1980
- 1980-12-03 JP JP55169678A patent/JPS5932901B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5793567A (en) | 1982-06-10 |
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