JPS5932125A - Mask for ion implantation - Google Patents

Mask for ion implantation

Info

Publication number
JPS5932125A
JPS5932125A JP14112682A JP14112682A JPS5932125A JP S5932125 A JPS5932125 A JP S5932125A JP 14112682 A JP14112682 A JP 14112682A JP 14112682 A JP14112682 A JP 14112682A JP S5932125 A JPS5932125 A JP S5932125A
Authority
JP
Japan
Prior art keywords
mask
implanting
ion implantation
ion
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14112682A
Other languages
Japanese (ja)
Inventor
Kuniyuki Sakumichi
訓之 作道
Keizo Suzuki
敬三 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14112682A priority Critical patent/JPS5932125A/en
Publication of JPS5932125A publication Critical patent/JPS5932125A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To micro-miniaturize the ion implantation area and make thin the mask by providing the mask covering non-implanting area on the surface of solid such as semiconductor and inclining the end surface of mask from the perpendicular line on the surface of solid on the occasion of implanting the ion only to the specific region. CONSTITUTION:An ion implantation mask 2' of specified pattern is formed on a substrate 1 consisting of a semiconductor or magnetic material and an implanted area is formed by obliquely implanting ion beam to the exposed surface of substrate 1 with inclination angle of beta. In such constitution, the end surface of mask 2' is inclined by an angle of alpha from the perpendicular line on the surface of substrate 1. This angle alpha is almost equal to an inclination angle beta of ion 3 or a little larger than the inclination angle beta. Thereby, the shadow 4 of implanting surface by mask is not generated and the implanting area can be microminiaturized and thickness of mask can also be reduced.

Description

【発明の詳細な説明】 本発明は、半導体など固体表面の特定の領域にだけイオ
ン打込みをするだめの非打込領域を覆うマスクの改良に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a mask that covers a non-implanted region for implanting ions only into a specific region of the surface of a solid such as a semiconductor.

トランジスタなどの半導体素子をつくるときの不純物ド
ーピングや磁気バブル素子をつくるときの磁気特性の制
御の目的で固体表面の特定部分にだけイオン打込みをす
るという方法がとられている。この場合、第１図に示す
ように固体１０表面のイオン打込みをしたくない部分に
酸化物、レジスト又は金属などのマスク２を付けてから
イオン３を打込み、このあと、マスク２を化学的、ある
いは物理的方法で除去するという方法がとられる。A method of implanting ions only into specific parts of a solid surface is used for the purpose of doping impurities when making semiconductor devices such as transistors and controlling magnetic properties when making magnetic bubble elements. In this case, as shown in FIG. 1, a mask 2 of oxide, resist, or metal is attached to the portion of the surface of the solid 10 where ion implantation is not desired, and then the ions 3 are implanted. Alternatively, a physical method may be used to remove it.

しかしながら、一般のイオン打込みではイオン３がチャ
ネリング効果により深くまで入シ込まないように、第２
図に示すようにイオンビーム３を固体１の表面に立てた
垂線から７°前後傾けで打込むことが多い。この場合、
マスク２の影４が固体１の表面に出来るためマスク２の
通りの打込領域ができないという問題が生じる。この問
題は素子の微細化が進む程、重大になってくる。However, in general ion implantation, in order to prevent ions 3 from entering deeply due to channeling effects, the second
As shown in the figure, the ion beam 3 is often implanted at an angle of 7 degrees from the perpendicular to the surface of the solid 1. in this case,
Since the shadow 4 of the mask 2 is formed on the surface of the solid 1, a problem arises in that the implantation area according to the mask 2 cannot be formed. This problem becomes more serious as the device becomes finer.

イオン打込用マスク２の必要な厚味は打込みエネルギー
とイオンの質量とにより決まるから、打込領域の微細化
と共に厚味を減らすことはできない。Since the necessary thickness of the ion implantation mask 2 is determined by the implantation energy and the mass of the ions, the thickness cannot be reduced with miniaturization of the implantation region.

この発明の目的はこのような問題点を解消したイオン打
込用マスクを提供することにある。An object of the present invention is to provide an ion implantation mask that solves these problems.

上記目的を達成するために本発明においてはマスクの端
面が固体表面上に立てた垂線から傾斜するようにイオン
打込用マスクを構成したことを特徴としている。In order to achieve the above object, the present invention is characterized in that the ion implantation mask is constructed such that the end face of the mask is inclined from a perpendicular line erected on the solid surface.

以下、本発明の一実施例を第２図により説明する。第２
図において、１は半導体基板あるいは磁性材基板のよう
な基板である。この基板ｌ上に本発明の最も特徴とする
イオン打込用マスク２′が載置されている。このマスク
２′の端面は基板１に立てた垂線から角度αだけ傾斜し
ている。この傾斜角度ａはイオン３の傾斜角度βとほぼ
同じか、またはそれよりも若干大きくなっている。この
ようにすることによって、第２図の影４を全く無くする
ことができる。An embodiment of the present invention will be described below with reference to FIG. Second
In the figure, 1 is a substrate such as a semiconductor substrate or a magnetic material substrate. An ion implantation mask 2', which is the most characteristic feature of the present invention, is placed on this substrate l. The end face of this mask 2' is inclined at an angle α from a perpendicular to the substrate 1. This inclination angle a is approximately the same as the inclination angle β of the ions 3, or is slightly larger than that. By doing this, the shadow 4 in FIG. 2 can be completely eliminated.

実際、このようなマスク２′はプラズマエツチングのよ
うな方法でそのパラメータを制御することによってつく
ることができる。In fact, such a mask 2' can be produced by controlling its parameters with methods such as plasma etching.

このように本発明によれば、打込領域を微細化してもマ
スクの影の影響を無く゛することができるという顕著な
効果が得られる。As described above, according to the present invention, it is possible to obtain the remarkable effect that even if the implantation area is miniaturized, the influence of the shadow of the mask can be eliminated.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図は従来のイオン打込による不純物ドー
ピングを示す図で、第１図は垂直入射の例で、第２図は
チャネリングを避けるために科目にイオンを入射する場
合の例、第３図は本発明によるマスクの一実施例を示す
図でちる。 １・・・イオン打込をする固体試料、２・・・マスク、
２′・・・本発明によるマスク、３・・・イオンビーム
、１２−Figures 1 and 2 are diagrams showing impurity doping by conventional ion implantation, where Figure 1 is an example of vertical injection, Figure 2 is an example of ion injection into the subject to avoid channeling, FIG. 3 is a diagram showing an embodiment of the mask according to the present invention. 1... Solid sample for ion implantation, 2... Mask,
2'... Mask according to the present invention, 3... Ion beam, 12-

Claims (1)

【特許請求の範囲】[Claims] １、固体表面にイオンを打込む時の打込み領域を制限す
るためのマスクにおいて、上記マスクがその端面を上記
固体面上に立てた垂線から傾斜してなることを特徴とす
るイオン打込用マスク。1. An ion implantation mask for limiting an implantation area when implanting ions into a solid surface, characterized in that the end face of the mask is inclined from a perpendicular to the solid surface. .
JP14112682A 1982-08-16 1982-08-16 Mask for ion implantation Pending JPS5932125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14112682A JPS5932125A (en) 1982-08-16 1982-08-16 Mask for ion implantation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14112682A JPS5932125A (en) 1982-08-16 1982-08-16 Mask for ion implantation

Publications (1)

Publication Number Publication Date
JPS5932125A true JPS5932125A (en) 1984-02-21

Family

ID=15284763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14112682A Pending JPS5932125A (en) 1982-08-16 1982-08-16 Mask for ion implantation

Country Status (1)

Country Link
JP (1) JPS5932125A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0880174A1 (en) * 1997-05-21 1998-11-25 Nec Corporation Method of fabricating semiconductor device capable of providing mosfet which is improved in a threshold voltage thereof
EP2761648A4 (en) * 2011-09-30 2015-06-24 Intel Corp Non-planar transitor fin fabrication

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0880174A1 (en) * 1997-05-21 1998-11-25 Nec Corporation Method of fabricating semiconductor device capable of providing mosfet which is improved in a threshold voltage thereof
US6281094B1 (en) 1997-05-21 2001-08-28 Nec Corporation Method of fabricating semiconductor device capable of providing MOSFET which is improved in a threshold voltage thereof
EP2761648A4 (en) * 2011-09-30 2015-06-24 Intel Corp Non-planar transitor fin fabrication

Similar Documents

Publication Publication Date Title
US4394182A (en) Microelectronic shadow masking process for reducing punchthrough
US5770502A (en) Method of forming a junction in a flash EEPROM cell by tilt angle implanting
JPS6032364A (en) Manufacture of semiconductor device
JPS61220424A (en) Manufacture of semiconductor device
JPS5932125A (en) Mask for ion implantation
JPS6421919A (en) Manufacture of semiconductor device
GB2138632A (en) Self-aligned double layers of poly-crystalline silicon
JPS60733A (en) Semiconductor device and manufactur thereof
JPS56107552A (en) Manufacture of semiconductor device
JPS55134929A (en) Ion implantation
JPS59119870A (en) Manufacture of semiconductor device
JPS59208784A (en) Manufacture of semiconductor device
JP2709086B2 (en) Method for forming electrode of semiconductor device
JPS62159469A (en) Manufacture of insulated gate type field effect transistor
JPS62274621A (en) Ion implantation
JPS59228718A (en) Semiconductor device
JPH04249316A (en) Manufacture of semiconductor device
JPS57170571A (en) Manufacture of mos type semiconductor device
GB1294515A (en) Improvements in or relating to the fabrication of semiconductor devices
KR960010735B1 (en) Rom structure and manufacturing method thereof
JPS6243341B2 (en)
KR100232884B1 (en) Manufacturing method of semiconductor memory device
KR100404220B1 (en) Method for manufacturing semiconductor device using tilt etching process
JPS60240131A (en) Manufacture of semiconductor device
JPS6350014A (en) Manufacture of semiconductor device