JPS5927548A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5927548A JPS5927548A JP57137261A JP13726182A JPS5927548A JP S5927548 A JPS5927548 A JP S5927548A JP 57137261 A JP57137261 A JP 57137261A JP 13726182 A JP13726182 A JP 13726182A JP S5927548 A JPS5927548 A JP S5927548A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- pellet
- semiconductor device
- package
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 abstract description 24
- 239000008188 pellet Substances 0.000 abstract description 15
- 239000010408 film Substances 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000003068 static effect Effects 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0232—Optical elements or arrangements associated with the device
- H01L31/02325—Optical elements or arrangements associated with the device the optical elements not being integrated nor being directly associated with the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は気密封止され１なるぶツケージに透光性部材を
備えた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that is hermetically sealed and includes a transparent member in a single cage.
一般に、例えば、消去可能な読み出し専用メモＩＪ−（
ＢＰ−ＲＯＭ）に使用される半導体装置において、メモ
リーの消去を紫外線照射により行なっている。そのため
、この種の半導体装置で番ま、紫外線の照射を行なう必
要上、ノ（・ソクージのベレットマウント部の封止用キ
ャップに紫外線透過性ガラス（Ｕｖガラス）を埋め込ん
だり、キャップ゛に紫外線透過用のザファイアまたは透
明アルミナ・ＴＩ！！ ＩＪフッド低融点ガラス等の接
着剤で貼り伺げたりしている。Generally, for example, erasable read-only memo IJ-(
In semiconductor devices used in BP-ROM (BP-ROM), memory is erased by irradiation with ultraviolet rays. Therefore, because it is necessary to irradiate ultraviolet rays with this type of semiconductor device, UV-transparent glass (Uv glass) is embedded in the sealing cap of the bullet mount part of the It can be attached with adhesive such as Zaphire or transparent alumina/TI!! IJ hood low melting point glass.
しかしながら、このような半導体装置にあって（・上、
透光性部材であるＵ■ガラス等が帯電し易いため、この
半導体装置の取扱（・中の摩擦等により、Ｕ■ガラス等
圧電荷が乗り、この電荷がベレット、上に放電現象（コ
ロナ放りを起こし、この放電が非破壊的な誤動作や回路
の破壊の原因になるという欠点があった。However, in such a semiconductor device (・upper,
Since transparent materials such as U glass are easily charged, handling of this semiconductor device (・Due to internal friction, etc., an isobaric charge is placed on the U glass, and this charge is transferred to the pellet, causing a discharge phenomenon (corona discharge). The disadvantage is that this discharge can cause non-destructive malfunctions and circuit destruction.
本発明の目的は、このような欠点を解消し、信頼性の高
い半導体装置を提供することにある。An object of the present invention is to eliminate such drawbacks and provide a highly reliable semiconductor device.
以下、本発明を図面に示ず実施例にしたがって説明する
。Hereinafter, the present invention will be explained based on embodiments not shown in the drawings.
第１図は本発明による半導体装ｔＮの一集施例を示す斜
視図、第２図は第１図のＩｆ −ＩＩ線断面図であるう
本実施例において、この半導体装置はいわゆるサーディ
ツプタイプのパッケージｌを備えており、このパッケー
ジｌは、共罠セラミックから成形されたベース２とキャ
ップ３とを最中合せにされる □ととも罠、両者２．３
の合せ面にガラスシール部４を形成されて気密刺止され
てなる。このパッケージ１０内部釦はペレット５がベー
ス２上にボンディングされて収容されている。ベース２
とキャップ３との合せ目にはリードフレーム６がパッケ
ージ１の内外に鏡って配設されており、リードフレーム
６の内部電極バッドにはペレット５の電極パッドがボン
ディングワイヤ７を介して適宜電気的忙接続されている
。FIG. 1 is a perspective view showing an embodiment of a semiconductor device tN according to the present invention, and FIG. 2 is a sectional view taken along the line If-II in FIG. It comprises a package l of the type □ and a trap, both of which are fitted with a base 2 and a cap 3 molded from co-trap ceramic.
A glass seal portion 4 is formed on the mating surfaces of the two and sealed in an airtight manner. A pellet 5 is bonded onto the base 2 and housed in the internal button of the package 10. base 2
A lead frame 6 is disposed at the joint between the cap 3 and the package 1 so as to mirror the inside and outside of the package 1, and the electrode pad of the pellet 5 is connected to the internal electrode pad of the lead frame 6 via a bonding wire 7. Connected to the point.
本実施例において、キャップ３のペレッ）５に対向する
位置には透光性部材としてのＵＶガラス８が埋め込まれ
ており、このＵＶガラス８の内側表面には導電性被膜９
が紫外線を透過させ得るように形成されている。この導
電性被膜９は、例えば、アルミニウム等導電性を有する
物質を蒸着法等の手段を用い、紫外線が透過し１（）る
秤度の薄膜に形成してＵＶガラス８の内側表面全体に刺
着されてなる。In this embodiment, a UV glass 8 as a translucent member is embedded in a position facing the pellet 5 of the cap 3, and a conductive coating 9 is formed on the inner surface of the UV glass 8.
is formed to allow ultraviolet rays to pass through. This conductive coating 9 is formed by forming a conductive material such as aluminum into a thin film having a thickness of 1 (1) through which ultraviolet rays can pass through, using means such as vapor deposition, for example, to pierce the entire inner surface of the UV glass 8. It will be worn.
前記構成にかかる半導体装置において、パッケージの摩
擦等圧よってＵｖガラス８０表面に静電電荷が乗ったと
しても、ＵＶガラス８の内側表面全体に導電性被膜９が
形成されているため、電荷の集中は発生せず、したがっ
℃、放電現象の発生は未然に回避される。In the semiconductor device having the above configuration, even if electrostatic charges are placed on the surface of the UV glass 80 due to equal pressure of friction of the package, since the conductive film 9 is formed on the entire inner surface of the UV glass 8, the concentration of charges is prevented. Therefore, the occurrence of discharge phenomenon is avoided.
このよ５＆Ｃ１本実施例によれば、放電現象の発生が未
然に防止できるので、ＥＰ−１ｔＯＭにおける放電によ
る非破壊的な誤動作や回路の破壊等の各種弊害を防止す
ることができ、る。According to this embodiment, the occurrence of the discharge phenomenon can be prevented, so that various problems such as non-destructive malfunctions and circuit destruction due to discharge in the EP-1tOM can be prevented.
ところで、ＵＶガラスとペレットとの間の放電の起こり
易さは、ＵＶガラスとペレットとの間隔に反比例する。By the way, the ease with which discharge occurs between the UV glass and the pellet is inversely proportional to the distance between the UV glass and the pellet.
したがって、ＵＶガラスとペレットとの間隔を広げるこ
とにより放電を防止することができる。しかしながら、
ＵＶガラスとペレットとの間隔を広げるためのパッケー
ジの構造の変更は、機械的強度性、気密刺止性２機能的
信頼性等の低下を招来する危険性がある。Therefore, discharge can be prevented by increasing the distance between the UV glass and the pellet. however,
Changing the structure of the package to widen the distance between the UV glass and the pellets has the risk of causing a decrease in mechanical strength, airtightness, functional reliability, etc.
本実施例によれば、ＵＶガラスとペレットとの間隔を広
げることなしに放電を防止することができるので、こ！
７）ような危険性は回避することができる。むしろ、放
電を防止できることから、ＵＶガラスとペレットとの間
隔が小さくなることを妨げない。例えば、ペレットのベ
ースに対するボンディングが高くなることを許容するか
ら、ボンディング精度の公差、ボンディング材料の選定
条件等を緩和することができる。また、機械的強度性。According to this embodiment, it is possible to prevent discharge without increasing the distance between the UV glass and the pellet.
7) Such risks can be avoided. Rather, since discharge can be prevented, the distance between the UV glass and the pellets does not become smaller. For example, since the bonding of the pellet to the base is allowed to be high, tolerances in bonding accuracy, conditions for selecting bonding materials, etc. can be relaxed. Also, mechanical strength.
気密封止性２機能的信頼性等を向上させるためのパッケ
ージの構造変更も可能である。It is also possible to change the structure of the package in order to improve hermetic sealability, functional reliability, etc.
なお、前記実施例では、導電性被膜をＵＶガラスの内側
表面圧紫外線を透過し得るように極薄く形成した場合に
つき説明したが、導電性被膜は格子状または縞状忙形成
することもできるし、内側表面に限らず、外側表面およ
び内外両面忙形成してもよい。また、透光性部材はＵＶ
ガラスに限らず、サファイアまたは透明アルミナ製リッ
ド等であってもよい。In the above embodiments, the conductive film was formed to be extremely thin so that ultraviolet light could pass through the inner surface of the UV glass, but the conductive film could also be formed in a lattice or striped pattern. However, not only the inner surface but also the outer surface and both inner and outer surfaces may be formed. In addition, the light-transmitting member is UV-resistant.
The lid is not limited to glass, and may be made of sapphire or transparent alumina.
さらにζ本発明はＥＰ−ＲＯＭに限らず、受光累子、固
体撮像素子等透光性部拐を有する半導体装置全般に適用
可能である。Furthermore, the present invention is applicable not only to EP-ROMs but also to any semiconductor device having a light-transmitting part, such as a light-receiving device or a solid-state image sensor.
以上説明したように、本発明によれば、静電電荷による
放電現象を防止することができ、信頼性を向上すること
ができる。As described above, according to the present invention, it is possible to prevent a discharge phenomenon caused by electrostatic charges, and it is possible to improve reliability.
第１図は本発明の一実施例を示す斜視図、第２図は第１
図の■−■線断面図である。FIG. 1 is a perspective view showing one embodiment of the present invention, and FIG. 2 is a perspective view showing one embodiment of the present invention.
It is a sectional view taken along the line ■-■ in the figure.
１・・・パッケージ、２・・・ベース、計・・キャップ
、４・・・ガラスシール部、５・・・ペレット、６・・
・リード、フレーム、８・−ＵＶガラス、９・・・導電
性被膜。1...Package, 2...Base, Total...Cap, 4...Glass seal part, 5...Pellet, 6...
- Lead, frame, 8 - UV glass, 9... conductive coating.
Claims (1)
せるための透光性部材を備えた半導体装置において、透
光性部材の表面圧導電性被膜を、光を′透過し得るよう
に形成したこと、を’ｔ＋を徴とする半導体装置。 ２、導電性被膜が、透光性部材のパッケージ内側表面に
形成されたことを特徴とする特許請求の範囲第１項記載
の半導体装置。 ３、導電性被膜が、透光可能に薄（形成されたことを特
徴とする特許請求の範囲第１項または第２項記載の半導
体装置。[Claims] 1. In a semiconductor device equipped with a light-transmitting member for transmitting light through a part of a package formed by airtight sealing, a surface pressure conductive coating of the light-transmitting member is used to transmit light. A semiconductor device characterized by 't+, which means that it is formed to be transparent. 2. The semiconductor device according to claim 1, wherein the conductive film is formed on the inner surface of the package of the light-transmitting member. 3. The semiconductor device according to claim 1 or 2, wherein the conductive film is thin enough to transmit light.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57137261A JPS5927548A (en) | 1982-08-09 | 1982-08-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57137261A JPS5927548A (en) | 1982-08-09 | 1982-08-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5927548A true JPS5927548A (en) | 1984-02-14 |
Family
ID=15194527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57137261A Pending JPS5927548A (en) | 1982-08-09 | 1982-08-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5927548A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4727221A (en) * | 1985-11-15 | 1988-02-23 | Nec Corporation | Semiconductor memory device |
| US6037655A (en) * | 1998-01-12 | 2000-03-14 | Eastman Kodak Company | Linear image sensor package assembly |
-
1982
- 1982-08-09 JP JP57137261A patent/JPS5927548A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4727221A (en) * | 1985-11-15 | 1988-02-23 | Nec Corporation | Semiconductor memory device |
| US6037655A (en) * | 1998-01-12 | 2000-03-14 | Eastman Kodak Company | Linear image sensor package assembly |
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