JPS59227119A - Silicon semiconductor device - Google Patents
Silicon semiconductor deviceInfo
- Publication number
- JPS59227119A JPS59227119A JP10168183A JP10168183A JPS59227119A JP S59227119 A JPS59227119 A JP S59227119A JP 10168183 A JP10168183 A JP 10168183A JP 10168183 A JP10168183 A JP 10168183A JP S59227119 A JPS59227119 A JP S59227119A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal silicide
- silicon semiconductor
- silicide layer
- transition metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 64
- 239000010703 silicon Substances 0.000 title claims description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 30
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910021350 transition metal silicide Inorganic materials 0.000 claims abstract description 29
- 239000003870 refractory metal Substances 0.000 claims 2
- 238000002844 melting Methods 0.000 abstract description 32
- 230000008018 melting Effects 0.000 abstract description 30
- 238000006243 chemical reaction Methods 0.000 abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 abstract description 12
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 229910008814 WSi2 Inorganic materials 0.000 abstract description 3
- 229910020968 MoSi2 Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 229910052723 transition metal Inorganic materials 0.000 description 5
- 150000003624 transition metals Chemical class 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910004217 TaSi2 Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- 229910006249 ZrSi Inorganic materials 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
この発明はシリコン半導体基板が電極孔を有する絶縁膜
で覆われたシリコン半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a silicon semiconductor device in which a silicon semiconductor substrate is covered with an insulating film having electrode holes.
第１図は従来のシリコン半導体装置を示す断面図である
。図において１はシリコン半導体基板、２はシリコン半
導体基板１内に形成された不純物拡散層、６はシリコン
半導体基板１を覆う絶縁膜、４は絶縁膜３に設けられた
電極孔、５は主にアルミニウムとシリコンの合金からな
る配線層である。FIG. 1 is a sectional view showing a conventional silicon semiconductor device. In the figure, 1 is a silicon semiconductor substrate, 2 is an impurity diffusion layer formed in the silicon semiconductor substrate 1, 6 is an insulating film that covers the silicon semiconductor substrate 1, 4 is an electrode hole provided in the insulating film 3, and 5 is a main This is a wiring layer made of an alloy of aluminum and silicon.
このシリコン半導体装置においては、シリコン半導体基
板１と配線層５とが直接に接触しているから、配線層５
を形成する前に電極孔４部のシリコン半導体基板１の表
面に生じたシリコンの自然酸化物等の汚染層が、配線層
５を形成した後においても、シリコン半導体基板１と配
線層５との界面に残存してしまう。このだめ、シリコン
半導体基板１と配線層５との間の接触抵抗が変動し、か
つ増大する。また、配線層５中に含まれるシリコンが電
極部に析出し、この析出したシリコンによっても、シリ
コン半導体基板１と配線層５との間の接触抵抗が変動し
、かつ増大する。In this silicon semiconductor device, since the silicon semiconductor substrate 1 and the wiring layer 5 are in direct contact with each other, the wiring layer 5
Even after the wiring layer 5 is formed, a contamination layer such as natural oxide of silicon generated on the surface of the silicon semiconductor substrate 1 in the electrode hole 4 before the formation of the wiring layer 5 may cause a contamination layer between the silicon semiconductor substrate 1 and the wiring layer 5. It remains on the interface. As a result, the contact resistance between the silicon semiconductor substrate 1 and the wiring layer 5 fluctuates and increases. Further, silicon contained in the wiring layer 5 is deposited on the electrode portion, and the contact resistance between the silicon semiconductor substrate 1 and the wiring layer 5 fluctuates and increases due to the deposited silicon as well.
また、シリコン半導体基板と配線層との界面を用いてシ
ョットキーダイオードを形成したときにも、を極部に残
存した汚染層および析出したシリコンによシ、ダイオー
ドの特性たとえば順方向の立上り電圧が変動し、高集積
のシリコン半導体装置の不良原因となっている。Furthermore, even when a Schottky diode is formed using the interface between a silicon semiconductor substrate and a wiring layer, the contamination layer and precipitated silicon that remain at the extremes can cause the diode characteristics, such as the forward rise voltage, to change. This fluctuation causes defects in highly integrated silicon semiconductor devices.
このような欠点を解決するため、第２図に示すように、
シリコン半導体基板１と配線層５との界面に遷移金属シ
リサイド層６たとえばパラジウム、白金等のシリサイド
層を挿入することが行なわれている。一般にこれらの遷
移金属シリサイドは、これらの遷移金属とＳｉ基板との
反応により形成する。この反応により形成した遷移金属
シリサイドではシリコン半導体基板１と遷移金属シリサ
イド層６との界面に、先に述べた自然酸化物等の汚染層
、シリコン析出層が介在しないので、シリコン半導体基
板１と配線層５との界面の接触抵抗およびその変動が減
少する。In order to solve these drawbacks, as shown in Figure 2,
A transition metal silicide layer 6, such as a silicide layer of palladium, platinum, etc., is inserted into the interface between the silicon semiconductor substrate 1 and the wiring layer 5. Generally, these transition metal silicides are formed by a reaction between these transition metals and a Si substrate. In the transition metal silicide formed by this reaction, there is no contamination layer such as the above-mentioned natural oxide or a silicon precipitate layer at the interface between the silicon semiconductor substrate 1 and the transition metal silicide layer 6, so that the silicon semiconductor substrate 1 and the wiring The contact resistance of the interface with layer 5 and its fluctuations are reduced.
しかし、この半導体装置においては、３００℃以上の熱
処理によって、遷移金属シリサイド層６と配線層５との
間に反応が起こり、遷移金属とアルミニウムとからなる
種々の金属間化合物およびアルミニウムが生成されるの
で、電極の耐熱信頼性が低い。また、これらの生成物中
に含まれるアルミニウムと、シリコン半導体基板１中の
シリコンとが、熱処理によって相互拡散し、不純物拡散
層２の接合を破壊してしまう。However, in this semiconductor device, a reaction occurs between the transition metal silicide layer 6 and the wiring layer 5 due to the heat treatment at 300° C. or higher, and various intermetallic compounds consisting of the transition metal and aluminum and aluminum are generated. Therefore, the heat resistance reliability of the electrode is low. Moreover, the aluminum contained in these products and the silicon in the silicon semiconductor substrate 1 are mutually diffused by the heat treatment, and the bond between the impurity diffusion layer 2 is destroyed.
そこで、第３図に示すように、遷移金属シリサイド層６
と配線層５との間に、モリブデン（Ｍｏ ）、タングス
テン（Ｗ）、クロム（Ｃｒ）等の高融点金属またはチタ
ン（Ｔｉ）−タングステン等の高融点金属間の合金から
力るバリヤ金属層７を挿入して、遷移金属シリサイド層
６と配線層５との間の反応を抑制することが行なわれて
いる。Therefore, as shown in FIG. 3, a transition metal silicide layer 6
A barrier metal layer 7 made of a high melting point metal such as molybdenum (Mo), tungsten (W), or chromium (Cr) or an alloy between high melting point metals such as titanium (Ti) and tungsten is provided between the wiring layer 5 and the wiring layer 5. is inserted to suppress the reaction between the transition metal silicide layer 6 and the wiring layer 5.
しかし、高融点金属の純度が高くなると、高融点金属と
シリコンとの間の反応が起こりやすくなシ、たとえば１
Ｑ Ｐａより低い真空度で清浄シリコン基板上にチタ
ン、クロム等の高融点金属を室温蒸着したときには、蒸
着直後においてすでに高融点金属シリサイドが生成され
る。したがって、遷移金属シリサイド層乙のピンホール
等にょシ、バリヤ金属層７とシリコン半導体基板１とが
接触したときには、シリコン半導体基板１とバリヤ金属
層７との間の反応により、高融点金属シリサイドが生成
され、この反応時に大きな応力が生じてシリコン半導体
基板１に結晶欠陥が発生するのでシリコン半導体装置の
歩留りが大きく低下する。However, as the purity of the high melting point metal increases, reactions between the high melting point metal and silicon tend to occur.
When a high melting point metal such as titanium or chromium is deposited at room temperature on a clean silicon substrate at a vacuum level lower than Q Pa, high melting point metal silicide is already generated immediately after the deposition. Therefore, when the barrier metal layer 7 and the silicon semiconductor substrate 1 come into contact due to pinholes or the like in the transition metal silicide layer B, the high melting point metal silicide is formed due to the reaction between the silicon semiconductor substrate 1 and the barrier metal layer 7. During this reaction, a large stress is generated and crystal defects are generated in the silicon semiconductor substrate 1, resulting in a significant decrease in the yield of silicon semiconductor devices.
また、パラジウム、白金等の遷移金属のシリサイド中で
は、シリコン原子の拡散定数が極めて大きいから、遷移
金属シリサイド層６から拡散したシリコン原子とバリヤ
金属層７の高融点金属とが反応し、高融点金属シリサイ
ドが生成され、この際にもシリコン半導体基板１内に大
きな応力が生じて、シリコン半導体基板１に結晶欠陥が
発生するだめ、シリコン半導体装置の歩留シが大きく低
下する。Furthermore, since the diffusion constant of silicon atoms is extremely large in the silicide of transition metals such as palladium and platinum, the silicon atoms diffused from the transition metal silicide layer 6 react with the high melting point metal of the barrier metal layer 7. Metal silicide is generated, and at this time too, a large stress is generated within the silicon semiconductor substrate 1, causing crystal defects in the silicon semiconductor substrate 1, which greatly reduces the yield of silicon semiconductor devices.
この発明は上述の問題点を解決するために々されたもの
で、耐熱性および信頼性に優れたシリコン半導体装置を
提供することを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a silicon semiconductor device having excellent heat resistance and reliability.
この目的を達成するため、この発明においては。 To achieve this objective, in this invention.
電極孔部のシリコン半導体基板の上に遷移金属シリサイ
ド層を形成し、その遷移金属シリサイド層の上に、上記
遷移金属シリサイド層の金属と異なる金属の高融点金属
シリサイド層を形成し、その高融点金属シリサイド層の
上に配線層を形成する。A transition metal silicide layer is formed on the silicon semiconductor substrate in the electrode hole, and a high melting point metal silicide layer of a metal different from the metal of the transition metal silicide layer is formed on the transition metal silicide layer. A wiring layer is formed on the metal silicide layer.
第４図はこの発明に係るシリコン半導体装置を示す断面
図である。このシリコン半導体装置においては、遷移金
属シリサイド層６と配線層５との間に、ＷＳｉ２． Ｍ
ｏＳｉ２． Ｔｉ Ｓｉ２． ＴａＳｉ２． ＺｒＳｉ
２等からなる高融点金属シリサイド層８が形成し、遷移
金属シリサイド層６と配線層５との間の反応およびシリ
コン半導体基板１と配線層５との間のシリコンとアルミ
ニウムの相互拡散を抑制している。この場合、Ｗ Ｓ
１２等は熱的に安定であるから熱処理によっても高融点
金属シリサイド層８からシリコンが遊離することがない
ので、シリコン半導体基板１、遷移金属シリサイド層６
と高融点金属シリサイド層８とが反応を起こすことはな
い。FIG. 4 is a sectional view showing a silicon semiconductor device according to the present invention. In this silicon semiconductor device, WSi2. M
oSi2. TiSi2. TaSi2. ZrSi
A high melting point metal silicide layer 8 consisting of 2 or the like is formed to suppress the reaction between the transition metal silicide layer 6 and the wiring layer 5 and the interdiffusion of silicon and aluminum between the silicon semiconductor substrate 1 and the wiring layer 5. ing. In this case, W S
12 etc. are thermally stable and silicon will not be liberated from the high melting point metal silicide layer 8 even by heat treatment.
There is no reaction between the metal silicide layer 8 and the high melting point metal silicide layer 8.
また、たとえばＭｏＳｉ２とアルミニウムとは５００℃
以下では反応せず、Ｗ ８１２とアルミニウムとは５５
０℃以下では反応しないから、５００ ℃程度以下の温
度では高融点金属シリサイド層８と配線層５との間の反
応は起こらない。そして、大部分のシリコン半導体装置
の製造法においては、配線形成後に５００℃以上の熱処
理を行なうことはない。さらに、たとえばＷ Ｓ Ｉ
２の融点は２ｏ００℃以上であり、高融点金属シリサイ
ド層８の融点は１６００℃以上と高い。このため、高融
点金属シリサイド層８中の原子の拡散定数は小さいので
、高融点金属シリサイド層８中のシリコンと配線層５中
のアルミニウムとの相互拡散が生ずることはない。Also, for example, MoSi2 and aluminum are heated at 500°C.
There is no reaction below, and W 812 and aluminum are 55
Since no reaction occurs at temperatures below 0°C, no reaction occurs between the high melting point metal silicide layer 8 and the wiring layer 5 at temperatures below approximately 500°C. In most methods of manufacturing silicon semiconductor devices, heat treatment at 500° C. or higher is not performed after wiring is formed. Furthermore, for example, W S I
The melting point of No. 2 is 2000° C. or higher, and the melting point of the high melting point metal silicide layer 8 is as high as 1600° C. or higher. Therefore, since the diffusion constant of atoms in the high melting point metal silicide layer 8 is small, mutual diffusion between silicon in the high melting point metal silicide layer 8 and aluminum in the wiring layer 5 does not occur.
なお、高融点金属シリサイド層８の厚さが小さすぎると
、遷移金属シリサイド層６と配線層５との間の反応を有
効に防止することができず、−実高融点金属シリサイド
層８の厚さが大きすぎるとシリコン半導体基板１内に応
力が生ずるから、高融点金属シリサイド層８の厚さは５
００〜１ｏｏｏｏＸより好ましくは２０００〜４０００
Ａにするのが望ましい。また、遷移金属シリサイド層
６としては、パラジウム、白金、ニッケル等のシリサイ
ドを用いることかできる。そして、遷移金属シリサイド
層６の厚さが小さすぎるときには、均一な膜厚でかつピ
ンホール等欠陥のない遷移金属シリサイドを形成するこ
とができず、一方遷移金属シリサイド層乙の厚さが太き
すぎると、シリコン半導体基板１内に応力が生じ、不純
物拡散層２の接合を劣化させるとともに、遷移金属シリ
サイド形成時の上記反応中に消費されるＳｉ基板の厚さ
も大きく、不純物拡散層２の接合を破壊することもある
。このだめ、遷移金属シリサイド層乙の厚さは ２００
〜１ｏｏｏｏｘ、より好ましくは５００〜３０００Ｘ［
するのが望ましい。Note that if the thickness of the high melting point metal silicide layer 8 is too small, the reaction between the transition metal silicide layer 6 and the interconnection layer 5 cannot be effectively prevented, and - the actual thickness of the high melting point metal silicide layer 8 cannot be effectively prevented. If the thickness is too large, stress will be generated in the silicon semiconductor substrate 1, so the thickness of the high melting point metal silicide layer 8 is set to 5.
00-1ooooX, preferably 2000-4000
It is desirable to set it to A. Further, as the transition metal silicide layer 6, silicides such as palladium, platinum, nickel, etc. can be used. When the thickness of the transition metal silicide layer 6 is too small, it is not possible to form a transition metal silicide with a uniform thickness and without defects such as pinholes. If it is too high, stress will be generated in the silicon semiconductor substrate 1, which will deteriorate the bonding of the impurity diffused layer 2, and the thickness of the Si substrate consumed during the above reaction during the formation of transition metal silicide will be large, which will cause the bonding of the impurity diffused layer 2 to deteriorate. may also be destroyed. In this case, the thickness of the transition metal silicide layer B is 200
~1ooooox, more preferably 500-3000X [
It is desirable to do so.
つぎに、第４図に示したシリコン半導体装置を製造する
方法について説明する。まず、第５図（ａ）に示すよう
に、ｐ形のシリコン半導体基板１にｎ形の不純物拡散層
２を形成したのち、酸化シリコンからなる絶縁膜６でシ
リコン半導体基板１を覆う。つぎに、通常の写真食刻法
により、絶縁膜６に電極孔４を設ける。ついで、パラジ
ウム等の遷移金属膜９を被着し、２００℃以上の熱処理
を行なって、電極孔４部に遷移金属シリサイド層６を形
成したのち、遷移金属膜９を除去する。つぎに、第５図
（ｂ）に示すように、後に形成しようとする高融点金属
シリサイド層と同じ組成比を持った高融点金属とシリコ
ンとの混合膜をスパッタ法、蒸着法等によって形成した
のち、５００℃以上の熱処理を行なって、高融点金属シ
リサイド層８を形成する。ついで、アルミニウムとシリ
コンとの合金膜１０を形成する。最後に、・通常の写真
食刻法によシ合金膜１０を加工して配線層５を形成した
のち配線層５をマスクとして、ＣＦ４を主成分としたガ
スを用いたドライエツチング法により、高融点金属シリ
サイド層８を加工する。Next, a method for manufacturing the silicon semiconductor device shown in FIG. 4 will be described. First, as shown in FIG. 5(a), an n-type impurity diffusion layer 2 is formed on a p-type silicon semiconductor substrate 1, and then the silicon semiconductor substrate 1 is covered with an insulating film 6 made of silicon oxide. Next, electrode holes 4 are formed in the insulating film 6 by ordinary photolithography. Next, a transition metal film 9 such as palladium is deposited and heat treated at 200° C. or higher to form a transition metal silicide layer 6 in the electrode hole 4, and then the transition metal film 9 is removed. Next, as shown in FIG. 5(b), a mixed film of high melting point metal and silicon having the same composition ratio as the high melting point metal silicide layer to be formed later was formed by sputtering, vapor deposition, etc. Thereafter, heat treatment is performed at 500° C. or higher to form a high melting point metal silicide layer 8. Then, an alloy film 10 of aluminum and silicon is formed. Finally, the wiring layer 5 is formed by processing the silicon alloy film 10 using a normal photolithography method, and then, using the wiring layer 5 as a mask, a high-temperature etching process is performed using a dry etching method using a gas mainly composed of CF4. The melting point metal silicide layer 8 is processed.
なお、上述実施例においては、配線層５をアルミニウム
とシリコンの合金で形成したが、アルミニウム、金等の
低抵抗金属などを用いることができる。In the above embodiment, the wiring layer 5 is formed of an alloy of aluminum and silicon, but a low resistance metal such as aluminum or gold may be used.
以上説明したように、この発明に係るシリコン半導体装
置においては、高融点金属シリサイド層によシ遷移金属
シリサイド層と配線層との間の反応およびシリコン半導
体基板と配線層との間の相互拡散を抑制することができ
る。また、高融点金属シリサイド層とシリコン半導体基
板、遷移金属シリサイド層、配線層とが反応を起こすこ
とはなく、高融点金属シリサイド層と配線層との間の相
互拡散も生ずることはない。したがって、シリコン半導
体装置の信頼性および耐熱性を向上することが可能であ
る。このように、この発明の効果は顕著である。As explained above, in the silicon semiconductor device according to the present invention, the high melting point metal silicide layer prevents the reaction between the transition metal silicide layer and the wiring layer and the mutual diffusion between the silicon semiconductor substrate and the wiring layer. Can be suppressed. Furthermore, no reaction occurs between the high melting point metal silicide layer, the silicon semiconductor substrate, the transition metal silicide layer, and the wiring layer, and no mutual diffusion occurs between the high melting point metal silicide layer and the wiring layer. Therefore, it is possible to improve the reliability and heat resistance of the silicon semiconductor device. As described above, the effects of this invention are remarkable.
第１図ないし第６図はそれぞれ従来のシリコン半導体装
置を示す断面図、第４図はこの発明に係るシリコン半導
体装置を示す断面図、第５図は第４図に示したシリコン
半導体装置を製造する方法。
の説明図である。
１・・・シリコン半導体基板
３・・・絶縁膜
４・・・電極孔
５・・・配線層
６・・・遷移金属シリサイド層
８・・・高融点金属シリサイド層
）ＰｌｖＡ
？２図
ｉ３図
１１Ｆ４図
１Ｆ５図
第１頁の続き
０発 明 者 斉田広二
国分寺市東恋ケ窪−丁目２８０番
地株式会社日立製作所中央研究
所内1 to 6 are cross-sectional views showing conventional silicon semiconductor devices, FIG. 4 is a cross-sectional view showing a silicon semiconductor device according to the present invention, and FIG. 5 is a fabrication of the silicon semiconductor device shown in FIG. 4. how to. FIG. 1...Silicon semiconductor substrate 3...Insulating film 4...Electrode hole 5...Wiring layer 6...Transition metal silicide layer 8...High melting point metal silicide layer) PlvA? Figure 2 i3 Figure 11F4 Figure 1F5 Continued from Figure 1 page 0 Inventor: Koji Saita 280 Higashi Koigakubo-chome, Kokubunji City, Hitachi, Ltd. Central Research Laboratory
Claims (1)
シリコン半導体装置において、上記電極孔部の上記シリ
コン半導体基板の上に形成された遷移金属シリサイド層
と、その遷移金属シリサイド層の上に形成された、上記
遷移金属シリサイドの金属と異なる金属の高融点金属シ
リサイド層とその高融点金属シリサイド層の上に形成さ
れた配線層とを具備することを特徴とするシリコン半導
体装置。In a silicon semiconductor device in which a silicon semiconductor substrate is covered with an insulating film having an electrode hole, a transition metal silicide layer formed on the silicon semiconductor substrate in the electrode hole portion, and a transition metal silicide layer formed on the transition metal silicide layer. Further, a silicon semiconductor device comprising a refractory metal silicide layer made of a metal different from the metal of the transition metal silicide, and a wiring layer formed on the refractory metal silicide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10168183A JPS59227119A (en) | 1983-06-09 | 1983-06-09 | Silicon semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10168183A JPS59227119A (en) | 1983-06-09 | 1983-06-09 | Silicon semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59227119A true JPS59227119A (en) | 1984-12-20 |
Family
ID=14307084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10168183A Pending JPS59227119A (en) | 1983-06-09 | 1983-06-09 | Silicon semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59227119A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6437011A (en) * | 1987-07-31 | 1989-02-07 | Nec Corp | Manufacture of semiconductor integrated circuit |
| US5041394A (en) * | 1989-09-11 | 1991-08-20 | Texas Instruments Incorporated | Method for forming protective barrier on silicided regions |
| US5371041A (en) * | 1988-02-11 | 1994-12-06 | Sgs-Thomson Microelectronics, Inc. | Method for forming a contact/VIA |
-
1983
- 1983-06-09 JP JP10168183A patent/JPS59227119A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6437011A (en) * | 1987-07-31 | 1989-02-07 | Nec Corp | Manufacture of semiconductor integrated circuit |
| US5371041A (en) * | 1988-02-11 | 1994-12-06 | Sgs-Thomson Microelectronics, Inc. | Method for forming a contact/VIA |
| US5041394A (en) * | 1989-09-11 | 1991-08-20 | Texas Instruments Incorporated | Method for forming protective barrier on silicided regions |
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