JPS592251A - Cylinder motor control circuit of video tape recorder - Google Patents
Cylinder motor control circuit of video tape recorderInfo
- Publication number
- JPS592251A JPS592251A JP57110418A JP11041882A JPS592251A JP S592251 A JPS592251 A JP S592251A JP 57110418 A JP57110418 A JP 57110418A JP 11041882 A JP11041882 A JP 11041882A JP S592251 A JPS592251 A JP S592251A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- circuit
- terminal
- cylinder motor
- control voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B15/00—Driving, starting or stopping record carriers of filamentary or web form; Driving both such record carriers and heads; Guiding such record carriers or containers therefor; Control thereof; Control of operating function
- G11B15/18—Driving; Starting; Stopping; Arrangements for control or regulation thereof
- G11B15/1808—Driving of both record carrier and head
Abstract
Description
【発明の詳細な説明】
本発明はビデオテープレコーダのシリンダモータ制御回
路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cylinder motor control circuit for a video tape recorder.
可変速再生が可能なビデオテープレコーダにおいては、
いわゆるスロー再生やＮ（ｉ数）倍速等の特殊再生時に
は標準再生時に対して水平同期の時間がずれるので、シ
リンダの回転数ヲ笈化させる必要かめる。このため、従
来では一般的に位相制御電圧を変化させてシリンダの回
転数を変化させている。ところが従来では特殊再生から
標準角化に復帰する際にサーボ系が暴れるので、急速に
復帰させることができなかった。In video tape recorders capable of variable speed playback,
During so-called slow playback or special playback such as N (i number) times the speed, the horizontal synchronization time deviates from that during standard playback, so it is necessary to increase the rotational speed of the cylinder. For this reason, conventionally, the rotation speed of the cylinder is generally changed by changing the phase control voltage. However, in the past, the servo system went wild when returning from special regeneration to standard keratinization, making it impossible to return to standard keratinization quickly.
本発明は、上述の技術的課題を解決し、特殊再生から標
準再生への復帰時にサーボ系が暴れることを防止して、
急速な復帰を可能としたシリンダモータ制御回路を提供
することを目的とする。The present invention solves the above-mentioned technical problems and prevents the servo system from going wild when returning from special playback to standard playback.
The object of the present invention is to provide a cylinder motor control circuit that enables rapid recovery.
以下、図面によって本発明の実′ｈ１！１例を説明する
０図面は本発明の一実施例の簡略化した回路図でるる。Hereinafter, an embodiment of the present invention will be explained with reference to the drawings. The drawing is a simplified circuit diagram of an embodiment of the present invention.
シリンダモータ１には、たとえはシリンダモ−り１の回
転数を検出するための磁気ヘッドと磁極とが設けられる
。この磁気ヘッドから処理回路２には、シリンダモータ
１の周波数検出信号（図面ではＦＧと略称する）と、位
相検出信号（瞳面ではＰ’Ｇと略称する）とが与えられ
る。また処理回路２には、基準信号が与えられる。The cylinder motor 1 is provided with a magnetic head and magnetic poles for detecting the number of rotations of the cylinder motor 1, for example. A frequency detection signal (abbreviated as FG in the drawing) and a phase detection signal (abbreviated as P'G in the pupil plane) of the cylinder motor 1 are supplied from this magnetic head to the processing circuit 2. Further, the processing circuit 2 is supplied with a reference signal.
処理回路２は、位相制御電圧端子ＥＰＧ、周波数制御電
圧端子ＦＧＣおよび出力端子ＯＵＴが備えられる。周波
数制御電圧端子Ｆ、ＧＯは、コンデンサＯＬ’に介して
接地でれる。また、この周波数制御端子ＦＧＯは可変抵
抗Ｒ１を介して電源供給端子３に接続される。出力端子
ＯＵＴはドライバ回Ｍ１２を介してシリンダモータＩＫ
接続される。The processing circuit 2 includes a phase control voltage terminal EPG, a frequency control voltage terminal FGC, and an output terminal OUT. Frequency control voltage terminals F and GO are grounded via capacitor OL'. Further, this frequency control terminal FGO is connected to the power supply terminal 3 via a variable resistor R1. The output terminal OUT is connected to the cylinder motor IK via the driver circuit M12.
Connected.
位相制御電圧端子ＫＥＧおよび接地間には、抵抗Ｒ２，
Ｒ３およびコンデンサＣ２から成る時定数回路４が接続
される。抵抗Ｒ２，Ｒ３の接続点５は、抵抗Ｒ４？介し
て接地式れる。また接続点５は、抵抗Ｒ５全介して、可
変抵抗Ｒ１および周波数制御電圧端子ＦＧＯの接続点６
に接続烙れる。A resistor R2,
A time constant circuit 4 consisting of R3 and capacitor C2 is connected. Connection point 5 between resistors R2 and R3 is resistor R4? Grounded via. Further, the connection point 5 is connected to the connection point 6 of the variable resistor R1 and the frequency control voltage terminal FGO through the resistor R5.
Connected to.
本発明に従えば、位相制御電圧端子ＥＰＧから周波数制
御電圧端子ＦＧＯに至る回路の途中、たとえば接続点５
および抵抗Ｒ５間に、第ｌおよび第２ト２ンジスタＴＲ
Ｉ、ＴＲ２から成るエミッタフォロワー回路７が接続さ
れる。すなわち、接続点５および抵抗Ｒ５間の接続点８
に第１トランジスタＴＲＩおよび第２トランジスタＴＲ
２が直列接続きれる。According to the present invention, in the middle of the circuit from the phase control voltage terminal EPG to the frequency control voltage terminal FGO, for example, at the connection point 5.
and resistor R5, the first and second transistors TR
An emitter follower circuit 7 consisting of I and TR2 is connected. That is, the connection point 8 between the connection point 5 and the resistor R5
the first transistor TRI and the second transistor TR
2 can be connected in series.
第１トランジスタＴＲＩはＮＰＮ）ランジスタでりり、
男２トランジスタＴＲ２はＰＮＰ ）ランジスタでめる
。第１トランジヌタＴＲＩのベースには、抵抗Ｒ６を介
して制御端子９が接続される。The first transistor TRI is an NPN) transistor,
The male 2 transistor TR2 is a PNP transistor. A control terminal 9 is connected to the base of the first transistor TRI via a resistor R6.
第２トランジスタＴＲ２のベースには一対のダイオード
ＤＩ、Ｄ２が並列に接続される０ダイオードＤＩ、Ｄ２
および第２トランジスタＴＲ２のベース間は抵抗Ｒ７ｉ
介して接地でれる。ダイオードＤＩに関して設けられた
制御端子ｌＯは可変抵抗Ｒ８全介して接地され、ダイオ
ードＤ２に関して設けられた制御端子１１ ｉ、ｉ：
ｌ’Ｊ笈抵抗Ｒ９全介し ：て接地式れる。ダイオー
ドＤｉは可変抵ｐＬＲ８に接続され、ダイオードＤ２は
可変抵抗Ｒ９に接続される。A pair of diodes DI, D2 are connected in parallel to the base of the second transistor TR2.
and a resistor R7i between the bases of the second transistor TR2
It can be grounded through. The control terminal lO provided for the diode DI is grounded through the variable resistor R8, and the control terminal 11 i, i provided for the diode D2:
l'J - All through resistor R9: Grounded. Diode Di is connected to variable resistor pLR8, and diode D2 is connected to variable resistor R9.
ｆｌＩＩＪ御端子９には、標準再生時のＮ（振数）倍速
の特殊再生時において、止・逆にかかわらすハイレベル
の信号か与えられる。したがって、ｉｉ）ランジスメＴ
ＲＩはＮ倍速時においてＯＮする。A high level signal is applied to the flIIJ control terminal 9, regardless of whether the signal is stopped or reversed, during special playback at a speed N (frequency) times that of standard playback. Therefore, ii) RunjismeT
RI is turned ON at N times speed.
制御端子ｌＯには、たとえばＮ倍速の正転時にハイレベ
ルの信号が与えられ、制御ｙ−子１１には、たとえばＮ
倍速の逆転時にハイレベルの信号が与えられる。A high level signal is given to the control terminal lO during normal rotation at N times the speed, for example, and a high level signal is given to the control terminal 11, for example
A high level signal is given when the speed is reversed.
このようにすると、特殊再生時には、第１トランジスタ
ＴＲＩはＯＮ状態となり、接続点８には、第２トランジ
スタＴＲ２のエミッタ電圧が加えられることになる。し
かも抵抗Ｒ２，Ｒ３，Ｒ４゜Ｒ５の回路系のインピーダ
ンスは旨いので、はとんど動作しない。In this way, during special reproduction, the first transistor TRI is turned on, and the emitter voltage of the second transistor TR2 is applied to the connection point 8. Moreover, since the impedance of the circuit system of resistors R2, R3, R4 and R5 is good, it rarely operates.
また可変抵抗Ｒ８，Ｒ９の抵抗値を適宜設定することに
より、Ｎ倍速萌の正方向および逆方向に応じて、第２ト
ランジスタＴＲ２のエミッタ電圧を変化させることかで
きる。したかつて１．正方向の場合にはシリンダの回転
速１に早くシ、逆方向の場合にはシリンダの回転速度を
遅くすることがｎ」能となる。Furthermore, by appropriately setting the resistance values of the variable resistors R8 and R9, it is possible to change the emitter voltage of the second transistor TR2 depending on the forward direction and reverse direction of the N-times speed moe. Once upon a time 1. In the case of the forward direction, the rotation speed of the cylinder can be increased to 1, and in the case of the reverse direction, the rotation speed of the cylinder can be decreased.
このようにして、抵抗Ｒ２〜Ｒ４の回路系をほとんど動
作嘔せることなしに、外部から６望の電圧を印加するこ
とができ、％殊再生から標準再生に復帰する際に、思違
復帰することが可能となる。In this way, it is possible to apply a desired voltage from the outside without significantly affecting the circuit system of resistors R2 to R4, and when returning from special playback to standard playback, false recovery may occur. becomes possible.
なお、複数の特殊再生モードかめる場合には、第２トラ
ンジスタＴＲ２のベースに、各モードに対応した電圧全
印加しうるようにダイオードマトリクスを構成すれはよ
い。In addition, when a plurality of special reproduction modes are available, it is preferable to configure a diode matrix so that all the voltages corresponding to each mode can be applied to the base of the second transistor TR2.
上述のごとく本発明によれば、特殊再生から標準再生へ
の復帰全急速に行なうことができるようになる。As described above, according to the present invention, it is possible to quickly return from special playback to standard playback.
【図面の簡単な説明】
図面は本発明の一実施例の簡略化した回路図でろるＯ
１・・・シリンダモータ、２・・・処理回路、７・・・
エミッタフォロワー回路、９，１０．１１・・・制御端
子、ＴＲＩ・・・第１トランジスタ、ＴＲ２・・・ｍ２
トラ７ジスタ、Ｒ８，Ｒ９・・・可変抵抗、Ｄｌ、Ｄ２
・・・ダイオード、］ｌ８ＰＧ・・・位相制御電圧端子
、ＦＧＯ・・・周波数制御％ｆｔ端子
代理人 弁理士 西教圭一部[Brief Description of the Drawings] The drawing is a simplified circuit diagram of an embodiment of the present invention. 1... Cylinder motor, 2... Processing circuit, 7...
Emitter follower circuit, 9, 10.11...control terminal, TRI...first transistor, TR2...m2
7 transistors, R8, R9...variable resistors, Dl, D2
...Diode, ]l8PG...Phase control voltage terminal, FGO...Frequency control %ft terminal Agent Patent attorney Kei Nishi
Claims (1)
位相制御電圧および周波数制御電圧によってシリンダモ
ータ全制御する信号を出力する処理回路を備えるビデオ
テープレコーダのシリンダモータ開側１回路において、 前記処理回路の位相制御電圧端子および周波数制御電圧
ν１ｍｌ子を連絡する回路の途中に、スイッチング動作
ケする第１トランジスタと、エミッタフォロワーとなる
第２トランジスタとが直列接続され、第１トランジスタ
のベースには特殊再生時にハイレベルとなる制御端子が
接続烙れ、第２トランジスタのペースには、特殊角化時
の正逆走行方間に応じた少なくとも一対の制御端子が、
可変抵すしおよびダイオードを個別に弁じて並列に、接
続ちれることを％徴とするビデオテープレコータノシリ
ンダモーメ制御回路。[Claims] One cylinder motor open side circuit of a video tape recorder, which includes a processing circuit that outputs a signal for fully controlling the cylinder motor using a phase control voltage and a frequency control voltage according to a phase detection signal, a frequency detection signal, and a reference signal. In this case, a first transistor that performs a switching operation and a second transistor that serves as an emitter follower are connected in series in the middle of a circuit that connects the phase control voltage terminal and the frequency control voltage ν1ml of the processing circuit. A control terminal that becomes high level during special playback is connected to the base, and at least a pair of control terminals that correspond to the forward and reverse running direction during special angulation are connected to the pace of the second transistor.
A video tape recorder cylinder motor control circuit whose characteristics include connecting a variable resistor and a diode in parallel with individual valves.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57110418A JPS592251A (en) | 1982-06-25 | 1982-06-25 | Cylinder motor control circuit of video tape recorder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57110418A JPS592251A (en) | 1982-06-25 | 1982-06-25 | Cylinder motor control circuit of video tape recorder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS592251A true JPS592251A (en) | 1984-01-07 |
Family
ID=14535257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57110418A Pending JPS592251A (en) | 1982-06-25 | 1982-06-25 | Cylinder motor control circuit of video tape recorder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS592251A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0176276A2 (en) * | 1984-09-20 | 1986-04-02 | Ampex Corporation | A multiple speed scanner servo system for protecting the heads and tape of helical recorders |
| JPS62205736A (en) * | 1986-03-05 | 1987-09-10 | Meiji Milk Prod Co Ltd | Production of jellified milk |
-
1982
- 1982-06-25 JP JP57110418A patent/JPS592251A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0176276A2 (en) * | 1984-09-20 | 1986-04-02 | Ampex Corporation | A multiple speed scanner servo system for protecting the heads and tape of helical recorders |
| JPS62205736A (en) * | 1986-03-05 | 1987-09-10 | Meiji Milk Prod Co Ltd | Production of jellified milk |
| JPH0119855B2 (en) * | 1986-03-05 | 1989-04-13 | Meiji Milk Prod Co Ltd |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1192257A (en) | Brushless dc motor driving circuit | |
| US3997823A (en) | Brushless DC motor driving circuit | |
| GB2103034A (en) | Brushless DC motor control system | |
| US4476421A (en) | Stepper motor exciting circuit | |
| JPS592251A (en) | Cylinder motor control circuit of video tape recorder | |
| US4516060A (en) | Digital motor speed control | |
| US4514668A (en) | D.C. Motor driving circuit | |
| JPH0731632Y2 (en) | Controllable divider circuit | |
| US4577243A (en) | Control signal generating circuit for a magnetic recording and/or reproducing apparatus | |
| KR910001826Y1 (en) | Tracking control circuit of picture signal recording and play back device | |
| KR880001385Y1 (en) | Double deck cassette | |
| JPH064432Y2 (en) | Magnetic recording / reproducing device | |
| JP2629199B2 (en) | Forward and reverse rotation device for DC motor | |
| JPH0134433B2 (en) | ||
| JPH0727836Y2 (en) | Motor drive circuit | |
| JP3009721B2 (en) | Electric governor motor control circuit | |
| KR900001501Y1 (en) | Stop mode control circuit of video tape recorder | |
| JPS6156709B2 (en) | ||
| KR890001029Y1 (en) | Continuous reproducing circuit of tape recorder | |
| JPS6017956Y2 (en) | switching circuit | |
| JPH0116395Y2 (en) | ||
| JPS6211198Y2 (en) | ||
| KR870004182Y1 (en) | Devices for continuous reproduction | |
| JPS6311080A (en) | Controller of dc motor | |
| JPH0216433Y2 (en) |