JPS59222954A - Laminated semiconductor integrated circuit and manufacture therrof - Google Patents

Laminated semiconductor integrated circuit and manufacture therrof

Info

Publication number
JPS59222954A
JPS59222954A JP58095729A JP9572983A JPS59222954A JP S59222954 A JPS59222954 A JP S59222954A JP 58095729 A JP58095729 A JP 58095729A JP 9572983 A JP9572983 A JP 9572983A JP S59222954 A JPS59222954 A JP S59222954A
Authority
JP
Japan
Prior art keywords
chip
solder
integrated circuit
semiconductor integrated
substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58095729A
Other languages
Japanese (ja)
Inventor
Mitsunori Ketsusako
光紀 蕨迫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58095729A priority Critical patent/JPS59222954A/en
Publication of JPS59222954A publication Critical patent/JPS59222954A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To enable to reduce the chip-to-chip wiring length and to contrive to enhance the mounting density by a method wherein the connection parts of active substrates are constituted of solder pads and interposing solder layers, which respectively oppose to each other, and a penetrating hole, whose inner surface has been coated with an insulating film and a conductive film, is provided on at least one side of the solder pads. CONSTITUTION:Groups of elements have been provided in the surfaces of chips 31 and 31' by selectively performing a doping and chip penetrating holes 32 and 32', etc., have been provided piercing through parts of the groups. Insulating films 33 and 33', such as an oxide film, etc., have been provided at the surfaces of the penetrating holes 32 and 32', and moreover, conductive coatings 34 and 34', which are provided at the upper parts thereof, and the substrates have been electrically separated. Solder bumps 35 and 35', which are used for connection with other chips, have been formed at the upper parts of wiring layers and the bump 35' of the lower chip has been provided opposite right to the bonding pad 34 having been extendedly provided from the opening part of the upper chip.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体集積回路チップを積層して成る半導体集
積回路およびその製法に係る。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit formed by stacking semiconductor integrated circuit chips and a method for manufacturing the same.

〔発明の背景〕[Background of the invention]

電子計算機のような高度な電子回路システムは従来半導
体高密度集積回路（ＬＳ　Ｉ　）のパッケージを単位と
し、これが多数、プリント配線基板上に配列され実装さ
れて構成されていた。さらに進んだシステムでは、第１
図に例示する如き複チップモジュールを構成し、配線長
を短縮して集積度の向上を図るとともに配線遅延を短縮
して高速化が図られていた。第１図に示す複チップモジ
ュールでは、各ＬＳＩチップ１１．１１’　、１１“は
素下層１２を下向きにし、チップの周縁部に設けられた
ポンディングパッド１３を、多層配線セラミック基板１
４の上に設けられたポンプイングツくラド１５に対向さ
せ、公知のフェースダウンボンディング技術により接続
されている。2. Description of the Related Art Advanced electronic circuit systems such as electronic computers have conventionally been constructed using semiconductor high-density integrated circuit (LSI) packages as units, and a large number of these packages are arranged and mounted on a printed wiring board. In more advanced systems, the first
A multi-chip module as exemplified in the figure was constructed, and the wiring length was shortened to improve the degree of integration, and the wiring delay was shortened to increase the speed. In the multi-chip module shown in FIG. 1, each LSI chip 11, 11', 11'' has its underlying layer 12 facing downward, and the bonding pad 13 provided on the periphery of the chip is connected to the multilayer wiring ceramic substrate 11.
The pumping rod 15 provided on the pump 4 faces the pump rad 15, and is connected by a known face-down bonding technique.

この複チップモジュールでは、ボンディングのための細
線は不要であり、各チップは半田により多層配線基板に
固定され、実装密度、システムの信頼性等多くの利点が
実現されていた。This multi-chip module does not require thin wires for bonding, and each chip is fixed to the multilayer wiring board by solder, achieving many advantages such as packaging density and system reliability.

しかし、従来の実装法は、完成したチップから出発して
おり、ポンディングパッドは各チップの周縁部のみに設
けられ、チップ間の接続は多層配線基板を介してのみ実
現されていたため、配線長の短縮にも限界があった。However, conventional mounting methods start from a completed chip, bonding pads are provided only at the periphery of each chip, and connections between chips are only realized through a multilayer wiring board, which results in long wiring lengths. There were limits to the shortening of the term.

〔発明の目的〕[Purpose of the invention]

本発明は、かかる従来実装技術の限界を超えてチップ間
配線長の短縮を可能とし、さらに高い実装密度を実現す
る新規な集積回路及びその製造方法を提供することを目
的とする。It is an object of the present invention to provide a novel integrated circuit and its manufacturing method that enables shortening of inter-chip interconnection lengths beyond the limitations of conventional packaging techniques and achieves higher packaging density.

〔発明の概要〕[Summary of the invention]

本発明は、基本的には第２図に示す如き、チップ積層に
よる高密度実装技術に係る。第２図で例示した構成では
、チップ２１．２１’　、２１“等の片面に素子群の形
成された層２２．２２’　。The present invention basically relates to high-density packaging technology using chip stacking as shown in FIG. In the configuration illustrated in FIG. 2, a layer 22, 22' on which a group of elements is formed is formed on one side of the chips 21, 21', 21'', etc.

２２“等が設けられ、素子層２２の上に設けられたポン
ディングパッド２３と、チップ２１′の裏面に設けられ
たポンディングパッド２４とが接続され、順次チップが
積層・接続されて基板２５にマウントされている。勿論
基板２５は第１図に示した如き多層配線基板であって良
く、また、積層は基板上の複数の位置でなされて差しつ
かえない。22'' etc. are provided, and a bonding pad 23 provided on the element layer 22 and a bonding pad 24 provided on the back surface of the chip 21' are connected, and the chips are sequentially stacked and connected to form a substrate 25. Of course, the board 25 may be a multilayer wiring board as shown in FIG. 1, and the lamination may be done at multiple locations on the board.

本発明により積層構造を構成するためにはチップの表“
面に形成した素子と、チップ裏面に形成したポンディン
グパッドとを接続するためのチップ貫通配線と、チップ
同士を接続するための方法が必要であり、以下実施例に
従ってこれを説明する。In order to construct a laminated structure according to the present invention, it is necessary to
Chip-through wiring for connecting elements formed on the front surface and bonding pads formed on the back surface of the chip and a method for connecting the chips to each other are required, and this will be explained below with reference to examples.

〔発明の実施例〕[Embodiments of the invention]

第３図は本発明によるチップ接続を行なう直前の接続部
素子断面の一例である。チップ３１および３１′の表面
には選択ドーピングにより素子群が設けられており、そ
の一部にはチップ貫通孔３２．３２’等が設けられてい
る。貫通孔３２゜３２′の表面は酸化膜等による絶縁膜
３３．３３’が設けられ、さらにその上部に設けられる
導電性被膜３４．３４’と基板とを電気的に分離してい
る。FIG. 3 is an example of a cross section of a connecting element immediately before chip connecting according to the present invention. Element groups are provided on the surfaces of the chips 31 and 31' by selective doping, and chip through holes 32, 32', etc. are provided in some of the elements. An insulating film 33, 33' made of an oxide film or the like is provided on the surface of the through hole 32, 32', and further electrically isolates a conductive film 34, 34' provided above the insulating film 34, 33' from the substrate.

配線層の上部には他のチップとの接続に用いられる半田
バンプ３５．３５’が形成されており、下層チップのバ
ンブ３５′は上層チップの開孔部から延在するポンディ
ングパッド３４に正対して設けられている。Solder bumps 35 and 35' used for connection with other chips are formed on the upper part of the wiring layer, and the bumps 35' of the lower chip are directly connected to the bonding pads 34 extending from the openings of the upper chip. It is set up against.

第３図に示した構造は第４図の如き回路と対応しており
、チップを接続することにより、論理回路の一部が構成
される。この論理回路の入力の一部、例えばＡには、さ
らに上層のチップの出力が受けられる構造となっており
、チップ間に亘る配線が第１図に示すような外部配線体
を用いる場合に比べ短縮されるのが理解できよう。The structure shown in FIG. 3 corresponds to the circuit shown in FIG. 4, and by connecting chips, a part of a logic circuit is constructed. Some of the inputs of this logic circuit, for example, A, have a structure that allows them to receive outputs from chips in the upper layer, and the wiring between chips is simpler than when using an external wiring body as shown in Figure 1. I can understand why it is shortened.

この実施例に示される半田パンプの大きさは、２０μｍ
径程度であり、これは多層配線の施されたチップに存在
する凹凸段差より十分大きく、またチップの反りを考慮
しても、半田の溶解時にはチップ上の全バンプがそれぞ
れ対向するポンディングパッドに接触できる。The size of the solder pump shown in this example is 20 μm.
This is sufficiently larger than the uneven steps that exist on a chip with multilayer wiring, and even considering the warping of the chip, when the solder melts, all bumps on the chip reach the opposing bonding pads. Can be contacted.

チップの接続は半田の溶解温度での熱圧接により実現さ
れる。この場合、ポンディングパッドが平坦であると、
各ポンディングパッドの蔦低差によシ、半田のポンディ
ングパッドからの圧し出しによる短絡が生ずることがあ
り、特にポンディングパッドの数が多い場合には集積素
子の歩留り上好ましくない。実施例によるポンディング
パッドに設けられた貫通孔は、チップ接続時に重要な役
割を演する。すなわち、リフロ一時に接続に必要とする
以外の半田を貫通孔内に吸収するため、圧接時に半田が
ポンディングパッドよシはみ出ることが少ない。この効
果は減圧環境下で行なうことが必要であり、また、貫通
孔の内容積が、半田パンプの体積よシも大きくなければ
ならない。Chip connections are realized by thermocompression welding at the melting temperature of the solder. In this case, if the pounding pad is flat,
Due to the difference in the height of the ridges of each bonding pad, a short circuit may occur due to solder being squeezed out from the bonding pads, which is unfavorable from the viewpoint of the yield of integrated devices, especially when there are a large number of bonding pads. The through hole provided in the bonding pad according to the embodiment plays an important role during chip connection. That is, since solder other than that required for connection is absorbed into the through hole during reflow, solder is less likely to protrude beyond the bonding pad during pressure bonding. This effect must be achieved under a reduced pressure environment, and the internal volume of the through hole must be larger than the volume of the solder pump.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明によれば、多数のチツブを積
層して実装密度を飛躍的に向上させることがでさる他、
従来のチップ周縁部にのみポンディングパッドを設けた
フェースダウンボンディング法に比べて、チップ内の領
域に多数の接続点を設けることが可能となり、また、配
線長を短縮できるため、総合的なシステム速度を向上さ
せることができる。As explained above, according to the present invention, in addition to being able to dramatically improve the packaging density by stacking a large number of chips,
Compared to the conventional face-down bonding method in which bonding pads are provided only on the periphery of the chip, it is possible to provide a large number of connection points in the area within the chip, and the wiring length can be shortened, making it possible to create a comprehensive system. Speed can be improved.

また、上記実施例では簡単なＭＯ８型素子を用いて説明
したが、各チップの導電形を変えて相補形の溝成とした
り、また、センサチップ、論理チップ、メモリチップ等
チップ毎に異なる機能を有するものを積層し、高度の複
合処理を実現することも可能である。In addition, although the above embodiment has been explained using a simple MO8 type element, it is also possible to change the conductivity type of each chip to form complementary grooves, or to have different functions for each chip such as a sensor chip, a logic chip, a memory chip, etc. It is also possible to realize advanced composite processing by stacking materials with .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の複チップモジュールの断面構造を示す模
式図、第２図は本発明の概念を示す断面構造図、第３図
は本発明の一実施例を示す接続部の素子断面図、第４図
はこれに対応する等価回路を示す図である。 ２１．２１’・・・チップ、２２．２２’　・・・素子
層、２３・・・表面ポンディングパッド、２４・・・裏
面ポンディングパッド、３１．３１’・・・チップ、３
２゜第１図 不２図 介　３　何 不　４　図FIG. 1 is a schematic diagram showing a cross-sectional structure of a conventional multi-chip module, FIG. 2 is a cross-sectional diagram showing the concept of the present invention, and FIG. 3 is a cross-sectional view of an element of a connecting part showing an embodiment of the present invention. FIG. 4 is a diagram showing an equivalent circuit corresponding to this. 21.21'...Chip, 22.22'...Element layer, 23...Surface bonding pad, 24...Back surface bonding pad, 31.31'...Chip, 3
2゜Figure 1, figure 2, figure 3, figure 4

Claims (1)

【特許請求の範囲】 １、半導体基板の少くとも一主面上に素子群が形成され
た能動基板を少くとも２以上積層して成る集積回路にお
いて、該能動基板の接続部は対向する半田パッド及び介
在半田層により構成され、かつ該半田パッドの少くとも
一方に内面が絶縁膜及び導電膜により被覆された貫通孔
を有することを特徴とする積層半導体集積回路。 ２、半導体基板の一主面に半田パッド及び半田バンプを
有し、他の主面に内面が絶縁膜及び導電膜により被覆さ
れた貫通孔を設けた半田受容パッドを有する能動基板を
構成要素とし、上記構成の基板を単位として複数積層し
て成る盤ｉ胱＃５ｔ＝ｙｊ＃；ｆ；ｔｙ！彫積層半導体
集積回路の製造方法。 ３、半田バンプの半田層の高さは能動基板の平坦度より
大であり、かつ貫通孔の内容積は上記半田層の体積より
大である如く形成された能動基板を用いることを特徴と
する特許請求の範囲第２項記載の積層半導体集積回路の
製法。 ４、能動基板の積層を減圧環境下での加熱により行なう
特許請求の範囲第２項記載の積層半導体集積回路の製法
。[Claims] 1. In an integrated circuit formed by laminating at least two active substrates each having a group of elements formed on at least one main surface of a semiconductor substrate, the connection portion of the active substrate is connected to an opposing solder pad. and an intervening solder layer, and at least one of the solder pads has a through hole whose inner surface is covered with an insulating film and a conductive film. 2. An active substrate having solder pads and solder bumps on one main surface of a semiconductor substrate, and a solder receiving pad with a through hole whose inner surface is covered with an insulating film and a conductive film on the other main surface. , a board made by laminating a plurality of substrates with the above configuration as a unit #5t=yj#;f;ty! A method for manufacturing a carved laminated semiconductor integrated circuit. 3. The active substrate is characterized in that the height of the solder layer of the solder bump is larger than the flatness of the active substrate, and the internal volume of the through hole is larger than the volume of the solder layer. A method for manufacturing a laminated semiconductor integrated circuit according to claim 2. 4. A method for manufacturing a laminated semiconductor integrated circuit according to claim 2, wherein the active substrates are laminated by heating in a reduced pressure environment.
JP58095729A 1983-06-01 1983-06-01 Laminated semiconductor integrated circuit and manufacture therrof Pending JPS59222954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58095729A JPS59222954A (en) 1983-06-01 1983-06-01 Laminated semiconductor integrated circuit and manufacture therrof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58095729A JPS59222954A (en) 1983-06-01 1983-06-01 Laminated semiconductor integrated circuit and manufacture therrof

Publications (1)

Publication Number Publication Date
JPS59222954A true JPS59222954A (en) 1984-12-14

Family

ID=14145561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58095729A Pending JPS59222954A (en) 1983-06-01 1983-06-01 Laminated semiconductor integrated circuit and manufacture therrof

Country Status (1)

Country Link
JP (1) JPS59222954A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02303043A (en) * 1989-04-26 1990-12-17 Commiss Energ Atom Method and machine for connecting electric parts by welding member
US5463246A (en) * 1988-12-29 1995-10-31 Sharp Kabushiki Kaisha Large scale high density semiconductor apparatus
WO1998048455A1 (en) * 1997-04-21 1998-10-29 Seiko Epson Corporation Interelectrode connecting structure, interelectrode connecting method, semiconductor device, semiconductor mounting method, liquid crystal device, and electronic equipment
FR2767223A1 (en) * 1997-08-06 1999-02-12 Commissariat Energie Atomique INTERCONNECTION METHOD THROUGH SEMICONDUCTOR MATERIAL, AND DEVICE OBTAINED
US6667551B2 (en) 2000-01-21 2003-12-23 Seiko Epson Corporation Semiconductor device and manufacturing thereof, including a through-hole with a wider intermediate cavity
EP1439576A2 (en) 2003-01-15 2004-07-21 Shinko Electric Industries Co., Ltd. Through hole manufacturing method
WO2005093827A1 (en) * 2004-03-26 2005-10-06 Fujikura Ltd. Through wiring board and method for producing the same
US7119428B2 (en) 2004-03-01 2006-10-10 Hitachi, Ltd. Semiconductor device
JP2007251188A (en) * 2007-04-27 2007-09-27 Rohm Co Ltd Semiconductor device
US7276738B2 (en) 2000-07-11 2007-10-02 Seiko Epson Corporation Miniature optical element for wireless bonding in an electronic instrument
WO2007135763A1 (en) * 2006-05-19 2007-11-29 Casio Computer Co., Ltd. Semiconductor device having low dielectric insulating film and manufacturing method of the same
US7714425B2 (en) 2007-10-04 2010-05-11 Elpida Memory, Inc. Semiconductor device, method for manufacturing the same, and flexible substrate for mounting semiconductor
US8154133B2 (en) 2008-03-31 2012-04-10 Casio Computer Co., Ltd. Semiconductor device having low dielectric constant film and manufacturing method thereof
US8587124B2 (en) 2007-09-21 2013-11-19 Teramikros, Inc. Semiconductor device having low dielectric insulating film and manufacturing method of the same

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463246A (en) * 1988-12-29 1995-10-31 Sharp Kabushiki Kaisha Large scale high density semiconductor apparatus
JPH02303043A (en) * 1989-04-26 1990-12-17 Commiss Energ Atom Method and machine for connecting electric parts by welding member
WO1998048455A1 (en) * 1997-04-21 1998-10-29 Seiko Epson Corporation Interelectrode connecting structure, interelectrode connecting method, semiconductor device, semiconductor mounting method, liquid crystal device, and electronic equipment
US6357111B1 (en) 1997-04-21 2002-03-19 Seiko Epson Corporation Inter-electrode connection structure, inter-electrode connection method, semiconductor device, semiconductor mounting method, liquid crystal device, and electronic apparatus
FR2767223A1 (en) * 1997-08-06 1999-02-12 Commissariat Energie Atomique INTERCONNECTION METHOD THROUGH SEMICONDUCTOR MATERIAL, AND DEVICE OBTAINED
WO1999008318A1 (en) * 1997-08-06 1999-02-18 Commissariat A L'energie Atomique Method for producing an interconnection path through a semiconductor material
US6667551B2 (en) 2000-01-21 2003-12-23 Seiko Epson Corporation Semiconductor device and manufacturing thereof, including a through-hole with a wider intermediate cavity
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