JP2871636B2 - LSI module and manufacturing method thereof - Google Patents
LSI module and manufacturing method thereofInfo
- Publication number
- JP2871636B2 JP2871636B2 JP31946696A JP31946696A JP2871636B2 JP 2871636 B2 JP2871636 B2 JP 2871636B2 JP 31946696 A JP31946696 A JP 31946696A JP 31946696 A JP31946696 A JP 31946696A JP 2871636 B2 JP2871636 B2 JP 2871636B2
- Authority
- JP
- Japan
- Prior art keywords
- lsi
- lsis
- module
- pads
- electrode extraction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路
（ＬＳＩ）装置に関し、特に複数のＬＳＩを三次元に積
み重ねて高密度化を図ったＬＳＩモジュールとその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (LSI) device, and more particularly to an LSI module in which a plurality of LSIs are three-dimensionally stacked to increase the density and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】近年におけるＬＳＩの高密度化の要求に
より、複数個のＬＳＩを積層して一体化し、かつ相互に
電気接続を行った三次元ＬＳＩモジュールが提案されて
いる。従来、この種の三次元ＬＳＩモジュールとして、
図３、図４に示す構造のものがある。図３の構成は、プ
リント配線板３０の上にＬＳＩの第１チップ３１ａが搭
載され、さらにその上に第２，第３のチップ３１ｂ，３
１ｃが搭載される。そして、第１，第２および第３のチ
ップ３１ａ，３１ｂ，３１ｃのそれぞれの電極取出しパ
ッド３２ａ，３２ｂ，３２ｃとプリント配線板３０上の
電極パッド３２ｄとが相互に金属ワイヤ３３により電気
的に接続される。また、図４の構成は、ＬＳＩチップ４
１ａ，４１ｂをプリント配線板４０に積層状態に搭載し
た上で、これらをフィルムキャリア上に形成したリード
４３により電気的に接続して実現した例である。2. Description of the Related Art In response to recent demands for higher density of LSIs, three-dimensional LSI modules have been proposed in which a plurality of LSIs are stacked and integrated and electrically connected to each other. Conventionally, as this kind of three-dimensional LSI module,
There is a structure shown in FIGS. In the configuration of FIG. 3, the first chip 31a of the LSI is mounted on the printed wiring board 30, and the second and third chips 31b, 3b are further mounted thereon.
1c is mounted. Then, the respective electrode extraction pads 32a, 32b, 32c of the first, second and third chips 31a, 31b, 31c and the electrode pads 32d on the printed wiring board 30 are electrically connected to each other by the metal wires 33. Is done. Further, the configuration of FIG.
This is an example in which 1a and 41b are mounted on a printed wiring board 40 in a laminated state, and are electrically connected by leads 43 formed on a film carrier.
【０００３】しかしながら、これらのモジュール構成で
は、モジュール化する各ＬＳＩ間をリード又はワイヤに
より接続しているため、ＬＳＩチップのサイズに加えリ
ードまたはワイヤのための実装領域が必要となり、実装
密度を高め、かつモジュールの小型化を図る上では有利
ではないという問題がある。この問題を解消するため
に、リードやワイヤを不要にしたリードレス構造が提案
されている。例えば、図５は特開昭５６−５５０６７号
公報に示されている３次元ＬＳＩモジュールの一例であ
る。However, in these module configurations, since each LSI to be modularized is connected by a lead or a wire, a mounting area for the lead or the wire is required in addition to the size of the LSI chip, and the mounting density is increased. In addition, there is a problem that it is not advantageous in reducing the size of the module. In order to solve this problem, a leadless structure which does not require leads and wires has been proposed. For example, FIG. 5 shows an example of a three-dimensional LSI module disclosed in JP-A-56-55067.
【０００４】図５において、ＬＳＩチップ５１ａ，５１
ｂ，５１ｃは積層されてプリント配線板５０に搭載され
ており、各チップはそれぞれに設けられた電極取り出し
パッドが直接的に接続されている。すなわち、ＬＳＩチ
ップ５１ａ上の電極取り出しパッド相当部に形成したア
ルミ層を５００℃以上で上面から輻射加熱することによ
りシリコンとアルミの共晶からなる貫通導電層５５が形
成されており、この導電層５５の表面と裏面にそれぞれ
電極取り出しパッド５２ａ，５２ａ’，５２ｂ，５２
ｂ’，５２ｃ，５２ｃ’が設けられている。モジュール
を構成する各ＬＳＩチップ５１ａ，５１ｂ，５１ｃおよ
びプリント配線板５０間はそれぞれ電極取り出しパッド
５２ａ’と５２ｂ間、５２ｂ’と５２ｃ問、および５２
ｃ’と５４間に設けられた半田バンプ５３ａ，５３ｂ，
５３ｃにより接続されている。In FIG. 5, LSI chips 51a, 51
b and 51c are stacked and mounted on the printed wiring board 50, and each chip is directly connected to an electrode extraction pad provided for each chip. That is, the through conductive layer 55 made of eutectic silicon and aluminum is formed by radiating and heating the aluminum layer formed on the part corresponding to the electrode extraction pad on the LSI chip 51a from the upper surface at 500 ° C. or higher. The electrode extraction pads 52a, 52a ', 52b, 52
b ', 52c and 52c' are provided. Between the LSI chips 51a, 51b, 51c and the printed wiring board 50 constituting the module, between the electrode extraction pads 52a 'and 52b, between 52b' and 52c, and 52, respectively.
solder bumps 53a, 53b provided between c ′ and 54,
53c.
【０００５】[0005]
【発明が解決しようとする課題】この図５の構造であれ
ば前述のリードまたはワイヤのための実装領域が不必要
であるため必要最小限の実装領域で３次元構造のＬＳＩ
モジュールが実現可能となる。しかしながら、モジュー
ルを構成する各ＬＳＩチップの表面と裏面の両方に互い
に電気的に導通した電極取り出しパッドをあらかじめ設
けておく必要があるため、ＬＳＩチップの表面または裏
面にのみ電極取り出しパッドが形成されている一般的な
ＬＳＩチップをそのまま利用してモジュールを構成する
ことはできず、そのために３次元モジュール作成のため
の専用のＬＳＩチップを開発しておく必要があり、その
ための設計、製造が煩雑なものとなり、しかも汎用的な
技術としての利用価値が低いという問題がある。With the structure shown in FIG. 5, an LSI having a three-dimensional structure with a minimum necessary mounting area is unnecessary because the mounting area for the above-mentioned lead or wire is unnecessary.
Module becomes feasible. However, since it is necessary to previously provide electrode extraction pads that are electrically connected to each other on both the front surface and the back surface of each LSI chip constituting the module, the electrode extraction pads are formed only on the front surface or the back surface of the LSI chip. It is not possible to construct a module using a general LSI chip as it is, and it is necessary to develop a dedicated LSI chip for creating a three-dimensional module, and the design and manufacturing for that purpose are complicated. However, there is a problem that the utility value as a general-purpose technology is low.
【０００６】本発明の目的は、一般的なＬＳＩチップを
そのまま使用可能で、かつリードまたはワイヤのための
実装領域を必要としない高密度なＬＳＩモジュールとそ
の製造方法を提供することにある。 ・An object of the present invention is to provide a high-density LSI module which can use a general LSI chip as it is and does not require a mounting area for leads or wires, and a method of manufacturing the same.・
【０００７】[0007]
【課題を解決するための手段】本発明のＬＳＩモジュー
ルは、それぞれ電極取り出しパッドが形成されている複
数個のＬＳＩが積層状態に一体化され、かつ前記電極取
り出しパッド位置において少なくとも２以上のＬＳＩを
貫通する開孔が設けられ、この開孔に充填された導電性
の樹脂で各ＬＳＩの電極取り出しパッドが相互に電気接
続されていることを特徴とする。According to an LSI module of the present invention, a plurality of LSIs each having an electrode extraction pad are integrated in a stacked state, and at least two or more LSIs are arranged at the electrode extraction pad position. A penetrating opening is provided, and an electrode extraction pad of each LSI is electrically connected to each other by a conductive resin filled in the opening.
【０００８】また、本発明のＬＳＩモジュールの製造方
法は、複数個のＬＳＩを、それぞれの電極取り出しパッ
ドを位置決めした状態で積層し、かつこれらを絶縁性の
樹脂により接着して一体化する工程と、前記電極取り出
しパッド位置において前記各ＬＳＩに対して積層方向に
レーザで開孔を開設する工程と、前記開孔内に導電性の
樹脂を充填する工程とを含んでいる。Further, the method of manufacturing an LSI module according to the present invention comprises a step of laminating a plurality of LSIs with respective electrode extraction pads positioned and bonding them with an insulating resin to integrate them. Forming a hole in the LSI in the stacking direction with a laser at the position of the electrode extraction pad, and filling the hole with a conductive resin.
【０００９】[0009]
【発明の実施の形態】次に、本発明の実施形態を図面を
参照して説明する。図１は本発明の３次元構造のＬＳＩ
モジュールの作成途中における断面図、図２はその完成
状態の断面図である。先ず、図１に示すように、モジュ
ールを構成する複数個、ここでは４つのＬＳＩｌ，２，
３，４は、それぞれ従来のＬＳＩと同様に、シリコンチ
ップに所要の素子が形成され、その裏面の複数箇所に前
記素子に接続される配線の一部、或いはこの配線に電気
接続された状態の電極取り出しパッド１ａ，２ａ，３
ａ，４ａが形成される。ここで、この電極取り出しパッ
ド１ａ，２ａ，３ａ，４ａは、少なくともシリコンチッ
プの厚さ方向に重なる位置には素子や他の配線が形成さ
れることがないように、例えばシリコンチップの周辺部
に沿って配列形成される。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an LSI having a three-dimensional structure according to the present invention.
FIG. 2 is a cross-sectional view of the module in the process of being manufactured, and FIG. First, as shown in FIG. 1, a plurality of LSIs constituting a module, here, four LSIs 1, 2,
Reference numerals 3 and 4 denote a state in which a required element is formed on a silicon chip and a part of a wiring connected to the element is provided at a plurality of positions on the back surface of the silicon chip, or a state in which the element is electrically connected to the wiring, similarly to the conventional LSI. Electrode extraction pads 1a, 2a, 3
a, 4a are formed. Here, the electrode take-out pads 1a, 2a, 3a, and 4a are formed, for example, in the peripheral portion of the silicon chip so that elements and other wirings are not formed at least at positions overlapping in the thickness direction of the silicon chip. It is arranged along.
【００１０】そして、これらのＬＳＩ１〜４は、各ＬＳ
Ｉの電極取り出しパッド１ａ〜４ｄが垂直方向に重なる
ように位置合わせされた後、絶縁性の樹脂５，６，７に
より順次積層されるように接着されている。ここで、絶
縁性の樹脂５〜７は、各ＬＳＩｌ〜４の電極取り出しパ
ッド１ａ〜４ａ部に空隙５ａ，６ａ，７ａが残るように
供給されている。この空隙５ａ〜７ａは、例えば、ＬＳ
Ｉ表面の保護膜とは密着性がある一方で、電極取り出し
パッドを構成する金属材との密着性がない絶縁性の樹脂
を利用すれば、ＬＳＩ表面における樹脂の表面張力によ
って容易に形成することが可能である。Each of these LSIs 1 to 4 has a
After the electrode extraction pads 1a to 4d of I are aligned so as to overlap in the vertical direction, they are bonded by insulating resins 5, 6, 7 so as to be sequentially laminated. Here, the insulating resins 5 to 7 are supplied so that the gaps 5a, 6a, and 7a remain in the electrode extraction pads 1a to 4a of the LSIs 1 to 4. The gaps 5a to 7a are, for example, LS
If an insulating resin is used, which has adhesion to the protective film on the surface of the I surface but does not adhere to the metal material forming the electrode extraction pad, it can be easily formed by the surface tension of the resin on the LSI surface. Is possible.
【００１１】次に、図２に示すように、積層されたＬＳ
Ｉの最上のＬＳＩ１の表面または反対側のＬＳＩ４の裏
面にレーザビームを投射し、垂直方向に重なった電極取
り出しパッド１ａ〜４ａの位置に各ＬＳＩ１〜４を貫通
する開孔８を形成する。そして、この開孔８内に導電性
の樹脂９を注入し、この導電性樹脂９により各ＬＳＩｌ
〜４はＬＳＩの積層方向に相互に電気接続する。このと
き、各電極取り出しパッド１ａ〜４ａに対応する部分に
は空隙５ａ〜７ａが設けられているため、この空隙５ａ
〜７ａに導電性の樹脂９の一部が充填され、各ＬＳＩｌ
〜４の電極取り出しパッド１ａ〜４ａでの電気的な接続
を安定させることが可能となる。Next, as shown in FIG.
A laser beam is projected onto the front surface of the LSI 1 at the top of I or the back surface of the LSI 4 on the opposite side, and an opening 8 penetrating through each of the LSIs 1 to 4 is formed at the positions of the electrode take-out pads 1a to 4a vertically overlapping. Then, a conductive resin 9 is injected into the opening 8 and each LSI
Are electrically connected to each other in the stacking direction of the LSI. At this time, since the gaps 5a to 7a are provided in portions corresponding to the respective electrode extraction pads 1a to 4a, the gaps 5a to 7a are provided.
7a are filled with a part of the conductive resin 9, and each LSI
4 can stabilize the electrical connection at the electrode extraction pads 1a to 4a.
【００１２】このように、この構成では、モジュール化
される複数のＬＳＩ１〜４間の接続は導電性の樹脂９の
注入により一括括で行えるため、ＬＳＩを一段ずつ積み
重ねるような方法と比較してモジュール組み立て工数の
削減が可能であり、また、リードやワイヤを配設ための
実装領域を必要としないため、必要最小限の実装領域
（実装面積および実装高さ）で三次元構造のＬＳＩモジ
ュールが実現可能となる。さらに、モジュールを構成す
る各ＬＳＩ１〜４は一般的なＬＳＩチップをそのまま利
用することが可能であり、チップ裏面にも電極取り出し
パッドを設ける等の特別なＬＳＩを設計、製造する必要
もない。As described above, in this configuration, the connection between the plurality of LSIs 1 to 4 to be modularized can be performed collectively by injecting the conductive resin 9, and therefore, compared to a method in which LSIs are stacked one by one. Since the number of steps for assembling the module can be reduced and there is no need for a mounting area for arranging leads and wires, an LSI module having a three-dimensional structure can be realized with a minimum necessary mounting area (mounting area and mounting height). It becomes feasible. Further, each of the LSIs 1 to 4 constituting the module can use a general LSI chip as it is, and there is no need to design and manufacture a special LSI such as providing an electrode extraction pad on the back surface of the chip.
【００１３】ここで、前記実施形態では、ＬＳＩを接着
するための樹脂に空隙を形成しているが、特に空隙を設
けなくとも各電極取り出しパッドの電気接続が可能であ
る。また、前記実施形態では全ての電極取り出しパッド
に対して開孔を開設して導電性樹脂を充填しているが、
選択された電極取り出しパッドに対してのみ、あるいは
開孔の深さを適宜に設定することで選択されたＬＳＩの
電極取り出しパッドに対してのみ導電性樹脂による電気
接続を行うことも可能である。Here, in the above-described embodiment, the void is formed in the resin for bonding the LSI, but the electrical connection of each electrode extraction pad is possible without providing a void. Further, in the above-described embodiment, the openings are opened for all the electrode extraction pads and the conductive resin is filled.
It is also possible to make electrical connection with the conductive resin only to the selected electrode extraction pad or only to the selected LSI electrode extraction pad by appropriately setting the depth of the opening.
【００１４】また、このように構成されたＬＳＩモジュ
ールをプリント配線板に実装する場合には、前記実施形
態の場合には最下層のＬＳＩの電極取り出しパッドに半
田等のバンプを設け、フリップチップ法によりプリント
配線板に実装すれば、より高密度の実装が実現できる。When the LSI module thus configured is mounted on a printed wiring board, in the case of the above-described embodiment, bumps such as solder are provided on electrode extraction pads of the lowermost LSI, and the flip-chip method is employed. Therefore, when mounted on a printed wiring board, higher density mounting can be realized.
【００１５】[0015]
【発明の効果】以上説明したように、本発明のＬＳＩモ
ジュールは、モジュールを構成する各ＬＳＩの電極取り
出し電極を、各ＬＳＩを貫通する開孔内に充填した導電
性の樹脂により相互に電気接続しているため、一般的な
ＬＳＩチップをそのまま使用しての三次元構造のモジュ
ールが構成でき、また、各ＬＳＩ間の接続にはリードま
たはワイヤが不必要であるため必要最小限の実装領域で
モジュール化が実現できるという効果がある。As described above, in the LSI module of the present invention, the electrode extraction electrodes of each LSI constituting the module are electrically connected to each other by the conductive resin filled in the opening penetrating each LSI. Therefore, a module having a three-dimensional structure can be configured by using a general LSI chip as it is, and since a lead or a wire is not required for connection between the LSIs, a minimum mounting area is required. There is an effect that modularization can be realized.
【図１】本発明のＬＳＩモジュールの実施形態の製造途
中の状態を示す断面図である。FIG. 1 is a cross-sectional view showing a state in the course of manufacture of an embodiment of an LSI module of the present invention.
【図２】本発明のＬＳＩモジュールの完成状態を示す断
面図である。FIG. 2 is a sectional view showing a completed state of an LSI module of the present invention.
【図３】従来の３次元構造のＬＳＩモジュールの一例の
断面図である。FIG. 3 is a cross-sectional view of an example of a conventional LSI module having a three-dimensional structure.
【図４】従来の３次元構造のＬＳＩモジュールの他の例
の断面図である。FIG. 4 is a sectional view of another example of an LSI module having a conventional three-dimensional structure.
【図５】従来の３次元構造のＬＳＩモジュールの改善さ
れた例の断面図である。FIG. 5 is a cross-sectional view of an improved example of a conventional LSI module having a three-dimensional structure.
１〜４ ＬＳＩ １ａ〜４ａ 電極取り出しパッド ５〜７ 絶縁性の樹脂 ５ａ〜７ａ 空隙 ８ 開孔 ９ 導電性の樹脂 1-4 LSI 1a-4a Electrode take-out pad 5-7 Insulating resin 5a-7a Void 8 Opening 9 Conductive resin
Claims (5)
ている複数個のＬＳＩが積層状態に一体化され、前記Ｌ
ＳＩには前記電極取り出しパッド位置において少なくと
も２以上のＬＳＩを貫通する開孔が設けられ、この開孔
に充填された導電性の樹脂により前記各ＬＳＩの電極取
り出しパッドが相互に電気接続されていることを特徴と
するＬＳＩモジュール。A plurality of LSIs each having an electrode extraction pad formed thereon are integrated in a stacked state;
An opening is provided in the SI at least at two or more LSIs at the position of the electrode extraction pad, and the electrode extraction pads of each of the LSIs are electrically connected to each other by a conductive resin filled in the opening. An LSI module, characterized in that:
取り出しパッドが設けられており、各ＬＳＩの対応する
電極取り出しパッドが前記導電性の樹脂によりＬＳＩの
積層方向に電気接続されてなる請求項１のＬＳＩモジュ
ール。2. A plurality of LSIs are provided with electrode lead-out pads at the same location on a plane, and the corresponding electrode lead-out pads of each LSI are electrically connected by the conductive resin in the LSI stacking direction. Item 1. The LSI module according to item 1.
される絶縁性の樹脂により接着され、この絶縁性樹脂に
は電極取り出しパッド部位に空隙が形成され、この空隙
内に導電性の樹脂が充填されている請求項１または２の
ＬＳＩモジュール。3. The LSI to be laminated is bonded with an insulating resin interposed between the two LSIs, and a gap is formed in the insulating resin at an electrode extraction pad portion, and a conductive resin is formed in the gap. 3. The LSI module according to claim 1, wherein
出しパッドを位置決めした状態で積層し、かつこれらを
絶縁性の樹脂で接着して一体化する工程と、前記電極取
り出しパッド位置において前記各ＬＳＩに対して積層方
向にレーザで開孔を開設する工程と、前記開孔内に導電
性の樹脂を充填する工程とを含むことを特徴とするＬＳ
Ｉモジュールの製造方法。4. A step of laminating a plurality of LSIs with their respective electrode take-out pads positioned and bonding them with an insulating resin to integrate them, and further comprising the steps of: Forming a hole with a laser in the stacking direction, and filling the hole with a conductive resin.
A method for manufacturing an I module.
部位には存在しないように形成する請求項４のＬＳＩモ
ジュールの製造方法。5. The method for manufacturing an LSI module according to claim 4, wherein the insulating resin is formed so as not to be present at a portion of the electrode extraction pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31946696A JP2871636B2 (en) | 1996-11-29 | 1996-11-29 | LSI module and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31946696A JP2871636B2 (en) | 1996-11-29 | 1996-11-29 | LSI module and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10163411A JPH10163411A (en) | 1998-06-19 |
| JP2871636B2 true JP2871636B2 (en) | 1999-03-17 |
Family
ID=18110524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31946696A Expired - Fee Related JP2871636B2 (en) | 1996-11-29 | 1996-11-29 | LSI module and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2871636B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7977801B2 (en) | 2005-07-15 | 2011-07-12 | Ryo Takatsuki | Integrated circuit chip component, multi-chip module, their integration structure, and their fabrication method |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3875867B2 (en) * | 2001-10-15 | 2007-01-31 | 新光電気工業株式会社 | Method for forming holes in silicon substrate |
| KR100435813B1 (en) * | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | Multi chip package using metal bar and manufacturing method thereof |
| US6867073B1 (en) * | 2003-10-21 | 2005-03-15 | Ziptronix, Inc. | Single mask via method and device |
| DE102004060345A1 (en) * | 2003-12-26 | 2005-10-06 | Elpida Memory, Inc. | Semiconductor device with layered chips |
| US7829438B2 (en) * | 2006-10-10 | 2010-11-09 | Tessera, Inc. | Edge connect wafer level stacking |
| JP5568467B2 (en) | 2008-08-28 | 2014-08-06 | パナソニック株式会社 | Semiconductor device |
| JP2010129958A (en) | 2008-12-01 | 2010-06-10 | Seiko Epson Corp | Semiconductor device, and manufacturing method thereof |
| JP5172751B2 (en) * | 2009-03-19 | 2013-03-27 | 株式会社東芝 | Manufacturing method of three-dimensional stacked semiconductor integrated circuit |
| JP5201048B2 (en) | 2009-03-25 | 2013-06-05 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
-
1996
- 1996-11-29 JP JP31946696A patent/JP2871636B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7977801B2 (en) | 2005-07-15 | 2011-07-12 | Ryo Takatsuki | Integrated circuit chip component, multi-chip module, their integration structure, and their fabrication method |
| US8076179B2 (en) | 2005-07-15 | 2011-12-13 | Ryo Takatsuki | Fabrication method for integrated circuit chip component, multi-chip module, and their integration structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10163411A (en) | 1998-06-19 |
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