JPS59217334A - Annealing method of compound semiconductor substrate - Google Patents
Annealing method of compound semiconductor substrateInfo
- Publication number
- JPS59217334A JPS59217334A JP9276083A JP9276083A JPS59217334A JP S59217334 A JPS59217334 A JP S59217334A JP 9276083 A JP9276083 A JP 9276083A JP 9276083 A JP9276083 A JP 9276083A JP S59217334 A JPS59217334 A JP S59217334A
- Authority
- JP
- Japan
- Prior art keywords
- annealing
- compound semiconductor
- semiconductor substrate
- ion
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000137 annealing Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 150000001875 compounds Chemical class 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 10
- 239000012535 impurity Substances 0.000 claims description 7
- 230000004913 activation Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims description 2
- 230000007547 defect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 abstract description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910002804 graphite Inorganic materials 0.000 abstract description 3
- 239000010439 graphite Substances 0.000 abstract description 3
- 230000029052 metamorphosis Effects 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000000452 restraining effect Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 101100366935 Caenorhabditis elegans sto-2 gene Proteins 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000001766 physiological effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 239000002341 toxic gas Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は化合物半導体基板へのイオン注入プロセスに
おける注入後のアニーリング方法に関スるものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a post-implantation annealing method in an ion implantation process into a compound semiconductor substrate.
超高速素子の構成材としてヒ化ガリウム（ＧａＡａ）結
晶をはじめとする化合物半導体基板が注目を集めている
。ところが、ＧａＡｓは蒸気圧の高い元素で構成されて
おシ、従って、不純物のドーピングは低温で実施せねば
ならない。その意味で、イオン注入技術は高温下での拡
散手法とは異なって大きな利点を有している。また、素
子の高速性を保紅する重要技術の一つに微細加工技術が
あるが、これはドーピング不純物の濃度、プロファイル
を精密制御できるイオン注入技術と組み合わされてはじ
めて二次元、三次元での素子の微細化が達成される。Compound semiconductor substrates including gallium arsenide (GaAa) crystals are attracting attention as constituent materials for ultrahigh-speed devices. However, GaAs is composed of elements with high vapor pressure, and therefore doping with impurities must be carried out at a low temperature. In this sense, ion implantation technology has significant advantages over diffusion methods that operate at high temperatures. In addition, one of the important technologies for maintaining the high-speed performance of devices is microfabrication technology, but this can only be achieved in two and three dimensions by combining it with ion implantation technology that can precisely control the concentration and profile of doping impurities. Miniaturization of elements is achieved.
ところで、化合物半導体基板へ所望のイオンを注入した
後には、これらのイオンを電気的に活性化させることを
主目的として’７００ ℃以上の温度でアニーリングを
施す必要がある。そして、このアニーリングには酸化シ
リコン（ＳｔＯ２） 、窒化シリコ７ （Ｓｉ３Ｎ４）
、酸化７ ルミニウム（Ａ１２ｏａ） ｌ多結晶シリ
コン、酸化ガリウム（Ｇａ２ｏ３） 、 Ｓｉ３Ｎ４＋
８１０゜などの保護膜を化合物半導体基板の主面上に
被着させた状態で行うキャップアニーリング、へ〇加圧
雰囲気で行うキャップレスアニーリング、および水素も
しくは不活性ガスの雰囲気で化合物半導体基板のイオン
注入面を対向密着させた状態で行うグロキシミティ・キ
ャップアニーリングの３種に大別できる。By the way, after desired ions are implanted into a compound semiconductor substrate, it is necessary to perform annealing at a temperature of 700° C. or higher, with the main purpose of electrically activating these ions. For this annealing, silicon oxide (StO2), silicon nitride 7 (Si3N4)
, 7 aluminum oxide (A12oa) l polycrystalline silicon, gallium oxide (Ga2o3), Si3N4+
Cap annealing is performed with a protective film such as 810° coated on the main surface of the compound semiconductor substrate, capless annealing is performed in a pressurized atmosphere, and ion annealing of the compound semiconductor substrate is performed in a hydrogen or inert gas atmosphere. It can be roughly divided into three types: gloximity and cap annealing, which are performed with the implanted surfaces facing each other in close contact.
これらのアニーリング方法はそれぞれ特色があり、利点
も挙げられるか、以下に述べる欠点を有しており、安定
した特性をもつ化合物半導体ＩＣを高歩留りで、生理性
よく得る上で支障をきたしている。たとえばキャップア
ニーリングの場合、通常は保護膜としてスパッタリング
、・プラズマＣｖＤ法などで形成された８１３Ｎ４膜が
よく用いられるが、Ｓｉ３Ｎ。膜の堆積速度、堆積温度
などの膜形成条件、 Ｓｉ３Ｎ４膜中の酸素不純物の挙
動すなわち膜質などの諸パラメータに電気的特性が大き
く依存していることはよく知られている。他の保護膜に
ついても同様であり、これらの保睦膜を被着させた上で
アニーリングされたイオン注入層の特性はこれらの保護
膜の種類、形成方法、膜質などの影響を敏感に受ける。Each of these annealing methods has its own characteristics and has advantages and disadvantages as described below, which hinder the ability to obtain compound semiconductor ICs with stable characteristics at a high yield and with good physiological properties. . For example, in the case of cap annealing, an 813N4 film formed by sputtering, plasma CVD, etc. is usually used as a protective film, but Si3N. It is well known that electrical characteristics are highly dependent on various parameters such as film formation conditions such as film deposition rate and deposition temperature, behavior of oxygen impurities in the Si3N4 film, or film quality. The same holds true for other protective films, and the characteristics of the ion-implanted layer coated with these protective films and annealed are sensitively affected by the type, formation method, film quality, etc. of these protective films.
一方、Ａｓの加圧雰囲気におけるキャップレスアニーリ
ングではＡｓ分圧で活性化率は微妙に変化する。たとえ
ば、マグネシウム（Ｍｇ） 、 ｓｉではＡｓ分圧の増
加で活性化率は増大し、一方イオウ（Ｓ）はＡｓ分圧の
増加で逆に活性化率が減少するという傾向が見られる。On the other hand, in capless annealing in a pressurized As atmosphere, the activation rate changes slightly depending on the As partial pressure. For example, the activation rate of magnesium (Mg) and si increases as the As partial pressure increases, while the activation rate of sulfur (S) tends to decrease as the As partial pressure increases.
また、ＡｓＨ，の加圧雰囲気におけるアニーリングは有
毒ガスを使用するという点で危険を伴い、スループット
の向上が望めない現状である。Furthermore, annealing AsH in a pressurized atmosphere is dangerous because it uses toxic gas, and currently no improvement in throughput can be expected.
以上のような問題点を軽減する方法として、半導体基板
のイオン注入面を対向密着させるプロキシミテイ・キャ
ップアニーリングが挙げられる。One method for alleviating the above-mentioned problems is proximity cap annealing, which brings the ion-implanted surfaces of the semiconductor substrate into close contact with each other.
この方法は上述のような種々の保護膜を形成する必要が
ないので工程を簡略化できる大きな特長を有している。This method has the great advantage of simplifying the process since it is not necessary to form various protective films as described above.
しかし、ＧａＡ３基板全体を均一な熱的環境のもとてア
ニールし、熱変成を極力抑えるとともに変成量のバラツ
キも小さくして、注入イオンの活性化率、移動度など重
要なパラメータを所望の水準に精密制御するうえで以下
に述べる難点をもつ。すなわち、対向させたＧａＡｓ基
板自体がそれぞれキャップの役目を果たすことが必要十
分灸件であるにもかかわらず、ＧａＡｓ基板自身がラン
ダムな反９形状、反り量を有するので、キャップの効果
が完全に発揮できない場合が多い。反りは主に、単結晶
を内周刃ブレードでスライスする際の（イ）ブレードの
湾曲、（ロ）基板の裏表の破砕歪の大小、などが原因で
ある。後者はスライス後の基板をエツチングすることで
矯正可能であるが、前者の場合、反りはラップ以降へも
引継がれる。However, by annealing the entire GaA3 substrate in a uniform thermal environment, thermal metamorphosis is suppressed as much as possible and variation in the amount of metamorphism is also reduced, and important parameters such as activation rate and mobility of implanted ions are kept at desired levels. It has the following difficulties in precise control. In other words, although it is necessary and sufficient that the opposing GaAs substrates themselves play the role of caps, the effect of the caps is not completely effective because the GaAs substrates themselves have a random anti-9 shape and a warped amount. It is often not possible to perform. Warpage is mainly caused by (a) the curvature of the blade when slicing the single crystal with the inner peripheral blade, and (b) the magnitude of crushing strain on the front and back surfaces of the substrate. The latter can be corrected by etching the substrate after slicing, but in the former case, the warpage is carried over to the subsequent layers.
第１図はこのような従来方法（こよるグロキシミテイ・
キャップアニーリングの状況を示す側断面図である。グ
ラファイトボー） （１１の上に一対の化合物半導体基
板（２）および（３）がそれぞれのイオン注入面（ａ）
および（ｂ）を対向させて載置されている。割基板（２
１、（３１ともに反りの形状がイオン注入面（ａ）。Figure 1 shows such a conventional method (such as gloximity).
FIG. 3 is a side cross-sectional view showing the state of cap annealing. (graphite bow) (A pair of compound semiconductor substrates (2) and (3) are placed on each ion implantation surface (a)
and (b) are placed facing each other. Split board (2
1 and (31), the warped shape is the ion implantation surface (a).
（ｂ）が凸形状になるような状態であるので、イオン注
入面（ａ） 、 （ｂ）の周縁部はアニール炉雰囲気に
露出されており、前述のような化合物半導体基板（２Ｉ
。Since (b) is in a convex shape, the peripheral edges of the ion-implanted surfaces (a) and (b) are exposed to the annealing furnace atmosphere.
.
（３）自身によるキャップ効果が著しく損われることは
図から明らかである。(3) It is clear from the figure that the self-capping effect is significantly impaired.
この発明は以上のような点に鑑みてなされたもので、化
合物半導体基板の鏡面研摩されイオン注入された主面が
凹状態になるように反った形状のもの同志を互いにその
主面を対向させてアニーリングすることによってキャッ
プ効果を損うことのないグロキシミテイ・キャップアニ
ーリング方法を提供するものである。This invention has been made in view of the above points, and involves the use of compound semiconductor substrates having mirror-polished and ion-implanted main surfaces that are curved so that they are in a concave state, with their main surfaces facing each other. The object of the present invention is to provide a gloximity cap annealing method that does not impair the cap effect by annealing.
第２図はこの発明の一実施例によるアニーリング状況を
示す側断面図で、グラファイトボート（ｌ）の上に、そ
れぞれ鏡面研摩されイオン注入された主面（、）および
（ｄ）が凹状態になった一対の化合物半導体基板（４）
および（５）を上記主面（Ｃ）および（ｄ）が対向する
ように重ねて載置されている。このような状態でアニー
リングすることによってイオン注入された主面（Ｃ）
、 （ｄ）はアニール炉雰囲気から隔離されているので
、キャップ効果は十分発揮され、基板面内での不均一な
熱変成を抑えることが可能となリ、電気的特性のバラツ
キの少ない化合物半導体素子を高歩留りで生産できる。FIG. 2 is a side cross-sectional view showing the annealing situation according to an embodiment of the present invention, in which the main surfaces (,) and (d), which are mirror-polished and ion-implanted, are in a concave state on the graphite boat (l). A pair of compound semiconductor substrates (4)
and (5) are placed one on top of the other so that the main surfaces (C) and (d) face each other. The main surface (C) where ions were implanted by annealing in this state
, (d) is isolated from the annealing furnace atmosphere, so the capping effect is fully exerted, and it is possible to suppress uneven thermal transformation within the substrate surface.It is a compound semiconductor with little variation in electrical properties. Devices can be produced with high yield.
なお、基板の反り形状の制御は、スライス時におけるダ
イヤモンドブレードの張力調整、偏心の微調、またはラ
ッピング時でのラップ盤の平坦度。The warped shape of the substrate can be controlled by adjusting the tension of the diamond blade during slicing, finely adjusting the eccentricity, or the flatness of the lapping machine during lapping.
ラップ量、荷重などを最適にすれば所望の凹形状の反り
を有する化合物半導体基板を得ることができる。By optimizing the amount of wrap, load, etc., it is possible to obtain a compound semiconductor substrate having a desired concave warpage.
以上説明したように、この発明では化合物半導体基板の
プロキシミティ・キャップアニーリングにおいて、鏡面
研摩されイオン注入された主面が凹状態になるように反
った基板を互いに上記主面を対向させてアニーリングす
るようにしたので、キャップ効果を損うことなく良好な
アニーリングが可能である。As explained above, in the proximity cap annealing of compound semiconductor substrates in the present invention, substrates that have been mirror-polished and ion-implanted are warped so that their main surfaces are in a concave state, and the substrates are annealed with their main surfaces facing each other. This allows for good annealing without impairing the cap effect.
第１図は従来方法によるプロキシミテイ・キャップアニ
ーリングの状況を示す側断面図、第２図はこの発明の一
実施例によるアニーリング状況を示す側断面図である。
図において、（１）はグラファイトポー） 、（４）
、 （Ｆｉｔは化合物半導体基板、（ｃ） 、 （ｄ）
はイオン注入主面である。
図中同一符号は同一または和尚部分を示す。
代理人 大岩増雄FIG. 1 is a side sectional view showing the proximity cap annealing according to a conventional method, and FIG. 2 is a side sectional view showing the annealing according to an embodiment of the present invention. In the figure, (1) is graphite powder), (4)
, (Fit is a compound semiconductor substrate, (c), (d)
is the main surface for ion implantation. The same reference numerals in the drawings indicate the same or Buddhist parts. Agent Masuo Oiwa
Claims (1)
物イオンを注入し、次いで上記不純物イオンの注入に伴
う結晶欠陥などの損傷を減少させるとともに、上記不純
物イオンを上記基板の結晶格子の置換位置に入れ電気的
に活性化するためのアニーリングを施すに際して、鏡面
研摩された上記不純物イオン注入側の主面が凹面状態に
なるように反った一対の上記基板を上記主面が互いに対
向するように重ねて不活性ガスまたは水素ガス雰囲気中
でアニールすることを特徴とする化合物半導体基板のア
ニーリング方法。(1) A desired impurity ion is implanted into one main surface of a compound semiconductor substrate, and then damage such as crystal defects caused by the implantation of the impurity ion is reduced, and the impurity ion is placed at a replacement position in the crystal lattice of the substrate. When annealing is performed for electrical activation, the pair of mirror-polished substrates, which are warped so that the impurity ion-implanted main surfaces are concave, are placed so that their main surfaces face each other. A method for annealing compound semiconductor substrates, which comprises stacking and annealing in an inert gas or hydrogen gas atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9276083A JPS59217334A (en) | 1983-05-24 | 1983-05-24 | Annealing method of compound semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9276083A JPS59217334A (en) | 1983-05-24 | 1983-05-24 | Annealing method of compound semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59217334A true JPS59217334A (en) | 1984-12-07 |
Family
ID=14063378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9276083A Pending JPS59217334A (en) | 1983-05-24 | 1983-05-24 | Annealing method of compound semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59217334A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4830987A (en) * | 1987-11-19 | 1989-05-16 | Texas Instruments Incorporated | Contactless annealing process using cover slices |
| JP2016115868A (en) * | 2014-12-17 | 2016-06-23 | 富士電機株式会社 | Method of manufacturing semiconductor device |
-
1983
- 1983-05-24 JP JP9276083A patent/JPS59217334A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4830987A (en) * | 1987-11-19 | 1989-05-16 | Texas Instruments Incorporated | Contactless annealing process using cover slices |
| JP2016115868A (en) * | 2014-12-17 | 2016-06-23 | 富士電機株式会社 | Method of manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6064081A (en) | Silicon-germanium-carbon compositions and processes thereof | |
| US20240022229A1 (en) | Composite substrate | |
| US4615766A (en) | Silicon cap for annealing gallium arsenide | |
| CA1253263A (en) | Back sealing of silicon wafers | |
| US4662956A (en) | Method for prevention of autodoping of epitaxial layers | |
| JP3454033B2 (en) | Silicon wafer and manufacturing method thereof | |
| US6436846B1 (en) | Combined preanneal/oxidation step using rapid thermal processing | |
| EP0209648B1 (en) | Wafer base for silicon carbide semiconductor device | |
| JPS59217334A (en) | Annealing method of compound semiconductor substrate | |
| EP0982764A2 (en) | Method of forming a gate oxide layer for transistors | |
| JP3344205B2 (en) | Method for manufacturing silicon wafer and silicon wafer | |
| JPH0473930A (en) | Substrate for heteroepitaxial growth | |
| JPS6226569B2 (en) | ||
| JPS6130030A (en) | Method of annealing multi-element semiconductor | |
| JPH0143454B2 (en) | ||
| JPS63291897A (en) | Method for growing single crystal membrane | |
| JPH09266175A (en) | Semiconductor wafer manufacturing method and semiconductor wafer | |
| JPS60193332A (en) | Method of annealing compound semiconductor substrate | |
| JPS59141221A (en) | Annealing method of compound semiconductor substrate | |
| JPH097907A (en) | Wafer having rear face polysilicon and its manufacturing method | |
| JPS6022316A (en) | Manufacture of compound semiconductor apparatus | |
| JPS60121725A (en) | Annealing method for ion-implanted compound semiconductor device | |
| TW202344699A (en) | Production method for single crystal semiconductor film, production method for multilayer film of single crystal semiconductor film, and semiconductor element | |
| JPS63271923A (en) | Heat treatment of compound semiconductor substrate | |
| JPH04188720A (en) | Etching of vapor growth susceptor |