JPS59214329A - Majority decision circuit - Google Patents

Majority decision circuit

Info

Publication number
JPS59214329A
JPS59214329A JP8935283A JP8935283A JPS59214329A JP S59214329 A JPS59214329 A JP S59214329A JP 8935283 A JP8935283 A JP 8935283A JP 8935283 A JP8935283 A JP 8935283A JP S59214329 A JPS59214329 A JP S59214329A
Authority
JP
Japan
Prior art keywords
address
bits
majority decision
output data
majority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8935283A
Other languages
Japanese (ja)
Inventor
Yoshiharu Yamazaki
山「ざき」　吉晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8935283A priority Critical patent/JPS59214329A/en
Publication of JPS59214329A publication Critical patent/JPS59214329A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the size and power consumption of a device by replacing parts of a full adder and a numeral comparator in an ROM with the 1st output data showing that the number of bits ''1'' among N bits of each address is larger than a specific majority majority decision threshold value in the address and with the 2nd output data showing the number of bits ''1'' in each address is smaller in the address. CONSTITUTION:The 2nd output data DiDo=00 showng that the number of bits ''1'' among eight bits of an address is smaller than the majority decision threshold value ''4'' is stored in the address, the 1st output data DiDo=01 showing that the number of bits ''1'' in an address is smaller than the majority decision threshold value ''4'' is stored in the address, and the 3rd output data DiDo=10 showing that the number of bits ''1'' in an address is equal is stored in the address respectively. Consequently, the ROM9 outputs the 1st, the 2nd, and the 3rd data ''01'', ''00'', and ''10'' as majority decision result signals 6 and 7 when signals containing bits ''1'' more and less than and equal to the majority decision threshold value ''4'' are inputted as a decision object signal 1.

Description

【発明の詳細な説明】 この発明は、例えばディジタル伝送路において冗長性を
持たせた複数ビットから多数決によりそのデータを復号
するような場合に使用される、多数決判定回路に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a majority decision circuit used when, for example, data is decoded by majority decision from a plurality of redundant bits in a digital transmission path.

従来、この種の装置として第１図に示すものがあった。Conventionally, there has been a device of this type as shown in FIG.

図において、１は多数決判定されるＮビットのディジタ
ルビットパターン、２はパターンｌ内のピント「１」の
数を積算する全加算器、３はそのバイナリ出力、４はバ
イナリで与えられる多数決判定闇値、　　５ｔよ比較器
、６．７は比較器５からの多数決判定結果信号である。In the figure, 1 is an N-bit digital bit pattern that is judged by majority decision, 2 is a full adder that adds up the number of focus "1"s in pattern l, 3 is its binary output, and 4 is a majority decision pattern given in binary. The value 5t of the comparator and 6.7 is the majority decision result signal from the comparator 5.

第２図は第１図の回路動作を説明するためのもので、図
において１は８ビツトの被判定信号、３は被判定信号１
の内の「１」の個数を積算した４ビットバイナリ値、４
は外部より４ビツトバイナリ値で与えられる多数決判定
闇値、６．７は２ビツトの多数決判定結果信号、８ａ〜
８ｇは全加算器である。Figure 2 is for explaining the circuit operation of Figure 1. In the figure, 1 is the 8-bit signal to be determined, and 3 is the signal to be determined 1
4-bit binary value, which is the sum of the number of "1"s in 4
is the majority decision dark value given externally as a 4-bit binary value, 6.7 is the 2-bit majority decision result signal, 8a~
8g is a full adder.

次に第２図に従って動作について説明する。Next, the operation will be explained according to FIG.

その加算値が全加算器８ｇに入力され、全加算器８ｇか
らは８ビツトの入力データ１に何個の「１」が存在する
かを示すデータがバイナリ値３として出力される。今、
入力信号１は８ビツトであるからバイナリ値３の出力範
囲ば０から８までの値となる。そしてこの出力信号３は
４ビツトの比較器５に入力される。またこの比較器５の
もう一方の入力には多数決判定閾値４がバイナリで入力
されており、この２僅の比較結果が２ビツトの多数決判
定結果信号６．７として出力される。第３図は多数決判
定結果を示したものである。The added value is input to the full adder 8g, and the full adder 8g outputs data as a binary value 3 indicating how many "1"s are present in the 8-bit input data 1. now,
Since the input signal 1 is 8 bits, the output range of the binary value 3 is from 0 to 8. This output signal 3 is then input to a 4-bit comparator 5. Moreover, the majority decision threshold 4 is input in binary form to the other input of the comparator 5, and the result of this 2-bit comparison is output as a 2-bit majority decision result signal 6.7. FIG. 3 shows the majority decision result.

従来の多数決判定回路は以上のように構成されているの
で、被判定信号のビット数Ｎが増大するに従って多数の
全加算器を必要とし、装置の占有するスペースが大きく
なるという欠点があった。Since the conventional majority decision circuit is configured as described above, it has the disadvantage that as the number of bits N of the signal to be decided increases, a large number of full adders are required, and the space occupied by the device increases.

この発明は上記のような従来のものの欠点を除去するた
めになされたもので、全加算器と数値比較器（第２図の
８ａ〜８ｇと５に相当する部分）とを、各アドレスＮビ
ット中ビット“１”の個数が所定の多数決判定闇値より
多いアドレスには多い旨を示す第１の出力データを、上
記多数決判定闇値より少ないアドレスには少ない旨を示
す第２−出力データを２等しいアドレスには等しい旨を
示す第３の出力データを記憶しているＲ　ＯＭ　（Ｒｅ
ａｄＯｎｌｙ　　Ｍｅｍｏｒｙ）に置換えることにより
、使用する回路素子の数を大幅に減少できる多数決判定
回路を提供することを目的としている。This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it uses a full adder and a numerical comparator (corresponding to 8a to 8g and 5 in FIG. 2) for each address N bits. First output data indicating that the number of middle bits "1" is greater than a predetermined majority judgment dark value is outputted to an address indicating that the number is large, and second output data indicating that the number of medium bits "1" is smaller than the majority judgment darkness value is provided to an address indicating that the number is small. ROM (Re
The purpose of the present invention is to provide a majority decision circuit that can significantly reduce the number of circuit elements used by replacing it with adOnly Memory.

以下、この発明の一実施例を図について説明する。第４
図において、１，６．７は第２図と同じものを示し、９
は２ビツト×２５６ワードのＲＯＭで、これは各アドレ
スに多数決判定信号として使用する出力データを記憶し
ているものである。An embodiment of the present invention will be described below with reference to the drawings. Fourth
In the figure, 1, 6.7 indicates the same as in Figure 2, and 9
is a 2 bit x 256 word ROM which stores output data used as a majority decision signal at each address.

次に動作について説明する。８ビツトの被判定信号１は
、ＲＯＭ９のアドレスラインに入力される。ＲＯＭ９に
は８ビツトの被判定信号１がとりうる全での場合、！Ｉ
］ち２＝２５６通りについである規則に従って出力デー
タが記憶されており、その出力データ６，７を多数決判
定信号として使用できる。Next, the operation will be explained. The 8-bit signal to be determined 1 is input to the address line of the ROM 9. In ROM 9, there are all possible 8-bit signals to be determined 1! I
] Output data is stored according to a certain rule in 2=256 ways, and the output data 6 and 7 can be used as a majority decision signal.

その場合のＲＯＭ９には予め記憶させておくメモリパタ
ーンの一例を第５図に示す。FIG. 5 shows an example of a memory pattern that is stored in advance in the ROM 9 in that case.

このメモリパターンは第４図の装置が第２図の装置と全
く等価に動作するためのものである。即ち、アドレス８
ビツトの内ビット「１」の個数が多数決判定闇値「４」
より少ない番地については少ない旨を示す第２の出力デ
ータＤ１Ｄｏ−００を記憶させ、アドレス８ビツトの内
ビット「１」の個数が多数決闇値「４」より多い番地に
ついては多い旨を示す第１の出力データＤｉＤｏ＝０１
を、また等しい番地には等しい旨を示す第３の出力デー
タＤｉＤｉｉ＝１０をそれぞれ記憶させておく。This memory pattern is used so that the device of FIG. 4 operates in exactly the same manner as the device of FIG. 2. That is, address 8
The number of bits “1” among the bits is the majority decision value “4”
For addresses with a smaller number, the second output data D1Do-00 indicating that the number is smaller is stored, and for addresses where the number of bits "1" among the eight bits of the address is greater than the majority decision value "4", the first output data D1Do-00 indicating that the number is large is stored. Output data DiDo=01
and third output data DiDii=10 indicating equality is stored at the same address.

その結果ＲＯＭ９は被判定信号１として８ビツト中ビツ
ト“１”の個数が多数決判定闇値「４」よりも多い、少
ない９等しいものがそれぞれ入力されたときに、第１．
第２．第３の出力データ「０１Ｊ、ｒｏｏＪ、ｒｌＯＪ
を多数決判定結果信号６，７として出力することとなる
。As a result, the ROM 9 inputs the signal to be judged 1 when the number of bits "1" out of 8 bits is greater than or less than the majority judgment value "4" and equal to 9, respectively.
Second. Third output data “01J, rooJ, rlOJ
will be output as majority decision result signals 6 and 7.

以上のように、この発明によれば、全加算器。As described above, according to the present invention, a full adder is provided.

及び数値比較器の部分を、各アドレスＮビット中ビット
“１”の個数が所定の多数決判定闇値より多いアドレス
には多い旨を示す第１の出力データを、上記多数決判定
闇値より少ないアドレスには少ない旨を示す第２の出力
データを２等しいアドレスには等しい旨を示す第３の出
力データを記憶しているＲＯＭに置換えるようにしたの
で、装置の小形化、低電力化が可能となる効果がある。and the numerical comparator part, for addresses where the number of bits "1" among N bits of each address is greater than the predetermined majority decision dark value, the first output data indicating that the number is greater than the predetermined majority decision dark value; Since the second output data indicating that the address is less than 2 is replaced by the ROM that stores the third output data indicating that the address is equal to 2, it is possible to downsize the device and reduce power consumption. This has the effect of

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の多数決判定回路を示す構成図。 第２図は従来装置の具体例を示す構成図、第３図は多数
決判定基準の一例を示す図、第４図は本発明の一実施例
による多数決判定回路を示す構成図。 第５図は本発明に使用するＲＯＭの記憶パターン例を示
す図である。 図中、１は被判定信号、６，７は多数決判定結果信号、
９はＲＯＭ　（読出し専用メモリ）である。 なお図中同一符号は同−又は相当部分を示す。 代理人　大岩増雄 第１図 第２図 （ＪＵ　　］　Ｏ 第３図 第４図FIG. 1 is a block diagram showing a conventional majority decision circuit. FIG. 2 is a block diagram showing a specific example of a conventional device, FIG. 3 is a diagram showing an example of majority decision criteria, and FIG. 4 is a block diagram showing a majority decision circuit according to an embodiment of the present invention. FIG. 5 is a diagram showing an example of a storage pattern of a ROM used in the present invention. In the figure, 1 is the signal to be determined, 6 and 7 are majority determination result signals,
9 is a ROM (read only memory). Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 2 (JU] O Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] （１）Ｎビットの各アドレスに対し各アドレスＮビット
中ピント“ｌ”の個数が所定の多数決判定闇値より多い
アドレスには多い旨を示す第１の出力データを、上記多
数決判定闇値より少ないアドレスには少ない旨を示す第
２の出力データを、等しいアドレスには等しい旨を示す
第３の出力データを記憶している読出し専用メモリがら
なり、Ｎピッ゛トの被判定信号がアドレス入力され上記
第１ないし第３の出力データのいずれかを出力すること
を特徴とする多数決判定回路。(1) For each address of N bits, the first output data indicating that the number of focus “l”s in each address N bits is greater than the predetermined majority decision dark value is calculated from the majority decision dark value. It consists of a read-only memory that stores second output data indicating that there are fewer addresses for fewer addresses and third output data that indicates that they are equal for equal addresses. and outputs any one of the first to third output data.
JP8935283A 1983-05-19 1983-05-19 Majority decision circuit Pending JPS59214329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8935283A JPS59214329A (en) 1983-05-19 1983-05-19 Majority decision circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8935283A JPS59214329A (en) 1983-05-19 1983-05-19 Majority decision circuit

Publications (1)

Publication Number Publication Date
JPS59214329A true JPS59214329A (en) 1984-12-04

Family

ID=13968312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8935283A Pending JPS59214329A (en) 1983-05-19 1983-05-19 Majority decision circuit

Country Status (1)

Country Link
JP (1) JPS59214329A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6243215A (en) * 1985-08-21 1987-02-25 Matsushita Electric Ind Co Ltd Synchronization detecting circuit containing majority deciding function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6243215A (en) * 1985-08-21 1987-02-25 Matsushita Electric Ind Co Ltd Synchronization detecting circuit containing majority deciding function

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